Access provided by Autonomous University of Puebla. Download to read the full chapter text
Chapter PDF
Keywords
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
References
Moore, G. E. “Progress in digital integrated electronics”, IEDM Tech. Digest, 1975, 11-13.
Semiconductor Industry Association, International Roadmap for Semiconductors, 2004, (available at http://public.itrs.net/)
GENESISe-ISE, User manual, ver. 10. 0, ISE Zurich, 2004.
Lee, K.; Shur, M.; Ejeldly, T. A.;Ytterdal, T. Semiconductor Device Modeling for VLSI. Englewood Cliffs: Prentice Hall, 1993.
Schenk, A. Advanced Physical Models for Silicon Device Simulation. New York: Springer Wien, 1998.
Jungeman, C.; Meinerzhagen, B. Hierarchical Device Simulation. NewYork: Springer Wien, 2003.
De Man, H. “Demands on Microelectronics Education and Research in Post - PC Area”, Proceedings of the 3rd EWME. Dordrecht: Kluwer Academic Publishers, 2000, 9-14.
Grasser, T.; Jungemann, C.; Kosina, H.; Meinerzhagen, B.; Selberherr, S. “Advanced transport models for sub-micrometer devices”, In Simulation of Semiconductor Pro-cesses and Devices. Wien: Springer-Verlag, 2004, 1-8.
Rainey, V. P. “Beyond technology - renaissance engineers”, IEEE Trans. Education, 2002, 45, 4-5.
Miura-Mattausch, M.; Mattausch, H. J.; Arora, N. D.;Yang, C. Y. “MOSFET modelling gets physical”, IEEE Circuits and Devices, 2001, 17, 29-36.
Simulation of Semiconductor Processes and Devices 2004, G. Wachutka and G. Schrag, Eds. Wien, New York: Springer-Verlag, 2004.
Zechner, C. et al. “New Implantation Tables for B, BF2, P, As, In and Sb”, 14th International Conference on Ion Implantation Technology Proceedings. New Mexico, USA: Taos, 2002, 567-570.
Ryssel, H.; Krüger, W.; Lorenz, J. “Comparison of Monte-Carlo simulations and ana-lytical models for the calculation of implantation profiles in multilayer targets”, Nucl. Instrum. and Meth., 1987, B12(20), 40-44.
DIOS - ISE, User manual, ver. 10. 0, ISE Zurich, 2004.
Wachutka, G. “An extended thermodynamic model for the simultaneous simulation of the thermal and electrical behavior of semiconductor devices”, In Proc. Sixth Int. NASECODE Conf., J. J. H. Miller, Ed., Boole Press Ltd., 1989, pp. 409-414.
Apanovich, Y.; Lyumkis, E.; Polsky, B.; Shur, A.; Blakey, P. “Steady-state and transient analysis of submicron devices using energy balance and simplified hydrodynamic models”, IEEE Trans. CAD, 1994, 13, 702-710.
DESSIS - ISE, User manual, ver. 10. 0, ISE Zurich, 2004.
Donoval, D.; Chvala, A.; Vrbicky, A. “Computer Aided Analysis of the Parasitic Prop-erties of a Bipolar Transistor Cell”, Proc. 5th EWME. Dordrecht: Kluwer Academic Publishers, 2004, 153-158.
Menozzi, et al. “Layout dependence of CMOS latch up”, IEEE Trans. Electron Dev., 1989, 36, 1892-1901.
Ker, M. D.; Lo, W. Y.; Wu, C. Y. “New Experimental Methodology to Extract Compact Layout Rules for Latch up Prevention in Bulk CMOS IC’s”, Custom Integrated System Conf., 1999, 143-146.
IC Latch Up Test, EIA/JEDEC Standard No. 78, Electronic Industries Association, 1997.
Contiero, C.;Andreini, A.; Galbiati, P. “Roadmap Differentiation and Emerging Trends in BCD Technology”, Proc. 32nd Euro. Solid State Research Conference (ESSDERC). Italy: Firenze, 2002, 459-462.
Kawamoto, K.; Takahashi, S.; Fujino, S.; Shirakawa, I. “A no snapback LDMOSFET with automotive ESD endurance”, IEEE Trans. Electron Dev., 2002, 49, 2047-2053.
Constapel, R.; Shekar, M. S.; Williams, R. K. “Unclamped inductive switching of inte-grated quasi-vertical DMOSFETs”, IEEE Trans. Electron Dev., 1996, 219-222.
Pinardi, K.; Heinle, U.; Bengtsson, S.; Olsson, J.; Colinge, J. P. “Electrothermal simu-lations of high-power SOI vertical DMOS transistor with lateral drain contacts under unclamped inductive switching test”, Solid State Electron, 2004, 48, 1119-1126.
Donoval, D.; Vrbicky, A. “Analysis of the Electrical and Thermal Properties of Power DMOS Devices during UIS Supported by 2-D Process and Device Simulation”, Proc. ASDAM, 2004, 211-214. Smolenice 2004.
Izaca Deckelmann, A.; Wachutka, G.; Hirler, F.; Krumrey, J.; Henninger, R. “Failure of Multiple-Cell Power DMOS Transistor inAvalanche Operation”, Proc. 33rd European Solid State Res. Conf. (ESSDERC). Portugal: Estoril, 2003, 323-326.
Fischer, K.; Shenai, K. “Dynamics of power MOSFET switching under unclamped inductive loading conditions”, IEEE Trans. Electron Dev., 1996, 43, 1007-1015.
Fischer, K.; Shenai, K. “Electrothermal effects during unclamped inductive switching (UIS) of power MOSFET’s”, IEEE Trans. Electron Dev., 1997, 44, 874-878.
D’Arcangelo, E. et. al. “Experimental characterization of temperature distribution on power MOS devices during unclamped inductive switching”, Microelectronics & Reliability, 2004, 13851455-1459.
Chien, F. et. al. “High ruggedness power MOSFET design by self-align p+ process”, IEICE Trans. Electron, 2005 E88-C(4), 694-698.
Nassif-Khalil, S. G.; Salama, C. A. T. “Super junction LDMOSFET on a silicon-on sapphire substrate”, IEEE Trans. Electron Dev., 2003, 50, 1385-1391.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer
About this chapter
Cite this chapter
Donoval, D., Vrbicky, A., Chvala, A., Beno, P. (2006). 2/3-D process and device simulation. An effective tool for better understanding of internal behavior of semiconductor structures. In: GRABINSKI, W., NAUWELAERS, B., SCHREURS, D. (eds) TRANSISTOR LEVEL MODELING FOR ANALOG/RF IC DESIGN. Springer, Dordrecht. https://doi.org/10.1007/1-4020-4556-5_1
Download citation
DOI: https://doi.org/10.1007/1-4020-4556-5_1
Publisher Name: Springer, Dordrecht
Print ISBN: 978-1-4020-4555-4
Online ISBN: 978-1-4020-4556-1
eBook Packages: EngineeringEngineering (R0)