Introduction

The internet is going through a new stage in which billions of smart objects, “things” that sense and interact with the physical world, are connected in homes, industries, hospitals, cities, farms, etc. These connected objects-the Internet of Things (IoT), are bringing about a paradigm shift in services, infrastructure, and consumer industries. It brings extraordinary possibilities for improvements in various domains like smart cities and grids, healthcare, wearable devices, robotic systems, and numerous other systems. IoT is gradually becoming an integral part of personal as well as professional lives for betterment. IoT brings improvements in connectivity, efficiency, convenience, conversations, and much more. While IoT benefits are undeniable, it is a double-edged sword. An IoT ecosystem is constantly subjected to changes and security threats at various levels—device, data transmission, and data storage within the systems and its applications.

IoT environment is a paradigm that works together, is aware, intelligent, and has a specific purpose. With the increased commercialization of this environment, society is growing more connected with the IoT infrastructure—making it more susceptible to various vulnerabilities. Security vulnerabilities in the IoT domain have intensified potential threats and attacks that can potentially compromise critical infrastructures and national security, causing physical and financial losses.

McAfee’s quarterly threat report exposed 176 new cyber-threats every minute [1]. Mirai-botnet-based recent DDoS attack on low-cost IoT devices infected over 2.5 million devices within just four months [1]. FDA found St Jude Medical’s implantable cardiac devices have vulnerabilities [2] and recalled 465,000 Pacemakers. In [3], the authors demonstrated an attack using popular Philips Hue smart lamps that can impact the IoT infrastructure on a mass scale. Side channel attacks on devices like smart card and mobile phones are rising [4, 5]. Another prominent example affecting billions of IoT devices is the Bluetooth low-energy communication protocol could potentially expose user data [6]. This protocol is used in many wearable and industrial IoT devices.

This scale of the impact is potentially expected to grow extensively with the increasing volume of IoT devices (29 billion in 2022). Traditionally, IoT devices allocate resources like energy and computation for the functionality, and incorporating security becomes very challenging [7]. With the short time-to-market and fierce competition among companies, security has become an afterthought [8] and has not been prioritized as a crucial metric. The security aspect is the primary concern in the IoT realm for deployment. Unlike in the traditional internet, where threats affect the digital world, attacks on IoT would directly impact the physical world. IoT’s future will rely on the ability to secure hard-to-secure, resource-sparse devices effectively. As IoT solutions are becoming prevalent in day-to-day life, attackers have found new opportunities to exploit the lack of built-in security.

This work addresses unified countermeasures for side-channel attacks, specifically for IoT devices. As the existing countermeasures for the physical attacks in IoT are limited to the applications, algorithms, platforms, and hardware specifics, there is a need to rethink the trusted environment to incorporate the security against these attacks. With this motivation, we propose to utilize 3D integration [9] for building the IoT devices as it offers a natural defence against physical attacks, heterogeneity, small form factor, and reduced power dissipation.

To the best of our knowledge, this is the first survey that addresses unified countermeasures in IoT and also describe the 3D integration features that can benefits to design reliable and secure IoT devices. The rest of this paper is organized as follows. “Preliminaries” briefly introduces security concerns in IoT, Three-dimensional (3D) integrated circuits in context to IoT, and hardware attacks. “Generic Countermeasures Against Side-Channel Attacks” discusses generic countermeasures for the selected side-channel attacks. In “Resilience Against Physical Attacks in IoT” , the defense methods specific to IoT against SCA are introduced. The unified approaches unique to the SCA attacks are discussed in “Unified Countermeasures for IoT”. “3D Integration as an Key Enabling Technology for IoT Devices” provides the different aspects of utilizing 3D integration for IoT systems and approaches to designing secure IoT devices using 3D ICs. Finally, “Conclusion”, concludes the paper.

Preliminaries

This section provides basic knowledge about the security concerns in the IoT realm and existing hardware attacks that can threaten the IoT infrastructure. It also provides background knowledge for the reader associated with 3D integrated circuits to understand section 6 effectively.

Security Concerns in IoT

As argued by many researchers, IoT will be the main component of the next era in computing. The network of smart devices-internet-enabled embedded systems is not limited to sensors and actuators but is a wide complex system from home appliances to smart cities and hospitals. The current state of IoT devices, for short, is challenging traditional security protocols. Many IoT designs prioritize keeping devices small in size, battery, and computation power, making traditional security methods unsuitable. It is currently causing a tug of war between having good security on your device or having a good performance at a low price. This fray in security affects IoT devices to be vulnerable to side-channel attacks. There are many published research that discussed IoT security and challenges facing IoT devices [10,11,12]. Most of the survey papers focus on secure IoT infrastructure creation and implementation, authentication, trust management, and attack in different IoT layers. Also, the survey related to the lightweight cryptographic algorithms is presented in [13, 14] for IoT applications. However, there is a lack of surveys that mainly discuss the side-channel attacks and respective countermeasures in the IoT domain.

The very nature of IoT devices means data are constantly being transmitted, processed, and collected in the cloud. Research shows many IoT infected devices have little to no security protections [15]. IoT can become more secure through cryptography for communication between the physical and cyber worlds. Some IoT devices have embedded cryptographic cores for authentication and information processing. However, a prominent attack method-physical side-channel attack (SCA), that breaks an encryption system’s security by exploiting the information leaked from the physical devices is a rising threat in IoT [16, 17]. Current IoT studies show that adversaries can easily acquire side-channel information, which is hard to detect because leakages are inevitable [18]. Side channels in IoT systems may arise from timing information, sensor data, or traffic rates between devices prevalent in our everyday lives. Further, having easy network connectivity as an intrinsic feature, these IoT devices have become lucrative targets for attackers.

Hardware Attacks

The emerging hardware threats arise because of globalized IC supply chain. There are multiple stages within the supply chain that can be manipulated by potential adversary in certain ways to perform the attacks. These diverse hardware attacks can be broadly classified in the following categories.

IP Piracy

Intellectual property (IP) piracy is the illegal or unlicensed usage of IPs. The semiconductor industry increasingly relies on a hardware IP based design flow, where reusable, pre-verified hardware modules are integrated to create a complex system of intended functionality. An attacker can steal valuable hardware IPs in the form of register-transfer-level (RTL) representations (‘soft IP”), gate-level designs directly implementable in hardware (“firm IP”), or GDSII design database (“hard IP”), and sell those IPs as genuine ones. Hardware IP reusing in Systems-on-chip (SoCs) design is a prevalent practice in the silicon industry as it reduces design time and cost dramatically. The IP piracy attack can occur at various stages in the IC supply chain [24]. The potential IP piracy attackers could be designers, third-party IP (3PIP) vendors, and SoC integrators at the design, synthesis, and verification stages. In the fabrication stage, an untrusted foundry may overbuild the IP cores and sell them under a different brand name to make a profit. Hardware IPs obtained from untrusted third-party vendors can have various security and integrity issues. An adversary inside an IP design house can deliberately insert a malicious circuit or design modification to compromise system security. Various design and algorithmic level robust hardware-based security primitives are proposed in [26] to protect the modern semiconductor supply chain.

Reverse Engineering

The process of identifying an IC’s structure, design, and functionality is known as reverse engineering. Different types of reverse engineering include product teardowns, system-level analysis, process analysis, and circuit extraction. One can use reverse engineering to (1) determine the device technology, (2) extract the gate-level netlist, and (3) infer chip functionality. Several techniques and tools have been developed to facilitate reverse engineering. Traditionally, it has been a legal method for teaching, assessing, and evaluating mask work processes under the US Semiconductor Chip Protection Act. Reverse engineering, on the other hand, is a two-edged sword. Reverse engineering techniques could be used to pirate ICs. Reverse engineering attacks can be carried out at many levels of abstraction in the supply chain, depending on the attacker’s goals [25].

Counterfeiting

A counterfeit semiconductor component is an illegal forgery or imitation of the original component. Counterfeiting is often performed by one of the many entities in the semiconductor supply chain, including new product vendors or secondary (recycled) IC vendors. In recent years, because of technological advances in 3D packaging, fake ICs are hard to distinguish from real ones. Counterfeit ICs are a serious threat to the IC supply chain. Computers, telecommunications, automotive electronics, and military systems are all affected by counterfeiting attacks. As counterfeiters get more sophisticated, counterfeit chips are becoming more difficult to detect.

Hardware Trojans

One of the most insidious methods of attacking a circuit is maliciously modifying its hardware. In simple words, a hardware Trojan (HT) is created by discreetly inserting hidden functionality into a Hardware Design. This insertion can occur at any stage in a production path and could have devastating effects on the final design [25]. Such Trojans can have a variety of functionality, ranging from denial-of-service that gives designs a controllable kill switch to hidden data leaks that can leak sensitive information. HTs are a direct threat to already vulnerable IoT. Unlike software Trojans, HTs cannot be removed simply by a firmware update, so they are very harmful and challenging to remove. Consequently, HT detection is a vital step to guarantee the chips used in IoT are authentic-meaning they only do what they intend to do, nothing less, nothing more. The simple structure of HT is shown in Fig. 1.

Fig. 1
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Simple example of hardware Trojan

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Side Channel Attacks

In the hardware security domain, one of the most prominent and influential tools in the hands of adversaries is a physical attack. Physical attacks are the type of attacks where the attacker has access to the targeted device. These attacks can help the adversary to intrude into the IoT. Physical attacks can be classified into two major categories—invasive vs. non-invasive and active vs. passive. Invasive attacks require tampering with the device under attack, while non-invasive don’t. If the adversary actively influences the device’s behavior, then it is an active attack, or they passively observe leaking information. With mobile devices, the scope of side-channel attacks changed dramatically. Early on, attackers needed access to the physical device. However, in the IoT, these attacks can be made remotely.

Side-channel analysis (SCA) attacks [16, 17, 27] aim to retrieve the secret key in cryptosystems by analyzing physical parameters like power, delay, or electromagnetic emission of the IC which runs security-critical applications.

Power Analysis Attacks Kocher et al. introduced power analysis attacks that exploit implementation of cryptographic algorithm [28]. Power-based SCA attacks are extensively studied that exploit the correlation between the power consumption of the cryptosystem and the hypothetical crypto key to retrieve the secret key applied. There are three common power analysis attacks: simple, differential, and correlation power analysis.

Timing Attacks This attack was also invented by Kocher [29] in 1996. It exploits the data-dependent execution time to reveal secret information. Cryptosystems take slightly different execution times to process different inputs because systems use conditional branches in the algorithm and performance optimization.

Electromagnetic Side-channel Attacks Electromagnetic side-channel attack [30] is also an important information source and is available when any system operates. This attack is non-invasive and does not need device tampering to measure the side-channel leakage. Electromagnetic SCA is becoming popular in the IoT paradigm because of the easy availability of EM probes to conduct the attack. This attack is more prominent in IoT as adversaries do not need physical access to devices compared to power SCA.

Fault Attacks A fault attack is an attack on a physical, electronic device (e.g., smartcard, HSM, USB token) which consists of stressing the device by an external mean (e.g., voltage, light) to generate errors in such a way that these errors lead to a security failure of the system. Fault attacks can be performed by an adversary to either force the device to bypass security mechanisms or to extract secret information using faulty outputs. The work [31] shows that a fault attack can break the advanced encryption standard (AES) implementation with only a pair of fault-free and faulty ciphertexts. One of the most common ways of performing the fault attack is by manipulating the external clock or power inputs or using electromagnetic disturbances. This type of attack is easy to perform as it needs a motivated attacker with mid-level expertise and low-cost equipment. Thus, these fault injection techniques should be considered as a severe threat to IoT systems.

Thermal Side-channel Attacks This type of side-channel attack is typically non-invasive. The temperature traces are collected from the device under attack to extract the secret information. Thermal attacks are not the most common because of the noise associated with the measurement. However, in the context of IoT devices, its distributive and remote nature provides easy access to capture thermal leakage on any node. Aljuffri et al. propose a thermal attack by maneuvering correlation power analysis and deep learning side-channel attack to perform a thermal attack [32]. This work proved that thermal side-channel attacks are possible, and IoT devices need to be safeguarded against them.

3D Integrated Circuits

For the last fifty years, Moore’s Law lies at the heart of high rates of technological change observed in the computer, communication, and software industries. It has accurately predicted the doubling of device density within Integrated Circuits (ICs). However, as conventional channel length scaling continues beyond the 10nm technology node, power and performance gains of scaling are becoming incommensurate. The semiconductor industry is exploring More-than-Moore technologies to overcome the disparity [19].

One such more-than-Moore technology is three-dimensional (3D) integration. 3D integration and similar forms of die-level integration provide novel design methodologies to increase transistor density, reduce interconnect distances, and integrate additional system components. In 3D ICs, active devices are placed in multiple planes (or tiers) of semiconductor dies and are interconnected vertically. 3D integration also facilitates combining multiple different process technologies within a single heterogeneous IC (Fig. 2).

Fig. 2
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3D integration approaches

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3D SiP Using Wire Bonding

In system-in-package (SiP) technology, multiple pre-fabricated dies are encapsulated within the same package. Multiple stacked tiers in a package are connected using wire bonding [20]. Wire bonds are placed around the perimeter of each die to achieve die-to-die connections and die-to-package connections. This technology is used in the IoT domain for sensing applications, where multiple heterogeneous silicon tiers are stacked, and integrated [21].

Through Silicon Vias

3D integration through silicon via (TSV) technology has become a promising solution for realizing high-density packages and high-speed integrated circuits [22]. In TSV-based 3D ICs, the communication between multiple tiers (planes) is achieved by high-density TSVs. TSV technology is the heart and most important key enabling technology of 3D integration. TSVs can be fabricated in several ways, including via-first (before Front End Of Line (FEOL) processing), via-middle (after FEOL processing, but before BEOL processing), or via-last (after BEOL processing).

Monolithic 3D ICs

Monolithic 3D ICs are fabricated using sequential fabrication that begin with a base wafer and then additional layers of crystallized silicon, metalized layers and active as well as passive circuitry are added. The layers are interconnected using fine-pitched Monolithic Inter-tier Vias (MIVs) [23]. It enables ultra fine-grained vertical integration since the MIVs are fabricated using a similar process as the regular local metal vias. There are primarily three design styles for M3D ICs: block-level, gate-level, and transistor-level

Generic Countermeasures Against Side-Channel Attacks

For power-based side-channel attacks, the main objective of countermeasure is to make the power consumption of a device as independent as possible to the intermediate values of a cryptographic algorithm. The general countermeasures for AES include either hiding or masking the data. The goal of hiding [33, 34] is to cover up a correlation between the power traces and the intermediate values. Hiding deceit power traces by randomizing power consumption in a device or flattening the power consumption to make all operations look similar. For the masking technique, the goal is to conceal data by adding/multiplying random numbers to the intermediate values in the encryption process to ward off potential attackers [34]. The challenge becomes implementing the countermeasures without reducing the speed, increasing the power consumption, or increasing the area of the cryptographic algorithm beyond reasonable limits.

Some of the countermeasures proposed against electromagnetic SCA include signal strength reduction techniques like shielding or signal information reduction using noise insertion [35]. Recently, Das et al. used white-box modeling [30] to develop a low-overhead generic circuit-level countermeasure against electromagnetic side-channel attacks. Electromagnetic Equalizer is proposed in [36], where on-chip power grid impedance is adjusted to flatten the current waveform.

A common approach to protecting the cryptographic core from timing attacks is to ensure that its behavior is never data-dependent. The sequence of cache accesses or branches does not depend on either the key or the plaintext. Paper [37] proposed to perform rescheduling of instructions so that each encryption round will consume constant time independent of the cache hits and misses. Another way is to induce noise in all events to prevent exploitation of timing information [38]. One beneficial way to make time attacks challenging is to desynchronize the execution of sensitive parts using random waits, dummy instructions, jitter on clocks, etc., as much as possible. The most cost-effective approach against FA attacks is modifying the cryptographic device’s design to detect injected faults. Traditional fault detection methods for cryptosystems exploit information redundancy, spatial redundancy, or time redundancy to detect faults [39]. Survey paper [40] presented countermeasures against fault injection attacks, including algorithmic changes, sensors and shields, and fault detection or correction techniques.

Resilience Against Physical Attacks in IoT

Side-channel information may arise from timing information, sensor data, or data traffic prevalent in everyday lives. Current IoT studies show that adversaries can easily acquire side-channel information, which is hard to detect because leakages are inevitable hence tackling these attacks is of utmost importance [16,17,18]. The IoT devices are intended to be small and convenient, and traditional, sophisticated security protocol implementations are unacceptable as used in the existing literature. The traditional countermeasures against power attacks reduce the signal to noise ratio, which may be expensive to implement for IoT lightweight applications. The attenuated signature AES is proposed in [17] to resist power-analysis attacks with reduced overhead. This approach implements AES in a signature attenuating hardware, making the variations in AES current highly suppressed. A false key-based AES engine that utilized wave dynamic differential logic (WDDL) is presented in [41] as a countermeasure against CPA attacks. The false round keys generated by the constant intermediate value added to the original round keys are added to the original round keys to disguise the correlation between the dynamic power consumption profile and the actual key. As the area and power overhead of the proposed technique is negligible compared to the unprotected AES, this method fits IoT devices. Kai Yang et al. presented a flexible FPGA virtualization approach [42] to prevent the FPGA-based system from timing attacks. This method’s masking and architectural diversity make it challenging to obtain the required information to carry the successful timing attacks.

Table 1 Categories of countermeasures against physical attacks in IoT with details of algorithm, security metric, hardware used and method description
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In recent years, the adiabatic logic circuit [43] has evolved as a promising solution to design cryptographic circuits for IoT applications because of their energy efficiency and resilience to power-based side-channel attacks. In work [43, 44], authors proposed to use novel single-rail Clocked CMOS Adiabatic Logic (CCAL) to design PRESENT-80 S-box. The study further explored the resistance of the CCAL logic against CPA. Power-based side-channel instruction-level monitoring [45]—side-channel disassembler that tracks the target device’s control flow and enforces decoupled monitoring. Chakraborty et al. developed a hardware-software framework called hardware-aware software timing-attack evaluation to detect the timing side-channel vulnerabilities and malware [45, 46] in runtime. Bai et al. introduced a low-cost external monitoring circuit board to detect anomalous behavior in IoT systems to monitor power, and electromagnetic traces [47]. A comprehensive defense and attack analysis of electromagnetic side-channel attack is presented in [48]. Paper [49] presents a very extensive overview of the approach to developing SoC level security measurement and estimation in IoT applications regarding Power Side-Channel Analysis. In the paper [50], the authors demonstrate the AM signal obtained from the capacitance value in real-time can leak to the outside world in the form of EM radiations. They proposed the technique to alter the accessible capacitance in a single-phase SC dc-dc converter to hinder the side channel. Dynamic IR drop solver ANSYS RedHawk is used in [51] to detect the root cause of EM leakage before manufacturing to minimize the leakage after chip fabrication. Power side-channel leakage assessment framework is presented in [52] that performs a fast, automated, and technology-independent pre-silicon evaluation at the RTL level.

The literature presented above is summarized in Table 1 and is representative of the defense approaches for three primary physical attacks-power, timing, and electromagnetic analysis discussed above. It covers a variety of methods, from standalone devices to comprehensive frameworks for SoC-level system security, and details about the simulation, hardware platform, and security metrics. However, the open questions that the research community is still struggling with are - how does one define the security of the chip and system as a whole? Are there any unified metrics that the community can use? Also, how do we deal with emerging threats inevitable in IoT? Can artificial intelligence be a friend in designing security methods against physical attacks? What is the best way forward?

Unified Countermeasures for IoT

As mentioned earlier, IoT devices are a constrained power budget, so it is imperative to design unified countermeasures that can address multiple attacks simultaneously.

An embedded trusted platform module is proposed in [53] to address a variety of side-channel attacks, including power, timing, fault, and power-glitching attacks. This work makes use of a quantized controller as shown in Fig. 3, that sits between a security-critical core and the rest of the system. A controller uses integrated decoupling capacitors to create uniform power and timing footprints. The inherent implementation of the controller allows control where the computer processor receives its power. During security-critical processes, it can switch the processor’s power source from the main power rail to the controller’s internal storage capacitors, invisible to attackers. This allows the power traces to become unreadable with the proper implementation. A core design is to leverage on-demand isolation to allow side-channel protection from a software-level decision, making the method effective in real-time changes to accommodate IoT design.

The paper [54] proposes strategies that could be used for the design specific targets, specifically for lightweight IoT applications. The first method is to use a maximum distance separable linear layer to incorporate diffusion and fault space transformation that helps to protect against classical cryptanalysis and differential fault attacks. The second strategy exploits modified transparency order metrics to select from different S-box implementations that guide the adequate refresh rate for the mask to defeat the differential power attacks with the same resistance. Cipher-dependent nibble-wise shuffling was proposed in their third method to enhance the side-channel resistance.

Fig. 3
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Secure processor using quantization controller [53]

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Fig. 4
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Stellar technique for side-channel protection [30]

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Recently, Das et al. used white-box modeling [30] to develop a low-overhead generic circuit-level countermeasure called STELLAR - Signature aTtenuation Embedded CRYPTO with Low-Level metAl Routing against electromagnetic and power side-channel attacks shown in Fig. 4. This approach utilizes the local lower-metal layers to route the crypto core with a signature suppression circuit, reducing the leakage reaching the top metal layer.

In the paper [55], the authors proposed a concurrent software approach to resist the side-channel and fault attacks. This countermeasure is generic and applicable to any byte-size cipher. It utilizes larger data path of 32-bit or 64-bit Microcontroller units to carry out parallel byte-sliced encryption. As depicted in Fig. 5, the same data byte D1 is cloned four times and encrypted using a fake key (K\(_F\)) twice and a true key (K\(_T\)) twice. This arrangement will generate the correlated algorithmic noise to protect against SCA as both computations operate parallel on the same data but using two different keys. The same approach helps detect the fault injection attack because of duplicated results from both the fake and correct key computation to detect any anomalies.

Fig. 5
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Combined SCA and FA countermeasure [55]

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In study [56, 57], authors proposed to integrate a dynamic masking technique with an error control code-based error deflection mechanism to thwart power analysis and fault attacks simultaneously. This method generates the masking vector from the intermediate state register in runtime, which changes over time. This arrangement fails the power model modification according to a guessed masking vector.

An on-chip waveform measurement (OCM) technique is exploited in [58] that protects against physical side-channel attacks. The on-chip latch comparator resonator senses the proximate antennas using magnetic coupling. The OCM captures the voltage substrate waveforms when a laser hits the substrate detecting the fault attacks. When OCM detects the antenna or laser presence, the cryptographic chip forces are immediately halted or transitioned to a dummy state. A framework–hardware aware software timing-attack evaluation is presented in [46] to detect the timing side-channel vulnerabilities and malware in runtime. We summarized these papers in Table 2.

Unified countermeasures benefit the IoT systems’ security considering the constraints. However, while designing the combined security approaches, one should analyze their impact on other attacks as they are not always orthogonal.

Table 2 Unified countermeasures against physical attacks in IoT
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3D Integration as an Key Enabling Technology for IoT Devices

3D integration is an emerging technology to ensure the growth in transistor density and performance expected for future ICs. 3D integration has attracted significant attention to developing diverse computing platforms such as high-performance processors, low power systems-on-chip (SoCs), and portable devices during the past two decades. However, 3D integration is not used in IoT devices yet much.

3D Heterogeneous Integration—More than Moore Technology

3D ICs include several tiers that are stacked together in the chip layout and provide a promising paradigm for IoT devices. 3D heterogeneous integration has great potential to design more complex systems such as IoT. 3D technology provides various advantages such as heterogeneous integration [59], split manufacturing [60, 61], disparate technologies for IoT like MEMS sensors [62], etc.

3D Integration for Reliability

Electrostatic discharge (ESD) failure in the nanometer regime is considered the most devastating reliability concern. In research work [63], Wang et al. designed a non-traditional above IC nano crossbar array for ESD protection using 3D heterogeneous integration. The nano crossbar ESD device is built into the back-end of CMOS, i.e., above-IC. Hence, this approach does not utilize any silicon area indeed reduces Si die area traditionally consumed by Si solutions for ESD protection. The same research also designed a novel vertical magnetic-cored inductor with an integrated stacked-via magnetic core made of nano particle powder for RF ICs.

Split Manufacturing

Split manufacturing protects IC design companies against piracy of their intellectual property (IP) by third-party manufacturing facilities [64]. Leading fabless semiconductor companies such as AMD and research agencies such as Intelligence Advanced Research Projects Agency have proposed split manufacturing. In split manufacturing, a design house (with a low-end, in-house, trusted foundry) fabricates the Front End Of Line (FEOL) layers (transistors and lower metal layers) in advanced technology nodes at an untrusted high-end foundry [65]. 3D integration has been successful in splitting 2D IP modules within 3D ICs [66] without thinking security aspect.

Energy Harvesting Using Solar Cell

Many IoT devices will be battery operated or self-powered. Energy harvesting is one technique that shows the potential to improve energy efficiency in IoT devices. Solar cells are the common option for providing a source of power to these devices. 3D integration provides an opportunity to use alternate forms of energy like solar, electromagnetic, thermal, etc., because of its heterogeneous nature.

Wireless 3D ICs

The idea of 3D integration to construct highly-integrated heterogeneous IoT chips has not yet been realized. The primary reason is the cost of manufacturing and limited EDA support for designing 3D chips. Fletcher explored a low-cost alternative to replace the bulky TSVs using wireless vertical links [67]. With the proposed approach, existing 2D fabrication processes can be used as it is and for all technologies. In wireless 3D ICs, the data is communicated to different tiers via an electromagnetic coupling instead of physical channels as in TSV-based 3D ICs. The authors utilized a low-energy Inductive coupling link (ICL) transceiver for data and power transmission using spike-latency encoding to reduce the energy consumption of existing ICL ideal for IoT devices (Fig. 6).

Fig. 6
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3D structure for IoT devices

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Security Perspective

The fact that security is not the main functionality of an IoT device means that even a lesser portion of its computing power is available for the security. Security measures implemented in traditional computers, such as cryptography, present a challenge in this context when applied to IoT devices. Further, due to the heterogeneity of devices, the power budget may not be enough to implement sophisticated security features. Many studies showed that side-channels in IoT devices are easy to obtain and hard to defend against; hence, addressing the side-channel leakage is crucial. Although various threats challenge IoT security, the root of trust starts from the hardware [68]. Without trusted and authenticated IoT devices, high-level approaches cannot stop these attacks. As many IoT devices are small in size, low in computation capabilities, and powered by low capacity batteries, we need to rethink the trusted environment for IoT.

3D integration provides the following benefits for their application in the IoT paradigm. The overview of the 3D structure for IoT devices is shown in 6.

Fig. 7
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Countermeasure against CPA attacks in 3D ICs

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Separate Security Plane Using 3D Stack

Sherwood et al. [69] introduce a novel architecture using a separate control plane, stacked using 3D integration, that provides security mechanisms to protect the design from explicit and implicit channels of information leakage. 3D will provide much higher integration, bringing multiple CPUs, memory blocks and cryptographic engines together. Hence the side channel information will become noisy, making the attacks very challenging. If the control (security) plane is placed in the middle stack of 3D IC for fault prevention, it will be unlikely to inject reliable faults to carry out successful fault attacks.

Shielding Side-Channels with 3D Stacking

In this approach, the authors utilize intrinsic characteristics of the 3D chip and dynamic shielding to hide the security-related activities on the chip [70]. They propose to use a micro-controller unit to produce complementary activity patterns dynamically thwarting side-channel information leakage. This method work with on-chip power budget and thermal management to minimize the power overhead by controlling activities in each layer. When the functional unit is active and utilizes more power, the noise generator will also increase the power counteracting the impact.

Intrinsic Power Distribution Network (PDN) Noise to Defeat SCA in 3D ICs

In this work, the authors demonstrate that 3D PDN introduces noise to the power profile of the crypto unit that depends on the load switching activities, PDN topology, and crypto module deployment in the 3D chip. Using real 3D PDNs and through-silicon-vias (TSVs) models, they performed quantitative experimentation to exploit intrinsic noise to defeat the side-channel attacks [72, 73]. The overview of the method is shown in Fig. 7. The crypto unit is divided into multiple sub-units (e.g., four). Each sub-unit is driven by a local supply voltage V DDi (i = 1, 2, 3, 4). We utilize a crossbar to connect the local VDD pins with the PDN nodes close to four power TSVs. Due to the non-uniform switching activities in every 3D plane, each TSV passes a unique voltage from other 3D planes to the plane carrying the crypto unit. The effect of parasitic resistance and capacitance (RC) of the metal wire between the power grid and the local VDD pin further increases the variance of the four VDDs for the crypto unit.

Camouflaging in Monolithic 3D ICs

Yan et al. [71] proposed a logic camouflaging for 3D ICs, more specifically for monolithic 3D ICs, to enable ultra-high density device integration. In work, standard cell libraries are created and characterized to analyze the performance of monolithic 3D ICs. Further, the authors used these libraries to design a camouflaged lightweight block cipher–SIMON and several academic benchmarks. This method is notable because it helps thwart reverse-engineering attacks with low overhead compared to classical 2D-centric camouflaging. For example, in the camouflaged 2D SIMON implementation, area, wirelength increased by 21.1%, 11.3%, and 7.4%, respectively, compared to the conventional 2D implementation. In contrast, in camouflaged monolithic 3D, the area, wirelength, and power are reduced by 37.7%, 15.7%, and 22% compared to 2D design.

Integration of Split Manufacturing and Camouflaging into 3D CAD Flow

The idea of combining the split manufacturing with camouflaging for security-driven 3D CAD flow is described in article [74]. Their scheme for 3D integration is focused on face-to-face 3D ICs and utilizes TSVs for external connections and additional metal redistribution layers (RDLs) for internal connections. These additional obfuscated layers (camouflaged RDLs) as shown in Fig. 8 protect against reverse engineering attacks thwarting IP piracy at untrusted foundries.

Fig. 8
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3D split manufacturing with Camouflaging [74]

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Conclusion

The emerging technological space is growing with the Internet of Things (IoT). IoT is revolutionizing our lives  by bringing the physical and digital worlds together. While creating exceptional benefits like convenience, accessibility, and efficiency, IoT is also causing significant concerns in the security realm. Security vulnerabilities in the IoT domain are threatening critical infrastructures and national security.

Many IoT designs prioritize keeping their devices small in size, battery, and computation power, making traditional security methods unsuitable. We must rethink the trusted environment for IoT devices that provides lightweight solutions and enhanced security. This paper highlights the countermeasures for single and then explores unified defense methods for physical attacks in IoT applications. Further, we explore the potential of 3D integration as a key enabling technology for IoT devices. It provides various advantages, such as heterogeneous integration, split manufacturing, and disparate technologies for IoT like MEMS sensors, making 3D integration the best choice for IoT platforms.