1 Introduction

A magnetic skyrmion is a stable topologically non-trivial configuration that possesses particle-like properties [1,2,3]. There are many advantages that make skyrmion a promising technology for beyond-CMOS computing devices and future data storage devices, including its small size, stable properties, and its ability to be driven by electric current [4,5,6]. In 2009, the existence of magnetic skyrmion has been demonstrated experimentally in bulk MnSi exhibiting the Dzyaloshinskii–Moriya interaction (DMI) [7,8,9]. Inspired by the experimental realizations of skyrmion, many skyrmion-based logic gates and computational devices have been proposed [10,11,12,13,14,15,16,17,18,19,20,21]. However, skyrmion-based arithmetic devices are relatively less discussed.

Conventional arithmetic devices are usually constructed using single-bit full adder [22, 23]. With appropriate matching of single-bit full adders and logic gates, basic arithmetic operations such as addition, subtraction, and multiplication can be realized in electronic circuit. Therefore, the speed and energy consumption of arithmetic devices strongly depend on the efficiency of the single-bit full adder [22, 23]. In CMOS circuit, the single-bit adder is usually constructed by the matching of multiple logic gates. With similar approach, Chauwin et al. [10] propose the design of an efficient single-bit full adder by matching skyrmion-based logic gates. Alternatively, Song et al. [13] demonstrate that the performance of single-bit full adder can be further improved by performing logical operations concurrently by taking advantages of the skyrmion annihilation properties. However, both designs of single-bit full adder rely heavily on precise control of skyrmion Hall effect, which can be challenging in operation. As demonstrated in recent studies, the skyrmion Hall angle is sensitive to the fluctuation of applied current density [24,25,26] and temperature [27, 28], causing changes in the skyrmion trajectory and unintentionally annihilation. On the other hand, studies also describe the issues of stabilizing skyrmions below 10 nm in ferromagnetic multilayers and ferromagnetic thin films [29, 30].

To resolve these problems, synthetic antiferromagnets (SyAF) have been introduced. The SyAF bilayer system is a ferromagnet/heavy-metal spacer/ferromagnet trilayer structures, where the two ferromagnetic (FM) layers are strictly exchange-coupled in an antiferromagnetic (AFM) configuration [31]. By using the SyAF structure, the skyrmion Hall effect is greatly suppressed [32], and skyrmions with the size below 10 nm are stabilized without applying magnetic field [33, 34]. These properties are important to stabilize skyrmion in high speed skyrmion-based devices, avoiding accidental skyrmion annihilation and allowing more compact devices to be fabricated. Therefore, it is important to perform study on designing a single-bit full adder based on the SyAF structure. Indeed, other racetrack fabrication methods based on local modification of magnetic properties [35, 36] are also important for building skyrmion-based devices.

In this paper, we propose designs of skyrmion-based single-bit half adder, single-bit full adder and XOR logic gate on SyAF bilayer structure. These designs execute computation by controlling skyrmion trajectory and annihilation with simple geometry. Since the skyrmion Hall effect is greatly suppressed on SyAF, our proposed devices are less sensitive to electric current and thermal fluctuation. We also demonstrate that the delay time and energy-delay product (EDP) of the single-bit full adder can be reduce to 1.95 ns and 2.50 × 10–22 Js per each operation, which are only 12% and 79% those of the previously proposed skyrmion adder, respectively. Our results provide guidelines for the design of quick response skyrmion-based logic gate and single-bit full adder device.

2 Model and methods

Figure 1a shows the schematic diagram of the proposed device. Two heavy metal (HM) layers sandwich the patterned trilayer SyAF structure. The patterned trilayer SyAF are shown in Fig. 1b–d and are used as the skyrmion conduit. Magnetic tunnel junctions (MTJ) are installed on top of the SyAF/HM layer for skyrmion nucleation and detection. This MTJ-based skyrmion nucleation and detection circuit is adopted from previous skyrmion devices and is spice-compatible [17, 37]. The skyrmion in the patterned SyAF layers is driven by spin–orbit torque (SOT), which is induced by applying electric current to the HM layers to produce vertical spin currents to the SyAF structure [19]. Thus, skyrmion moves in the electric current direction.

Fig. 1
figure 1

Schematic diagrams of proposed SyAF bilayer single-bit half adder, single-bit full adder and logical XOR gate: a XZ cut of SyAF bilayer used; b FM layer design of single-bit half adder; c FM layer design of single-bit full adder; d FM layer design of XOR logic gate

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The operation of the proposed devices is designed based on the analysis of SOT driven skyrmion motion properties described by Thiele equation [13, 32]:

$$ {\mathbf{G}} \times {\mathbf{v}} - D\alpha {\mathbf{v}} + {\mathbf{F}}_{{{\text{st}}}} + {\mathbf{F}}_{{{\text{ext}}}} = 0 $$
(1)

where \(\mathbf{G}=\widehat{z}G=\widehat{z}\left(4\uppi Q\right){M}_{\mathrm{s}}d/\gamma \) is the gyromagnetic vector, \(G\) is the magnitude of the gyromagnetic vector in the z direction, d is the thickness of the plate, Q is the topological charge, \(\gamma \) is the gyromagnetic ratio and constant \(D=-\frac{16}{3}\uppi {M}_{\mathrm{s}}d/\gamma \) is dissipation. The first term \(\mathbf{G}\times \mathbf{v}\) is the gyroscopic force related to the skyrmion Hall effect and the second term \(D\alpha \mathbf{v}\) is the dissipative forces that oppose the skyrmion movement in the direction of the velocity \((\mathbf{v})\). The third term \({\mathbf{F}}_{\mathrm{st}}=\sigma \kappa j\widehat{z}\times \widehat{p}\) is spin torque force, with spin Hall angle dependent constant \(\sigma =-\pi \mathrm{\hslash }{\theta }_{\text{SH}}/2e\), characteristic length of skyrmion \(\kappa \) and \(\widehat{p}=-\widehat{y}\) in our simulation. The fourth term \({\mathbf{F}}_{\mathrm{ext}}\) is an external force, including forces induce by the conduit’s boundary, notches or tilted edge.

Skyrmions movements on the FM layer are determined by the balances of these four forces. Considering the skyrmion in the free space moving along the x-axis, i.e., \({\mathbf{F}}_{\mathrm{ext}}=0\):

$$ {\mathbf{v}}_{x} = \frac{\alpha D}{{G^{2} + \alpha^{2} D^{2} }}{\mathbf{F}}_{{{\text{st}}}}, \quad {\mathbf{v}}_{y} = \frac{{\mathbf{G}}}{{G^{2} + \alpha^{2} D^{2} }}{\mathbf{F}}_{{{\text{st}}}} $$
(2)

Thus, the skyrmion transverse movement \({\mathbf{v}}_{y}\) is related to G and its direction depends on the topological charge of the skyrmion Q. In SyAF, the skyrmions on top FM layer and bottom FM layer are strictly exchange-coupled in an antiferromagnetic (AFM) configuration. Hence, the skyrmions have opposite sign of Q and the transverse movement will cancel out each other. As a result, with balance of the three forces: gyroscopic force (\(\mathbf{G}\times \mathbf{v}\)), dissipative force (\(D\alpha \mathbf{v}\)), and spin torque force (\({\mathbf{F}}_{\mathrm{st}}\)), skyrmion moves in a straight line in free space.

When the skyrmion is close to the boundary of the conduits, changes of magnetization at the boundary induced repulsive force (\({\mathbf{F}}_{\mathrm{ext}}\) = \({\mathbf{F}}_{\mathrm{b}}\)) to the skyrmion. For titled edge, transverse force (\({\mathbf{F}}_{\mathrm{b}}={\mathrm{F}}_{\text{b}}\widehat{y}\)) is extracted from the boundary, causing the skyrmions to move along the boundary. When the forces exceeds the threshold value, a skyrmion annihilates at the boundary [38, 39].

The adders and logic gate operation are demonstrated using micromagnetic simulations performed on the GPU-accelerated open-source micromagnetic simulator software package MuMax3 [40], which have been used in simulating SyAF system as reported in Refs. [41,42,43,44]. In real experimental samples, a spacer layer is added to adjust the interlayer exchanges coupling between two ferromagnetic layers. In the simulation, we focus on the magnetic layers and ignore the physical thickness of the nonmagnetic spacer layer, as the spacer is nonmagnetic and is usually much smaller than 1 nm in experiments [45]. However, we do consider the interlayer exchange coupling based on the RKKY-type exchange interaction. Therefore, in the simulation, we applied interlayer exchange coupling between two ferromagnetic layer and ignore the thickness of nonmagnetic spacer layer. The software simulates the magnetization dynamics by solving the Landau–Lifshitz–Gilbert (LLG) equation augmented with SOT [46, 47]:

$$ \frac{{{\text{d}}{\mathbf{m}}}}{{{\text{d}}t}} = - \gamma_{0} {\mathbf{m}} \times {\mathbf{H}}_{{{\text{eff}}}} + \alpha \left( {{\mathbf{m}} \times \frac{{{\text{d}}{\mathbf{m}}}}{{{\text{d}}t}}} \right) - \frac{{\hbar \theta_{{{\text{SH}}}} J}}{{2meM_{\text{s}} t_{{{\text{FM}}}} }}{\mathbf{m}} \times \left( {{\mathbf{m}} \times {{\varvec{\upsigma}}}} \right) $$
(3)

where \(\mathbf{m}\) is normalized magnetization, \({\gamma }_{0}\) is the gyromagnetic ratio, \({\mathbf{H}}_{\mathrm{eff}}\) is effective field vector, \(\alpha \) is damping constant, \({\theta }_{\mathrm{SH}}\) is spin Hall angle, \(J\) is current density, \({M}_{\mathrm{s}}\) is saturation magnetization, \({t}_{\mathrm{FM}}\) is thickness of the FM layer, and \({\varvec{\upsigma}}=-\overrightarrow{{u}_{y}}\) in our model. The intrinsic magnetic material parameters used in our simulation are adopted from experimental data of Co/Pt materials reported in Ref. [47] and are used in simulations reports [48,49,50,51,52]: exchange stiffness of \({A}_{\mathrm{intra}}\)= 15 pJ·m−1, Gilbert damping coefficient of \(\alpha =0.3\), saturation magnetization of \({M}_{\mathrm{s}}=\) 580 kA·m−1, perpendicular magnetic anisotropy (PMA) constant of K \(=0.8\) MJ·m−3, DMI strength of \(D\)= 3.5 MJ·m−2 and spin Hall angle of \({\theta }_{\mathrm{SH}}=0.2\). To balance the accuracy and efficiency, all models are discretized into tetragonal elements with the size of 2 nm × 2 nm × 2 nm.

3 Results and discussion

3.1 Skyrmion-based single-bit half adder device

A half adder is operated by compiling XOR and AND logical operation simultaneously to generate SUM and CARRY outputs, respectively. Realization of half adder in conventional CMOS circuit requires 18 transistors with complex circuit connections [13]. Here, we propose a different approach to realize single-bit half adder device using simple geometry and magnetic skyrmions. The design of the half adder device includes two inputs and outputs with a crossover region (Fig. 1b). Figure 2 shows the operation of the proposed single-bit half adder. Skyrmions present at the left input terminals travel to the right terminals for detection. For input (1,0) (Fig. 2a and Supplementary Video S1), the skyrmion nucleated at the upper input terminal is diverged to the crossover region by a 45° tilted edge. Owing to the skyrmion-edge repulsion, the skyrmion moves in the center of the crossover region and passes the triangular notch. Then, the skyrmion is diverged by the second 45° tilted edge and is detected at the output terminals, resulting in an output (1,0). Similarly, for input (0,1) (Fig. 2b and Supplementary Video S2), the skyrmion nucleated at the lower input terminal is diverged to the crossover region by a 45° tilted edge. Owing to the skyrmion-edge repulsion, the skyrmion moves in the center of the crossover regions and passes the triangular notch. Then, the skyrmion is diverged by the second 45° tilted edge and is detected at the output terminals, resulting in an output (1,0). Finally, for input (1,1) (Fig. 2c and Supplementary Video S3), two skyrmions encounter at the crossover region and repel each other, due to skyrmion–skyrmion repulsion. Subsequently, the upper skyrmion is annihilated at the triangular notch, and the lower skyrmion is diverged to the lower output terminal by the second 45° tilted edge. Therefore, the input (1,1) results in an output (0,1). Input (0,0) obviously generates an output (0,0). The upper and lower output terminals are corresponded to SUM and CARRY, respectively. As a result, the simple geometry shown in Fig. 1b can perform the XOR and AND operation concurrently and can operate as a single-bit half adder with delay time 1.1 ns.

Fig. 2
figure 2

Skyrmion-based single-bit full adder device operation for each input case: a 1 + 0, b 0 + 1, and c 1 + 1, where device size is 150 nm × 300 nm, applied current density is j = 140 MA·cm−2, operation time of half adder is 1.1 ns, Cout and Cin are output carry and input carry of half adder, respectively

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3.2 Skyrmion-based single-bit full adder device

A single-bit full adder is operated by compiling two binary inputs and a carry-in digit to generate SUM and CARRY-OUT outputs. Hence, it comprises three inputs and two outputs. The previous skyrmion-based full adders are constructed by connecting two half adders and one OR gate properly [10, 13]. Here, we implement single-bit half adder device using simple geometry with design similar to the half adder, as shown in Fig. 1c. Figure 3 and Supplementary Videos S4–S10 show the operating process of the full adder. The skyrmions presented at the left input terminals travel to the right for detection at the output terminals. The final outputs represent SUM (upper branch) and CARRY-OUT (lower branch).

Fig. 3
figure 3

Skyrmion-based single-bit full adder device operation for each input case: a 1 + 0 and Carry 0, b 0 + 0 and Carry 1, c 0 + 1 and Carry 0, d 1 + 0 and Carry 1, e 1 + 1 and Carry 0, f 0 + 1 and Carry 1, and g 1 + 1 and Carry 1, where device size is 190 nm × 300 nm, applied current density j = 140 MA·cm−2, and operation time of full adder is 1.95 ns, Cout and Cin are output carry and input carry of full adder, respectively

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We first demonstrate the operation of full adder with input (0,1,0), (1,0,0) and (0,0,1). For input (0,1,0), the skyrmion nucleates on the left terminal will pass through the triangular notch and is diverged to the SUM region by the second 45° tilted edge, as show in Fig. 3a (Supplementary Videos S4). For input (1,0,0) and (0,0,1), the skyrmion nucleates on the left terminal will be diverged to the crossover region by the 45° tilted edge. Owing to the skyrmion-edge repulsion, the skyrmions will align to the center of the crossover region and pass through the triangular notch. The skyrmion will be diverged to the upper output terminal for detection by the second 45° tilted edge, as shown in Fig. 3b, c (Supplementary Videos S5,S6). Therefore, the input (0,1,0), (1,0,0) and (0,0,1) results in an output (1,0).

The operation of full adder with input (1,0,1), (0,1,1) and (1,1,0) is demonstrated in Fig. 3d–f (Supplementary Videos S7–S9). Similar to the operation with input (0,1,0), (1,0,0) and (0,0,1), skyrmions nucleated in the input terminals enter the crossover region. Within the crossover region, two skyrmions encounter and repel each other, due to skyrmion–skyrmion repulsion. Subsequently, the upper skyrmion is annihilated at the triangular notch. The lower skyrmion is diverged by the 45° tilted edge to the lower output terminal. Therefore, the input (1,1,0), (0,1,1) and (1,1,0) results in an output (0,1).

The operation of full adder with input (1,1,1) is demonstrated in Fig. 3g (Supplementary Video S10). Similar to the operation with input (1,1,0), (0,1,1) and (1,0,1), skyrmions nucleated in the inputs enter the crossover region. Within the crossover region, three skyrmions encounter and repel each other. Two skyrmions travel simultaneously with one skyrmions is repel backwards. Thus, the upper skyrmion is annihilated at the triangular notch. The lower skyrmion and the skyrmions at the back are diverged by the 45° tilted edge to the lower and upper output terminal, respectively. Therefore, the input (1,1,1) results in an output (1,1). In addition, input (0,0) obviously generates an output (0,0). We have investigated the reliability of the full adder and found the proper range of the operation current density to be from 120 to 145 \(\mathrm{MA}\!\cdot\!{\mathrm{cm}}^{-2}\).

It is interesting to note that the skyrmion arrives the upper and lower output terminal in 1.95 and 1.7 ns, respectively. Therefore, the CARRY-OUT result can be read and pass to the subsequent adder 0.25 ns before the OUTPUT is computed, which can further reduce the delay time in constructing multi-bits adder. On the other hand, when we compare it with the full adders that are constructed by combination of half adders, our design does not have the synchronizing issue of arrival time between two half adders and one OR gate. Therefore, the full adder is more robust and scalable. Additionally, Ref. [13] suggests that cascading single-bit skyrmion adders can realize energy efficient multi-bits adder without wire connection. Similar cascading approach is also feasible to build energy efficient multi-bits adder with our proposed adder, information can be found in Figure S1.

In addition, we have performed simulations on our design when the notch is displaced by ± 5 nm in the x direction (Figs. S2, S3). The execution of addition operation is not affected by the displace notch, showing there is tolerance for defects to some degree in our design.

3.3 Skyrmion-based single-bit half adder device

A half adder is a combination of XOR and AND logic gate, as demonstrated in Sect. 3.1. However, for high-speed computation, we designed an alternative version of XOR logic gate that operate faster than the half adder. The proposed skyrmion-based XOR logic gate is shown in Fig. 4. Input A and Input B are located on the left and the output are located on the right. Different from the half adder, the output region is at the center of the channel. We first demonstrate the XOR logic gate operation in Fig. 4 (Supplementary Videos S11–S13). The logical XOR gate is operated such that 0 + 0 = 0, 1 + 0 = 1, 0 + 1 = 1 and 1 + 1 = 0. The process of 0 + 0 = 0 in XOR gate is trivial, where no skyrmions are presents in input and output. We interpret the process 1 + 0 = 1 and 0 + 1 = 1 as follow: when a skyrmion is placed on either Input A or Input B, the skyrmion is diverged to the crossover region. Owing to skyrmion edge repulsion, the skyrmion travels at the center and reaches the output terminal for detection. On the other hand, the important process 1 + 1 = 0 is represented as follow: skyrmions are placed on both Input A and Input B, both skyrmions enter the crossover region and repel each other. Then, two skyrmions travel simultaneously and are annihilated by the edges of the output terminal. Thus, no skyrmions reach the output region, representing logical 0 as the output of XOR gate. The operation time for the XOR logic gate is 0.7 ns, which is much lower than 1.1 ns in half adder.

Fig. 4
figure 4

Skyrmion-based XOR logic gate operation for each input case: a 1 + 0, b 0 + 1, and c 1 + 1, where device size is 130 nm × 200 nm, applied current density j = 140 MA·cm−2, and operation time of XOR logic gate is 0.7 ns

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XOR logic gate is important in constructing adder–subtractor. A multi-bit ripple-carry adder–subtractor is demonstrated in Fig. 5a, where the circuit is composed of multiple full adders and XOR logic gate, in which the carry-out of each full adder is the carry-in of the subsequent full adder. XOR logic gate provide Control Input to the adder–subtractor logic circuit. When the Control Input is logical 0, the XOR logic gate is a connection line. Thus, the logical state in Input B is passed to the full adder without alternation and addition operation is executed. On the other hand, when Control Input is logical 1, XOR logic gate is turn into a NOT gate. Thus, the logical state in Input B will be flipped and passes to the full adder. In such condition, the logical computation \(A-B=A+\overline{B }+1\) is realized in circuit and subtraction operation is executed. Hence, by cascading or wire-connected the full adder and XOR logic gate proposed in this study, a quick response skyrmion-based multi-bit ripple-carry adder–subtractor can be realized.

Fig. 5
figure 5

a Diagram of wire-connected n-bit ripple-carry adder–subtractor; b diagram of wire-connected n-bit ripple-carry adder; c time delay of various skyrmion-based n-bit ripple-carry adder, where red squares represent estimated time delay for Ref. [13], blue squares correspond to estimated time delay for Ref. [10] and black squares correspond to our proposed full adder design

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3.4 Skyrmion-based single-bit half adder device

The operation of half adder, full adder and XOR logic gate that operate without skyrmion Hall effect have been demonstrated on SyAF structure. We first estimate the total delay time of our full adder and half adder using the following equation:

$$ t_{{{\text{operation}}}} = t_{{{\text{nucleation}}}} + t_{{{\text{propagation}}}} + t_{{{\text{detection}}}} $$
(4)

The \({t}_{\mathrm{nucleation}}\) of one skyrmion nucleation by MTJ is about 20 ps and the \({t}_{\mathrm{detection}}\) by MTJ is about 5 ps [35]. Therefore, the operation time of our full adder and half adder is 1.98 and 1.13 ns, which is, respectively, only about 12% and 19% that of the previous skyrmion-based adder [13]. The difference is contributed by the SyAF structure, which allows skyrmion to be diverged by the conduct’s edge in high current density without annihilation, and can make great impact on computational devices. For example, ripple-carry adder is constructed by series connection of single-bit adder, as shown in Fig. 5b. In such configuration, the delay time of the n-bit ripple-carry adder is the sum of all single-bit full adder delay times. Figure 5c shows the total delay time of the n-bit ripple-carry adder for previous proposed devices [10, 13]. The blue and red symbols correspond to the delay time consumption based on Refs. [10, 13], respectively. The black symbols correspond to the delay time consumption of our design. Obviously, our adder design response quicker than the previous proposal [10] and [13]. For a 64-bit system (n = 64), the time delay in our design is about 126.4 ns, which is about 899 ns lower than previous skyrmion-based adder design [13]. The delay time can be further reduced to 110.65 ns by taking advantages of the 0.25 ns delay time different between the OUTPUT and CARRY-OUT of the single-bit adder. Since our proposed device are built on SyAF structure, it is possible to further increase the operation speed by minimizing the device for sub-10 nm skyrmion [33, 34].

We then evaluate the energy efficiency of our adder devices using the energy-delay product \({\mathrm{EDP}}_{\mathrm{operation}}={E}_{\mathrm{operation}}\times {t}_{\mathrm{operation}}\), where \({E}_{\mathrm{operation}}\) is the energy during nucleation (Input), propagation and detection (Output), which are given by the following equation:

$$ E_{{{\text{operation}}}} = E_{{{\text{nucleation}}}} + E_{{{\text{propagation}}}} + E_{{{\text{detection}}}} $$
(5)

\({E}_{\mathrm{nucleation}}\) of one skyrmion nucleation by MTJ is about 3.1 fJ, while \({E}_{\mathrm{detection}}\) by MTJ is about 0.8 fJ [17]. \({E}_{\mathrm{propagation}}\) is calculated from the energy dissipation caused by the electric resistance of the HM layer:

$$ E_{{{\text{propagation}}}} = I^{2} R_{{{\text{HM}}}} \Delta t = \rho_{{{\text{HM}}}} V_{{{\text{HM}}}} j^{2} t_{{{\text{propagation}}}} $$
(6)

where \({\rho }_{\mathrm{HM}}\) is the resistivity of the HM (resistivity of Pt is \(10.6 \times {10}^{-8}\;\Omega \cdot \mathrm{m}\), j is the current density, \({V}_{\mathrm{HM}}\) is the volume of the HM layer (\(190\,{\text{nm}}\times 300\,{\text{nm}} \times 2.5 \,{\text{nm}}\) for Full adder) and the \({t}_{\mathrm{propagation}}\) of full adder is 1.95 ns. Therefore, the EDP of full adder, including I/O, is estimated to be \(2.5 \times {10}^{-22}\) Js, which are only about 79% that of the previous proposed skyrmion-based adders [13]. The difference in energy efficiency is contributed by the smaller propagation area and shorter propagation time in our design, which allows the same functionality with a smaller number of logic gates than the previous proposal. On the other hand, the size of our full adder is 190 nm × 300 nm, only 48% that of the previous proposed skyrmion-based full adder and 0.06% that of the transistor based full adder [53], which is significant for making compact computer chips.

On the other hand, our design of the skyrmion-based adder is implemented by the skyrmion trajectory that is driven by SOT, which is one of the most commonly used methods applied in skyrmion-based devices to manipulate the magnetization. Recently, other approaches, such as the piezospintronics and topological anomalous Hall effect, have been predicted and experimentally demonstrated to switch magnetization with lower energy and less Joule heating effect [54,55,56]. These approaches on skyrmion-based device are worth studying due to their potential to further improve the energy efficiency of our proposed full-adder.

4 Conclusion

In summary, novel designs of the skyrmion-based arithmetic circuits and logic gates on SyAF structure have been demonstrated. By introducing geometric notches and tilted edges on patterned nanotracks, we have successfully constructed the half adder, the full adder and the XOR logic gate based on skyrmions. Owing to the simple geometries, the proposed logic gates have the advantage of low delay time and high energy efficient when compared with the conventional CMOS-based logic gates or skyrmion-based logic devices that have been proposed. Since the skyrmion Hall effect is suppressed on the SyAF structure, our proposed logic gate is less sensitive to electric current fluctuation. We have also demonstrated the strength of our proposed single-bit full adder by calculating the delay time and energy-delay product of a multi-bit ripple carry adder circuit. Our proposed arithmetic circuit is compossible with semiconductor fabrication technology in the industry. Therefore, the skyrmion-based arithmetic circuit on the SyAF structure is a promising candidate for spintronics devices.