Abstract
This paper presents the technique of using the negative capacitance phenomenon in a charge-plasma junctionless nanotube tunnel field effect transistor (CP-JLTFET). In recent decades, owing to the fundamental physics of the “Boltzmann tyranny,” the rising power dissipation in nano-devices has become an issue in complementary metal oxide semiconductor (CMOS) technology. So, it has become important to introduce new techniques into the operation of FETs to avert such types of bottlenecks. Negative capacitance is an effective technique to reduce threshold voltage and subthreshold slope < 60 mV/decade. This phenomenon reduces the power supply voltage and minimizes the power dissipation. In this work, the performance of the device is analyzed using a ferroelectric capacitor [P(VDF-TrFE)], which generates a negative capacitance effect during the device operation. The device performance is investigated with and without using negative capacitance. The impacts of varying ferroelectric thickness on the device performance, like threshold voltage, polarized charge, transconductance, etc., are also analyzed.
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A. Nourbakhsh, A. Zubair, S. Joglekar, M. Dresselhausa, and T. Palacios, Nanoscale 9, 6122 (2017).
A.M. Ionescu and H. Riel, Nature 479, 329 (2011).
H. Kam, D. T. Lee, R. T. Howe, and T. J. King, IEEE Int. Ele. Dev. Meet., 463 (2005).
K. Gopalakrishnan, P. B. Griffin, and J. D. Plummer, IEEE Int. Elec. Dev. Meet., 289 (282).
N.M. Estakhri, B. Edwards, and N. Engheta, Science 363, 1333–1338 (2019).
L. La Spada and L. Vegni, Opt. Express 25, 23699–23708 (2017).
N.J. Greybush, V. Pacheco-Peña, N. Engheta, C.B. Murray, and C.R. Kagan, ACS Nano 13, 1617–1624 (2019).
L. La Spada, C. Spooner, S. Haq, and Y. Hao, Sci. Rep. 9, 3107 (2019).
I.H. Lee, D. Yoo, P. Avouris, T. Low, and S.H. Oh, Nat. Nanotechnol. 14, 313 (2019).
L. La Spada and L. Vegni, Materials 11, 603 (2018).
A.I. Khan, K. Chatterjee, B. Wang, S. Drapcho, L. You, C. Serrao, S.R. Bakaul, R. Ramesh, and S. Salahuddin, Nat. Mater. 14, 182 (2015).
S. Salahuddin and S. Datta, Nano Lett. 8, 405 (2007).
D.J. Appleby, N.K. Ponon, K.S. Kwa, B. Zou, P.K. Petrov, T. Wang, N.M. Alford, and A.O. Neill, Nano Lett. 14, 3864 (2014).
G. Catalan, D. Jiménez, and A. Gruverman, Nat. Mater. 14, 137 (2015).
S. Salahuddin and S. Datta, Nano Lett. 8, 405 (2008).
A.I. Khan and S. Salahuddin, IEEE Conf. (2015). https://doi.org/10.1109/S3S.2015.7333485.
T. Krishnamohan, D. Kim, S. Raghunathan, and K. Saraswat, IEEE Int. Electron Dev. Meet., 1 (2008).
K. Boucart and A.M. Ionescu, Solid-State Electron. 51, 1500 (2007).
R. Jhaveri, V. Nagavarapu, and J.C.S. Woo, IEEE Trans. Electron Dev. 58, 80 (2011).
J. Knoch and J. Appenzeller, IEEE Electron Dev. Lett. 31, 305 (2010).
M.H. Lee, Y.T. Wei, J.C. Lin, C.W. Chen, W.H. Tu, and M. Tang, AIP Adv. 4, 107 (2014).
S. Shreya, A.H. Khan, N. Kumar, I. Amin, and S. Anand, IEEE Sens. J. 1, 1 (2019). https://doi.org/10.1109/jsen.2019.2944885.
T. Furukawa, Y. Takahashi, and T. Nakajima, Curr. Appl. Phys. 10, 62 (2010).
H. Ku and C. Shin, J. Electron Dev. Soc. 5, 3 (2017).
A. Saeidi, and F. Jazaeri, et al., IEEE Electron Dev. Lett. 38, 10 (2017).
S.M. Sze and K.K. Ng, Physics of Semiconductor Devices (Hoboken, NJ: Wiley, 2007), p. 315.
Silvaco International, ATLAS User Manual 2010 (Santa Clara: Silvaco International, 2010).
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Shreya, S., Kumar, N., Anand, S. et al. Performance Analysis of a Charge Plasma Junctionless Nanotube Tunnel FET Including the Negative Capacitance Effect. J. Electron. Mater. 49, 2349–2357 (2020). https://doi.org/10.1007/s11664-020-07969-3
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DOI: https://doi.org/10.1007/s11664-020-07969-3