Abstract
Design Rule Checking (DRC) in VLSI design involves checking if a given VLSI layout satisfies a given set of rules and reporting the violations if any. We propose data structures for reporting violations of the minimum extension rule in a query window of interest.
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A preliminary version of the paper appears as a four-page extended abstract in the Proceedings, Canadian Conference on Computational Geometry (2009) [8].
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Das, A.S., Gupta, P. & Srinathan, K. Data Structures for Extension Violations in a Query Range. J Math Model Algor 10, 79–107 (2011). https://doi.org/10.1007/s10852-010-9144-y
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DOI: https://doi.org/10.1007/s10852-010-9144-y