1 Introduction

CMOS technology is rapidly approaching the threshold of its limitation regarding feature size reduction to the nanoscale. To overcome this limitation, quantum-dot cellular automata (QCA) technology has been proposed as a possible alternative to replace conventional CMOS devices. Due to its high device density, extremely low power consumption, and very high switching speed, QCA could be of great interest, being first presented in 1993 by Lent et al. [1]. This new paradigm for computing is based on quantum effects, where information (signal) switching and propagation take place without any current flow but via the position of electrons [2]. Based on this new approach, QCA offers attractive features such as high speed, low power consumption, and extreme size reduction [3, 4]. Room-temperature-operable quantum cellular automata (to at least 293 K) have been implemented [5].

Two basic primitive logic structures for QCA are the inverter and the three-input majority gate [6]. However, due to the functional incompleteness of three-input majority logic, it cannot implement all functions without an inverter. Previous studies have suggested that design complexity is influenced by the majority and inverter gate count [7]. Recently, five-input majority logic has been of prime interest among researchers due to its varied functionality [8, 9]. In this regard, programmable computing using five-input majority logic is becoming increasingly desirable, due to its ability to generate new logical functions and be configured to deal with new situations to increase the efficiency of such systems [10, 11]. Other advantages of programmable computing include reductions in size and component count (and hence cost), which decreases the requirement for disparate hardware and increases the benefit of integrating more functionality on a chip. Very little effort has been invested in use of QCA in this way [12,13,14], and reliability issues have not been addressed.

Nanoscale integration cannot guarantee reliability and accuracy to the desired level [15]. The defect rates in nanoelectronic devices are projected to be several orders of magnitude higher due to their bottom-up stochastic assembly process [16,17,18]. According to [15], the requirement for high fault tolerance stems from the predictable huge complexity of such nano-architectures. Various types of cell deposition defects are the main obstacle to implementation of reliable QCA, as first explained in [17, 19]. At various levels of the design hierarchy, the major problem can be framed as building reliable nanocomputing systems from unreliable nanoelectronic devices [15, 20]. Reliability has therefore become an important issue for the success of any nanodevice [21].

On the other hand, the clocking scheme also plays a significant role in enabling the specification of standard cells, and the development of placement and routing algorithms for QCA, which is a critical requirement to enable this technology to advance. Signal transition and propagation for QCA cells are enabled by external clock signals. Several clocking schemes for QCA circuits have been suggested in previous works [22,23,24,25]. Unfortunately, most of this published work does not consider generation of such clocking circuit regions using fault-tolerant architecture. We present herein a scalable clocking scheme, which is regular, and flexible enough to enable fault-tolerant RP structures. Moreover, the architecture of the proposed clocking scheme can be fabricated using known and well-established fabrication technologies. The primary contributions of this work are as follows:

  • A scalable, regular, and efficient clocking mechanism implemented using a fault-tolerant architecture is proposed.

  • A generic, reliable and programmable (RP) QCA logic structure is designed, possessing high tolerance under different cell deposition (missing/additional) defects. The issue of fault tolerance is addressed herein from the architectural point of view.

  • The circuitry necessary to establish the electric fields for the regular clock zones is established.

  • Different multivalued logics (five and seven input) are explored to prove the flexibility and efficiency of the proposed structure. Detailed characterization of the functional properties of the proposed logic structures is reported.

  • Performance evaluation of the proposed fault-tolerant structure is performed and described.

The rest of this paper is organized as follows: Section 2 deals with the preliminaries, including a brief overview of QCA technology. Related works on fault-tolerant architectures are explored in Sect. 4. The fault-tolerant RP architecture and scalable regular clocking scheme for the aforesaid architecture are proposed in Sect. 5. The proposed design for a five-input reliable majority voter (5i-RMV) evolving from the RP architecture scheme is introduced in Sect. 6. In Sect. 6.1, the flexibility of the proposed five-input MV is reported. The reliability of the proposed 5i-RMV is analyzed in Sect. 6.2. In Sect. 6.3, synthesis of a full adder based on the 5i-RMV is reported. A seven-input RP logic device is designed in Sect. 7. The simulation and framework are elaborated in Sect. 3. The conclusions are presented in Sect. 8.

Fig. 1
figure 1

QCA basics: a structure of a QCA cell, b QCA cell with two polarizations, c majority voter, d inverter, e wire-crossing, and f clocking

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2 Preliminaries

A QCA cell consists of four quantum dots positioned at the corners of a square (Fig. 1a) and contains two free electrons [26, 27]. The two free electrons can tunnel quantum-mechanically among the dots and settle either in polarization \(\mathrm{P}=-1\) or in \(\mathrm{P}=+1\), as shown in Fig. 1b. A QCA cell with polarization \(\mathrm{P}=-1\) denotes logic state 0. On the other hand, polarization \(\mathrm{P}=+1\) defines logic state 1 of the cell.

The basic structure in QCA is the three-input majority voter, which is shown in Fig. 1c. The functionality in the output cell of majority logic depends on the polarity of the device cell, which is specified by the location of the electrons. Again, the electron position in the quantum dot of the central cell (device cell) is determined by the interaction of the other three cells surrounding it, which drives the polarity of the cell. It is found that the output of a majority voter is equal to the value of the majority of the inputs, which is equivalent to the Boolean function \(\mathrm {MV}(\mathrm {A}, \mathrm {B}, \mathrm {C}) = \mathrm {AB} + \mathrm {AC} + \mathrm {BC}\) (Fig. 1c). It can function as two-input AND or two-input OR logic, if any one of the three input cells is set to \(\mathrm {P} = -1\) or \(\mathrm {P}=+1\). The QCA inverter implemented in two different orientations is shown in Fig. 1d. Using a simple chain of rotated (\(45^{\circ }\)) \(+\)-cells, an inverter chain can be implemented as shown in Fig. 1d. In QCA-based logic, two varieties of wire-crossing, called coplanar and multilayer crossover, are possible. Due to assembly constraints, multilayer wire-crossing is not explained here. Figure 1e illustrates coplanar wire-crossing, considering a \(90^{\circ }\) (\(\times \)-cell) and a \(45^{\circ }\) (\(+\)-cell) structure.

Fig. 2
figure 2

QCA clocking zones controlling a wire

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2.1 Clocking in QCA

Timing in QCA is accomplished by cascaded clocking of four distinct and periodic phases [23, 26], as shown in Fig. 1f. In Fig. 1f, the basic four phases of the clock, i.e., switch, hold, release, and relax, are shown, being used for signal propagation, synchronization, and energy restoration in a row of cascaded QCA cells (Fig. 2). In the first (switch) phase, the tunneling barrier between two quantum dots starts to rise. This is the phase during which computation takes place; that is, the polarization of a QCA cell is reoriented through tunneling of electrons due to induction of polarization of neighboring cells. The second (hold) phase is reached when the tunneling barriers are high and prevents electrons from tunneling. In the third (release) phase, the barrier falls from high to low. The final (relax) phase ensures that there is no interdot barrier and the cell remains unpolarized.

One of the effective mechanisms to implement clocking in QCA circuits is to bury wires below the QCA surface, as proposed in [23, 25]. In this work, the creation of straight wires under the QCA cell layout is considered, as described in [23, 25]. Despite the favorable features of the 2DDwave clocking scheme, associated wiring layouts for fault-tolerant architectures remain a problem, which is a disadvantage, especially for reliability-aware programmable (RP) elements. That being said, to the best of the authors’ knowledge, no clocking schemes satisfy creation of RP elements of any length and well-defined clocking circuitry. In this work, we extend the 2DDwave clocking scheme in a symmetric manner to meet all these requirements. It is scalable as well as flexible to allow efficient and easy placement and routing of the RP logic unit.

2.2 Defects in QCA

According to [17, 19], defects are more likely to occur during the deposition phase (resulting in cell misplacement) (Fig. 3). These defects are mainly categorized into four types:

  • Cell omission/missing: A particular cell is missing or remains undeposited (Fig. 3b);

  • Cell displacement and misalignment: The defective cell is displaced from its original direction (Fig. 3c, d);

  • Additional cell deposition: An additional cell is deposited on the substrate (Fig. 3e). This extra cell is erroneously deposited along the device perimeter (adjacency boundary) of the original (defect-free) configuration (Fig. 3a);

  • Rotational defect: A cell is in the correct location but is not aligned in the same direction as its neighboring cell (Fig. 3f).

Fig. 3
figure 3

a Defect-free majority voter. b Missing cell. c Cell displacement. d Cell misalignment. e Additional cell. f Rotational cell defects

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3 Simulation environment

All the proposed logic structures were analyzed and simulated using the coherence vector engine in QCADesigner version 2.0.3 [28] using the following parameters for the simulation engine: cell dimensions = 18 nm \(\times \) 18 nm, dot diameter = 5 nm, grid spacing = 1 nm, temperature = 1 K, relaxation time = \(1.000000 \times 10^{-15}\) s, time step = \(1.000000 \times 10^{-16}\) s, total simulation time = \(7.000000 \times 10^{-11}\) s, clock high = \(9.800000 \times 10^{-22}\) J, clock low = \(3.800000 \times 10^{-23}\) J, clock shift = \(0.000000\times 10^{0}\), clock amplitude factor = 2.000, radius of effect = 80.000000 nm, relative permittivity = 12.900000, and layer separation = 11.50000 nm.

4 Prior work

Three-input majority logic (\(\mathrm {F}=\mathrm {AB}+\mathrm {BC}+\mathrm {AC}\)) can be programmed to AND/OR logic by setting any one input to 0 or 1. However, an inverter cannot be implemented using it. Likewise, AND/OR logic can be generated from a five-input majority gate by setting two of the five inputs to logical 0 or 1, respectively. The five-input majority gate realizes the Boolean function \(M (\mathrm {A}, \mathrm {B}, \mathrm {C}, \mathrm {D}, \mathrm {E}) = \mathrm {ABC} + \mathrm {ABD} + \mathrm {ABE} + \mathrm {ACD} + \mathrm {ACE} + \mathrm {ADE} + \mathrm {BCD} + \mathrm {BCE} + \mathrm {CDE} + \mathrm {BDE}\) [8, 14]. Since majority logic is not functionally complete, an inverter is required for majority logic (MI logic) to implement all Boolean functions. Hence, the programmable feature of existing majority logic is restricted due to its functional incompleteness. Different complex logics based on three-input majority logic were investigated in [14, 29]. By cascading/coupling multiple three-input majority gates, seven-input majority logic can be implemented [14]. Several attempts have been made to implement five-input majority gates in QCA for better programmability (Fig. 4a) [8]. Further endeavors have also been made to design fault-tolerant five-input majority logic, as described in [30, 31]. However, only 40 % success was achieved after introducing the tile structure. Another attempt was made to implement a fault-tolerant structure around majority logic [32] based on complementary tiles (CTs) of \(2\times 2\). To achieve a reliable architecture, such complementary/hybrid tiles (CTs) have been identified as a prominent approach, but only with three-input majority logic [32, 33]. These architectures are also not easily scalable and programmable. Multivalued logic based on such complementary tiles has not been implemented. Also, there is no regular, symmetric well-defined clocking mechanism to implement a generic fault-tolerant architecture around CTs. Finally, a novel programmable architecture using this five-input majority logic (known as PRC) has been explored [34] (Fig. 4b).

Fig. 4
figure 4

a Existing five-input MV [8]. b PRC proposed in [34]

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However, this programmable circuit is sensitive to the total distance (cell position) with no fault-tolerance capability. This cell placement factor is critical, because cells at different locations, i.e., distances from the main driver/central cell, are not the same (no regular assembly/arrangement of cells), making fabrication very difficult. Some logical functions of the five-input gate cannot be achieved due to the cells’ radius of effect and nonuniform distances from the device cells. The output depends on the relative position of the cell, which is defect prone. Also, no systematic methodology for synthesizing fault-tolerant programmable QCA structures has been fully investigated. All of these factors motivated us to design an efficient, reliable, scalable, and programmable architecture for QCA.

5 Proposed design of reliability-aware programmable (RP) QCA architecture with scalable clocking circuit

The tile structure is one of the well-established fault-tolerant architectures for QCA [21, 35, 36]. However, the redundant cells in each tile increase the cost and complexity of the circuit. This section investigates an alternative structure to achieve the desired (\({\approx }100\,\%\)) fault tolerance in QCA circuits that implement universal functions at the output. It also targets a compact implementation of this programmable logic structure. The fault-tolerance capability of the hybrid tile structure based on three-input majority logic was reported in [33], where it was concluded that construction with different cell orientations results in less kink energy, ensuring a more stable architecture. Here, the terms “reliable” and “fault tolerant” are used interchangeably.

Fig. 5
figure 5

RP fault-tolerant architecture for QCA

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Following the constraints of hybrid cells, the principal idea is to construct a generic, reliable and programmable (RP) scheme (with triangular shape) using normal cells at \(45^\circ \) and \(90^\circ \) orientation placed one after another (alternately), scaling from output to input (right to left \(\leftarrow \ll \)) as shown in Fig. 5. Note, the term “generic” is used here, as the proposed scheme can be extended to a number of input variables n (where n is any odd number \({\ge }5\)). As the number of inputs is increased, the triangular arrangement of cells (covered area) will increase. The basic unit of this design starts with five variables having a single clock. Five-input majority logic can be synthesized based on this basic module (as discussed below). The number of clock cycles required for the proposed majority logic gate depends on the number of input variables; i.e., the number of clock cycles increases with increasing number of input variables. A total of 0.25 clock cycles (where 1 clock cycle = 4 clock zones) is required for five-input majority logic, whereas 0.5 clock cycles are required for seven-input majority logic, and so on. In Fig. 5, green color indicates the cells in clock zone 0, whereas magenta color indicates the cells in clock zone 1. The red-colored arrow indicates the direction in which the circuit will grow. The circuit grows in three directions (left, up, and down), with the rightmost center cell being the output cell.

5.1 Clocking arrangement for proposed RP structure

Clocking is synchronized so as to propagate the signal from input to output (left to right) appropriately. For small-scale circuits, one clock zone is sufficient. However, as the circuit grows in the direction of the red arrow, the clocking will be enhanced for better stability. Figure 6 depicts the concept of the proposed clocking scheme. The idea of the clocking scheme is that clock zones consisting of pairs of rotated and nonrotated cells are always arranged in a fixed chevron shape. Initially, the output cell is surrounded by a pair of layers of normal (\(45^\circ \)) and rotated (\(90^\circ \)) cells in clock zone (n+1) in the chevron pattern shown in Fig. 6, i.e., the magenta-colored cells. Another two layers of normal (\(45^\circ \)) and rotated (\(90^\circ \)) cells of clock zone n are then placed in front of these cells in clock zone (n+1) in a larger chevron arrangement. Another two layers of normal (\(45^\circ \)) and rotated (\(90^\circ \)) cells of clock zone (\({n}-1\)) are then placed in a larger chevron arrangement, and so on. Likewise, a clocking panel with triangular shape can be positioned to synchronize the cell output. All the input cells are placed at the leftmost position of the structure in the lowest clock zone, i.e., clock zone 0.

Fig. 6
figure 6

Cell layout for RP fault-tolerant QCA architecture

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Depending on the circuit size, this clocking scheme can be replicated as necessary, as shown in Fig. 6. All clock zones in a given line of the scheme are arranged in a chevron pattern, following a sequence which defines the information flow from left to right. Therefore, all diagonal lines have a given direction, while adjacent diagonal lines always contain cells of opposite orientation. This allows the large number of routing paths necessary for fault-tolerant and programmable structures.

Fig. 7
figure 7

Clocking arrangement for proposed RP structure

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The basic circuitry for clocking in order to generate the electric fields for the required five-input programmable circuit is shown in Fig. 7a. It requires only one clock zone. In accordance with [23], diagonal metal wires are buried under the QCA design, through which the clock signal is passed to the QCA cells from a four-phase clock generator. The scheme described above can be used for a generic n-input programmable circuit (where n is any odd number). As shown in Fig. 7b, for a seven-input programmable circuit, an extra diagonal metal wire is added alongside the previous basic circuit. Here, the outer diagonal is connected to clock zone 0, whereas the inner diagonal is connected to clock zone 1. Thus, as the number of layers increases along with the number of inputs, the number of clock zones is also increased, with an additional layer having clock zone 0. Similarly, the nine-input programmable circuit will have three clocks. Based on the discussion above, the following lemma can be concluded:

Fig. 8
figure 8

QCA layout of proposed five-input reliable majority voter (5i-RMV) a Cell layout, b schematic view, c simulation result

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Lemma 1

For an n-input system, there will be \(({n}-3)/2\) clock zones.

Proof

For an n-input system (where \({n} \ge 5\)), it is observed that there are \((n-3)/2\) clock zones. As the cells in the proposed structure are scaled from the output to input, the innermost layer will be \([\{(n-3)/2\}-1]\%4\) (since there are four clock zones), and the following layers will have clock zones in decreasing order such that the input cells are in clock zone 0. For the seven-input circuit, the number of clock zones will be \((7-3)/2=2\), and the innermost layer of this structure will be clock zone \([\{(7-3)/2\}-1]\%4 = 1\). \(\square \)

Table 1 Truth table of 5i-RMV
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Table 2 Programmable parameters to obtain three-input Boolean logic
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6 Synthesis of five-input majority logic (5i-RMV) using proposed scheme

To exemplify the application of the proposed RP scheme, a reliable design of the five-input majority gate (5i-RMV) is proposed, using the hybrid cell orientation of the RP architecture (Fig. 8a) as opposed to the existing majority gate structure. It is well known that, if two cells are positioned diagonally with respect to each other, inverted polarization will propagate between them. In Fig. 8a, input A and C are placed diagonally from the corresponding internal logic cell, therefore always propagating their inverted polarization to the cell following them. Thus, in the truth table and function, we state these values as \(\overline{\mathrm {A}}\) and \(\overline{\mathrm {C}}\) to indicate the inverted values of A and C. Five-input majority logic is implemented as \(F(\overline{\mathrm {A}}, \mathrm {B}, \overline{\mathrm {C}}, \mathrm {D}, \mathrm {E}) = (\overline{\mathrm {A}}\mathrm {B}\overline{\mathrm {C}}) + (\overline{\mathrm {A}}\mathrm {BD}) + (\overline{\mathrm {A}}\mathrm {BE}) + (\overline{\mathrm {A}}\overline{\mathrm {C}}\mathrm {D}) + (\overline{\mathrm {A}}\overline{\mathrm {C}}\mathrm {E}) + (\overline{\mathrm {A}}\mathrm {DE}) + (B\overline{\mathrm {C}}\mathrm {D}) + (B\overline{\mathrm {C}}\mathrm {E}) + (\overline{\mathrm {C}}\mathrm {DE}) + (\mathrm {BDE})\), as presented in Table 1. A schematic diagram of the equivalent proposed majority logic (five-input MV) is shown in Fig. 8b. The QCA implementation of the proposed 5i-RMV (Fig. 8a) has cell count of 14 and delay of 1 clock zone (0.25 clock cycles). The design covers an area of \(0.01\,\mu \hbox {m}^2\).

For different combinations of the inputs, the corresponding output values are presented in Table 1. In the 5i-RMV, five \(+\)-cells placed in front of the input cell and three \(\times \)-cells placed around the output cell play the role of the logic driver. The internal logic behind this structure is that all the inputs are isolated from the driver cell by a diagonal chain of rotated cells to increase the fault tolerance. The influence of the input cell is fully controlled by the \(+\)-cell, so that stable signal transition occurs. The simulation results shown in Fig. 8c validate the operation of the 5i-RMV circuit.

6.1 Programmable computing with proposed (5i-RMV) circuit

The proposed multivalued 5i-RMV logic circuit can be utilized to generate primitive AND, OR, and MV logics for three variables efficiently. Inverter logic can also be implemented using the proposed 5i-RMV. This circuit can be programmed accordingly by applying different values to the inputs. In the 5i-RMV circuit, the output is affected by the inverting effect of input cells A and C; however, the majority value of the five inputs is computed.

Synthesis of three-input AND, OR, and majority logic using the proposed 5i-RMV Three-input gates are implemented when two input cells function as control cells. From the five-input cell, any three are chosen and the other two input cells are used to control the output (Fig. 8b). When fixing the two control cells to logical 0 or 1, the resulting functionality of the circuit is presented in Table 2, confirming its operation as OR, AND, and majority logic. The proposed programmable majority gate can realize the maximum number of majority functions possible, as presented in Table 2.

6.2 Defect characterization of proposed 5i-RMV

To analyze the fault-tolerance capability of the proposed 5i-RMV, the fault model described in [17, 19] was considered. The cell deposition defect is the prime source of QCA defects. Here, single and double missing cell defects, additional cell deposition defects, and the displacement tolerance of the cells were considered. The possible positions of cell deposition defects are shown in Fig. 9.

6.2.1 Missing cell defects

The cell deposition location of the faulty 5i-RMV is depicted in Fig. 9. One or more cells may be missing from its position in a QCA circuit. Table 3 presents the simulation results when at most one cell of the 5i-RMV is not deposited. The first column of Table 3 indicates the missing cell position (Fig. 9), the second column indicates the polarization of the output cell, and the last column states the output function of the 5i-RMV when that particular cell is missing. Once missing cell defects are present, the input signals may also interact and different functions can be generated at the output. In particular, variants of the majority function (with complemented input variables) are expected due to possible input inversion through the cells of the circuit. The variants of the majority function are referred to as MV-like functions.

Fig. 9
figure 9

Cell positions of 5i-RMV for missing and additional cell deposition

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The following observations can be drawn from these simulation results:

  1. (1)

    In almost all cases, our proposed 5i-RMV with undeposited cells (as defects) behaves in the following two ways: undefined functions or MV/MV-like functions.

  2. (2)

    Undeposited cell defects around the output cell (cells 3, 6, and 7) change the logic function of the RMV to undefined values. All other cases of single missing cell defects have no effect on the output, confirming the 62.5 % defect-tolerant design.

  3. (3)

    In the simulations using the coherence vector engine, the polarization level never experienced a significant drop under missing cell defects. In all the simulated occurrences, the magnitude of the maximum polarization was above 0.9 eV. The statistical results in the presence of up to eight undeposited cells are summarized in Table 3. Note that, by definition, the MV-like function set does not include the MV function.

Table 3 Functional characterization of 5i-RMV under single missing cell defects
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Table 4 Overall functional characterization of programmable logics under missing cell defects
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We analyzed the behavior of the proposed programmable logic (5i-RMV) and the existing five-input programmable logic circuit (Fig. 4) from literature with respect to missing cell defects. Single and double missing cell defects of such gates are presented in Table 4. The probable function implemented in the event of a missing cell defect is listed in column 1 of Table 4, while columns 2 and 3 report the number of cases a function is implemented out of all possible single and double missing cell defects in PRC [34]. Columns 4 and 5 report the effect of single and double cell defects in the proposed 5i-RMV. From the results in Table 4, it can be observed that, under single missing cell defects, the probability of having the correct majority function at the output is 62.5 % for the 5i-RMV, whereas the existing programmable approach [34] achieves no success. Again, for double missing cell defects, the proposed 5i-RMV logic achieves 35 % tolerance, whereas existing majority logic gates show 0 % tolerance. The average magnitude of the maximum polarization level of the output when a number of cells are not deposited as defects is shown in Table 5. From the results in Tables 4 and 5, it can be concluded that the proposed 5i-RMV logic circuit performs better in presence of missing cell defects, showing prominent fault tolerance, whereas the existing programmable circuit shows no success.

Table 5 Average maximum polarization on missing cell deposition for PRCs
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Table 6 Additional cell deposition output function for 5i-RMV
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6.2.2 Additional cell deposition defects

This subsection investigates the effect of additional/extra single cell deposition defects on the 5i-RMV gate. An extra cell (with \(\times \) or \(+\) orientation) was placed in any of the regions around the proposed programmable majority gate to investigate defects arising due to additional cell deposition. The layout showing the possible positions (P, Q, R, S \(\ldots \) X, Y, etc.) susceptible to the additional cell defect is shown in Fig. 9. The functional behavior in the event of all possible extra cell deposition positions for the 5i-RMV is reported in Table 6. The first column of this table indicates the defective cell position, the second column indicates the orientation type, i.e., rotated (\(+\)) or not (\(\times \)), of the defective cell, the third column reports the clock zone of the cell, the fourth column reports the polarization of the output cell, and the fifth column reports the functional behavior of the output. Likewise, other columns of the table report the behavior and polarization of the output cell in the presence of the other orientation of the extra cell. From the results in Table 6, it can be inferred that the 5i-RMV is 55.56 % fault tolerant under additional cell deposition defects (Table 7).

Table 7 Performance of five-input majority logics
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6.2.3 Displacement tolerance for programmable block

Besides missing cells and deposition of extra cells, the relative position of cells also has some impact on the structure. So, the displacement tolerance of the cells from the original position plays a vital role in synthesis of error-free circuits. To analyze the displacement tolerance of the circuit, the cell layout of the 5i-RMV was described by a network of nodes (cells) as shown in Fig. 10. The cells of the 5i-RMV were divided into two classes based on their connection with the driver cell, i.e., loosely and tightly coupled cells. A cell is considered loosely coupled if a node is connected to another one or two nodes of the circuit, whereas if a node is connected to more than two nodes, it is called tightly coupled. It is noteworthy that tightly coupled cells have greater influence on the circuit than do loosely coupled cells. The maximum displacement of the cells beyond which the circuit will not perform correctly is reported in Table 8.

Fig. 10
figure 10

Network diagram of 5i-RMV

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Table 8 Displacement tolerance of loosely coupled cells in 5i-RMV
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Fig. 11
figure 11

Comparative analysis for displacement tolerance (DT)

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Comparative analysis of the displacement tolerance of the circuits is also shown in Fig. 11. It is evident from Fig. 11 that the proposed 5i-RMV has a greater tolerance (displacement) value than existing PRC [34]. The overall performance analysis of the programmable logic circuit is presented in Table 7. The proposed 5i-RMA outperforms all the existing five-input logic circuits in terms of design complexity as well as fault-tolerance capability.

6.3 High-level logic synthesis

Several attempts have been made towards implementation of efficient full adders [37,38,39,40,41,42,43,44,45]. Most earlier attempts addressed how to obtain cost-efficient full adders in terms of area (reducing the cell count) and delay (response time) only. In this section, the fault-tolerance capability of the proposed logic is further extended by implementing the full adder circuit shown in Fig. 12.

Fig. 12
figure 12

QCA layout of proposed coplanar full adder using programmable logic (5i-RMV). a Cell layout of the full adder. b Simulation result

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A single-bit full adder representation is considered sufficient for evaluation of the fault-tolerant architecture. Increasing the number of bits for a carry look-ahead (CLA) adder means greater error propagation from faulty devices, which decreases the overall fault tolerance. If the one-bit adder circuit has a high fault rate, then a multibit form of the aforesaid will definitely be much less fault tolerant. So an analysis of a one-bit full adder is considered here.

The individual performance of the 5i-RMV implementing the full adder is reported in Table 9. It is evident from the results in this table that the 5i-RMV retains its fault-tolerant capability at circuit level. Also, the overall performance of the full adder circuit (taking into account all wires and other modules) in the presence of 5i-RMV is estimated as shown in Table 10. The results in this table imply that an efficient, fault-tolerant full adder can be synthesized based on the proposed 5i-RMV.

Table 9 Performance of 5i-RMV implementing full adder under missing cell defects
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Table 10 Performance of ft-FA under missing cell defects
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Fig. 13
figure 13

Seven-input gate based on RP architecture

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7 Discussion: seven-input RP structure

Similarly, a seven-input programmable logic gate can be planned based on the proposed generic RP architecture, as depicted in Fig. 13. The function implemented by this gate is \(\mathrm {OUT}(\mathrm {A}, \mathrm {B}, \mathrm {C}, \mathrm {D}, \mathrm {E}, \mathrm {F}, \mathrm {G}) = \overline{\mathrm {B}}\mathrm {E} + \overline{\mathrm {B}}\mathrm {D} + \overline{\mathrm {A}} \overline{\mathrm {B}} \overline{\mathrm {C}} + \overline{\mathrm {A}} \overline{\mathrm {B}}\mathrm {G} + \overline{\mathrm {B}} \overline{\mathrm {C}}\mathrm {G} + \overline{\mathrm {A}} \overline{\mathrm {B}}\mathrm {F} + \overline{\mathrm {B}} \overline{\mathrm {C}}\mathrm {F} + \overline{\mathrm {B}}\mathrm {FG} + \overline{\mathrm {A}} \overline{\mathrm {C}}\mathrm {DEG} + \overline{\mathrm {A}} \overline{\mathrm {C}}\mathrm {DEF} + \overline{\mathrm {A}}\mathrm {DEFG} + \overline{\mathrm {C}}\mathrm {DEFG}\). By fixing polarizing inputs with different values, multiple functions can be generated from the same device, thus validating the multiprogrammable feature of the device.

One such example to illustrate the programmability is given here. Fixing inputs \(\mathrm {A} = +1\), \(\mathrm {C}=-1\) and \(\mathrm {B}=-1\), one gets \(\mathrm {OUT}= \mathrm {D} + \mathrm {E} + \mathrm {F} + \mathrm {G} +\mathrm {DEFG}\). \(\mathrm {OUT}= \mathrm {D} + \mathrm {E} + \mathrm {F} + \mathrm {G} + \mathrm {DEFG}\) can also be obtained by setting \(\mathrm {A} = -1\), \(\mathrm {C} = +1\), and \(\mathrm {B} = -1\). Now this function can be made to act as a three-input OR gate by fixing any of D, E, F, and G to \(-1\), as follows:

  • If \(\mathrm {D}=-1\), \(\mathrm {OUT} = \mathrm {E} + \mathrm {F} + \mathrm {G}\),

  • If \(\mathrm {E}=-1\), \(\mathrm {OUT} = \mathrm {D} + \mathrm {F} + \mathrm {G}\),

  • If \(\mathrm {F}=-1\), \(\mathrm {OUT} = \mathrm {D} + \mathrm {E} + \mathrm {G}\),

  • If \(\mathrm {G}=-1\), \(\mathrm {OUT} = \mathrm {D} + \mathrm {E} + \mathrm {F}\).

Another such example is fixing \(\mathrm {B} = -1\), \(\mathrm {D} = -1\), and \(\mathrm {E} = -1\), in which case the function becomes \( \mathrm {OUT} = \overline{\mathrm {A}}\) \(\overline{\mathrm {C}} + \overline{\mathrm {A}}\mathrm {G} + \overline{\mathrm {C}}\mathrm {G} + \overline{\mathrm {A}}\mathrm {F} + \overline{\mathrm {C}}\mathrm {F} + \mathrm {FG}\). By fixing either \(\mathrm {F} = -1\) or \(\mathrm {G} = -1\), one gets \(M(\overline{\mathrm {A}},\overline{\mathrm {C}},\mathrm {G})\) or \(M(\overline{\mathrm {A}},\overline{\mathrm {C}},\mathrm {F})\). These examples highlight the programmability of the seven-input RP structure.

8 Conclusions

A regular, symmetric, and scalable clocking structure for a fault-tolerant QCA architecture is proposed. A generic reliable and programmable (RP) QCA architecture with hybrid cell orientation is designed based on the proposed clocking scheme. A reliable five-input programmable circuit (5i-RMV) is established as a basic logic module to allow QCA technology to advance. Defect characterization of the proposed 5i-RMV reveals fault tolerance of 62.5 % under single cell deposition defects, increased in comparison with existing programmable logics. Furthermore, the fault-tolerance capability of the proposed logic module is shown to extend to circuit level by implementing a fault-tolerant full adder. Also, a seven-input RP structure is explored for the sake of continuity. Similarly, this work can be extended to any number of inputs, demonstrating its generic property.