1 Introduction

During the last decades, every year the microelectronics field has become more demanding to engineers and technology to achieve even more compact electronic systems and higher energy efficiency due to increased demands imposed by the widespread use of battery-powered portable equipment. The effort towards miniaturization gave birth to the System on Chip (SoC) design strategies, in which the maximum number of electronic components are integrated together on the same die, thus reducing volume, weight and, in most cases, cost. This trend has recently embraced on-chip power supplies, since the ultimate step in miniaturized power management circuits consists in the fully monolithic integration of the power converter together with the same circuits which constitute its load, particularly in standard CMOS [1–6], as an extension to a low power scenario of the research activities in the field of system-in-package integration of high power converters [7, 8]. Apart from benefits in terms of compactness, better signal integrity and higher efficiency at circuit level, the availability of on-chip power conversion in turn enables aggressive system-level power management policies, such as adaptive voltage scaling (AVS) [9] in digital circuits, in which the supply voltage is adapted to the processing requirements, and adaptive supply of RF power amplifier circuits, such in as envelope-tracking transmitter architectures [10, 11].

Recently, triggered by cost and by the need of shorter time-to-market delays, factors as reusability and migration easiness have increasingly constrained analog designs when design specifications forbid the use of digital approaches, since they require careful tuning and simulation and the layout has to be redesigned for each CMOS process.

Even though power converters are inherently continuous-time switched systems, increased efforts have been addressed towards integration of their controllers, to be used as part of larger SoC systems for on-chip power management policies [12–14] and the digital design of their key building blocks [15–17]. Several problems arise when power converter control is fully digitally implemented [18], especially for low-power applications such as on-chip power management where the power consumed by the controller can be of the same order of magnitude as the converter output power and a large area overhead may result.

The first generation of digital controllers for switching DC–DC power converters [15, 16, 19] aimed to provide comparable performance to their continuous-time analog counterparts in terms of dynamic performance as well as use of implementation resources (silicon area and power consumption) while providing extended functionality, such as programmability, and practical interest due to the ease of synthesis. A decade later, the ultimate goals for the next generation of digital controllers encompass both aspects of integration and functionality [20]. In terms of integration, the aim is to provide simple switched-converter-specific practical controller realizations with the advantages of CMOS process scaling and digital IC design flow with continuous improvements in the area/power/processing space [20–25]. As far as functionality is concerned, the target is to address enhanced performance that is impractical or challenging by means of the analog approach, namely: system integration and system-level power management [26], full programmability, testability, self-diagnostics, self-tuning [27], adaptability, on-line efficiency optimization [6], on-line calibration and nonlinear control with enhanced dynamics [28].

However, several partial challenges in digital switched-mode converters are still open: (a) those fundamentally related to time quantization (inherent to discrete-time systems) such as aliasing of signal frequencies, modification of system Bode plots and filter corner frequencies shift with sample rate [29, 30], (b) related to amplitude quantization, such as limited resolution for regulation, limit cycling disturbances, distorted waveforms, rounding of filter corner frequencies (finite word lengths) [31], and (c) the availability of cost-effective high-performance hardware, such as dedicated hardware processing blocks and controller design and coding to minimize hardware requirements [32], in which this work is framed.

Lately, some research works explore digital control methods which do not mimic the constant switching frequency analog PWM counterpart, but instead consider finite-state-machine based zonal control, both for adaptive dead-time control [33], as well as enhanced linear [34–36] and nonlinear control laws [28]. This approach enables in turn to implement adaptive and flexible control methods, such as hybrid control and space state zone-wise control, and system-level power management.

Aligned with this trend, recently, asynchronous finite-state machines were proposed by the authors [37] as simple, low-cost and short-design-cycle controllers for power converters. In contrast to usual synchronous digital circuits, in which the controller states do not change until the next clock active edge, states in digital asynchronous controllers can change at any time as a reaction to an input change. Thus, contrary to the clocked systems, signals in asynchronous circuits are self-timed. Consequently, they exhibit an extremely low latency without the need of high-frequency clock, so dissipated power is kept at very low levels since no unnecessary signal transitions are required [38, 39]. If proper design techniques are used, the advantages of automated are also kept [39, 40]. The digital asynchronous design, although not mainstream, has been applied in many different areas where low consumption or self-timing are required, as, for example, in energy harvesters [41], current sensing [42], or hostile environments [43].

Even if the converter is fully integrated, and the controller is fully digital, as far as functionality is concerned, note that most of on-chip efficient power management circuits usually focus on integrating a regulator, a circuit which pursues a stable output regardless of perturbations in both the output load and input power source. Nevertheless, there are indeed a few challenging applications in which the converter output is forced to track a wideband time-varying signal. Among the different applications for such wideband amplifiers, we could point out three cases with stringent specifications, namely: (a) MEMS-based capacitive actuators, where the positive-feedback pull-in effect can be overcome applying time-variable supply [44], (b) System-level optimization of power consumption in digital circuits, via AVS scheme [16, 45], (c) Envelope elimination and restoration or Kahn technique [10, 11], which theoretically allows implementation of linear highly efficient RF transmitters. One of the key remaining challenges for a successful realization of such systems that has been recently explored [46–50], is the practical implementation of the efficient, wide-bandwidth tracking power converter.

In this article, we present a noninverting buck-boost power converter with tracking capabilities controlled by a digital asynchronous finite-state machine. The power converter architecture is presented in Sect. 2. Section 3 explains the implementation details of the controller and experimental results are presented in Sect. 4.

2 System architecture

2.1 Main blocks

The architecture of the proposed power converter is depicted in Fig. 1. Transistors M 1, M 2, M 3, M 4N , M 4P and M 5 are power MOS transistors and M 2b , M 3b M 6 and M 7 are small switching transistors used to multiplex the U 1 comparator inputs. V IN represents the input voltage, L the external inductor and C L and R L the load model at the output node V OUT .

Fig. 1
figure 1

Power converter architecture. M 1, M 2, M 3, M 4N , M 4P and M 5 are power MOS transistors and M 2b , M 3b , M 5 and M 6 are small MOS transistors, all driven by the AFSM controller. Both U 1 and U 2 are voltage comparators, but U 2 additionally provides a window-comparator functionality

Full size image

Except for transistor M 5, this architecture is known as the noninverting buck-boost (see, for example, [17, 51, 52]). Those combine two converters that share the same inductor: a step-down (buck) converter with a step-up (boost) converter, enabling to obtain a greater or lower output voltage than the input voltage. In this case, transistor M 5 plays an important role in the working principle of the system as a means of returning unnecessary energy stored in the inductor back to the source, as it will be explained later. The transistors gates are logically driven by the asynchronous finite-state-machine (AFSM) through an inverter chain working as a pre-driver in case of the power transistors or directly in case of the multiplexing transistors. The M 4 switch was implemented as a pass-gate formed by M 4N and M 4P in case of the output voltage is required to go close to zero, below the threshold voltage of the PMOS transistor.

U 1 is a voltage comparator used to sense the inductor current. The M 2b and M 3b switches allow to select if the current is sensed as the V DS voltage drop of either M 2 or M 3, depending on which one is active. The inductor current I L is related to the sensed voltage V DS of M 2 or M 3 by

$$ I_L=\frac{V_{DS}}{R_{ON}} $$
(1)

where R ON is the ON resistance of transistors M 2 and M 3. On the other hand, the M 6 and M 7 switches allow to select whether the inductor current is compared with zero to know when the inductor has completely discharged or with a constant voltage V LIM to know when the inductor current has reached the I LMAX  = V LIM /R ON threshold.

This U 1 comparator architecture has a PMOS transconductor as input stage, a current comparator as reported in [53] as second stage and a chain of logic inverters working as amplifiers as output stage. Since the comparator has to sense only small voltages, it is not necessary to use rail-to-rail transconductors in the input stage. The current comparator on the second stage provides a very effective voltage clamping effect at the transconductor output, making it much less sensitive to the parasitic capacitances that would otherwise make the overall comparator very slow. This architecture has proven to give response times below 8 ns with input changes of only 2 mV and <1 mW of dissipated power.

The voltage comparator U 2 is used to compare the output voltage V OUT to the reference voltage V REF that the converter must follow. Its architecture is based on a rail-to-rail input transconductance stage like the one reported on [54], but with the addition of two output stages that provide the functionality of a standard comparator (V OUTC output) and of a window comparator (V OUTW output). The behavior of the window comparator is described by the following equation:

$$ V_{OUTW} = \left\{ \begin{array}{l} V_{OH} : |V_{REF}-V_{OUT}| < V_{RIP}/2\\ V_{OL} : |V_{REF}-V_{OUT}| > V_{RIP}/2 \end{array} \right. $$
(2)

where V OH and V OL are, respectively, the voltages of the logic 1 and logic 0, and V RIP is the window width of the comparator, which is related to the V OUT ripple. Also, this window functionality is useful for detecting when the output voltage is close to the reference and thereby the converter can be deactivated, allowing for example, to automatically reduce the switching frequency if the window width is adjusted close to the maximum ripple voltage allowed by the load, thus increasing efficiency.

2.2 AFSM controller

The control of the power converter relies on the finite state machine diagram depicted in Fig. 2. In this state diagram, each circle represents a major state of the controller and in each one, there is a particular set of active transistors that provide a certain functionality in the power plant. The arrows departing from each state indicate the new states where the AFSM controller can jump into. A jump between states occurs when the conditions shown near each arrow as logical functions are fulfilled. To better understand the working principle of the controller, the purpose of each state is described in the following list:

  • ChgL charges the inductor until its current reaches the specified limit V LIM /R ON . When this occurs, the state jumps to LtoC. Active transistors are M 1, M 3, M 3b and M 6.

  • LtoC transfers energy from the charged inductor to the output load. If the output voltage reaches the reference, it jumps to LtoV to return the remaining energy of the inductor to the source. If the inductor discharges completely without the output voltage reaching the reference, the state jumps to ChgL to begin another charging cycle, but in case that the difference between the output voltage and the reference is small (less than V RIP /2) the state jumps to Idle instead of ChgL. Active transistors are M 2, M 2b , M 4 and M 7.

  • LtoV returns the remaining inductor energy (if any) to the source. When it is done, it jumps back to ChgL if the output voltage is well below the reference or to CtoL if it is well above. If the difference is small, it jumps to Idle. Active transistors are M 2, M 2b , M 5 and M 7.

  • CtoL transfers energy from the capacitor to the inductor (thus decreasing the output voltage) until it reaches the reference V REF or the inductor current reaches the I LMAX limit. Then it jumps to DisL. Active transistors are M 2, M 2b , M 4 and M 6.

  • DisL returns energy to the source. When it is done it jumps to CtoL if the output voltage is still well above the reference or to ChgL if is well below. Again, if the difference is small, it jumps to Idle instead. Active transistors are M 1, M 3, M 3b and M 7.

  • Idle waits until the absolute difference between the output voltage and the reference is higher than V RIP /2. When this happens and the output voltage is below the reference the state jumps to ChgL and a charging cycle starts. When it is above the state jumps to CtoL and a discharging cycle starts. There are no active transistors in this state. This allows for disconnecting the power converter for reducing its switching frequency when the output ripple or the load are small.

Fig. 2
figure 2

Finite state machine controller diagram. Each state shows the active transistors \(M_{1{\ldots}7}.\) The jump conditions are represented as physical variables instead of the comparator outputs for clarity purposes

Full size image

In Fig. 3, a transistor-level simulation of the output voltage, inductor current and active state shows the power converter behavior. Since the reference voltage V REF is changed from 3.3 to 0 V, both charging and discharging cycles can be observed. Note how the power converter deactivates itself when the difference between V REF and V OUT is small by entering the Idle state, effectively reducing the switching frequency.

Fig. 3
figure 3

Transistor-level simulation of the power converter. The top graph shows the output voltage V OUT and the reference voltage V REF , which changes from 3.3 to 0 V at t = 15 μs. The plot in the middle shows the inductor current I L and the bottom plot shows the FSM active state. C L was initially discharged and its capacitance was set to 180 nF. The inductor L was set to 10 μH and the load resistor R L to \(500\,\Upomega.\)

Full size image

Each one of the major states presented in the previous list and in Fig. 2 is composed of three minor states (or substates) that provide important functionality to the power converter. These substates are described in the following list:

  • Stabilization activates the required transistors by each major state of the power converter and waits for a specified amount of time, determined by a delay line made of a chain of starving inverters, until the comparator outputs stabilize. This avoids anomalous behaviors due to the nonzero response time of the comparators. When the settling time has elapsed, it jumps to Process.

  • Process monitors the comparators outputs until some jump condition is fulfilled. Then, it jumps to Deadtime.

  • Deadtime deactivates the transistors that can cause a current shoot-through between the state transitions for a specified amount of time, determined by a chain of starving inverters. This avoids loosing efficiency for this reason. Then it jumps to the next major state, specifically to its Stabilization substate.

A key difference between this architecture and the classical non-inverting buck-boost topology Sahu and [17, 51, 52] is transistor M 5. Its sole purpose is to return the remaining inductor energy to the source when it has been over-charged (state LtoV). This significantly eases the task of the AFSM controller since there is no need to estimate how much energy is required by the inductor, so it can be charged to a fixed level I LMAX and return the unused energy back to the source. With this technique, only a minimum of two bits are necessary to control the complete power converter, one related to the inductor energy and other related to the output voltage. Experiments show that this process only degrades the power converter efficiency by <1.25 %. Anyway, further improvement can be obtained by using a dynamic V LIM or I LMAX signal or increasing the complexity of the AFSM and the number of bits used to monitor the status of the power converter.

Due to the discontinuous nature of the current flowing through V IN , the power source has to present a low-impedance at high frequencies or it will become deregulated. Also, if the converter is intended to operate frequently in the DisL or LtoV states (thus, frequently returning energy to the source), the power source has to be able to efficiently handle this returned energy. Usually this is accomplished if the voltage source is adiabatic in nature, if a capacitor is used to store this returned energy for a later usage, or if some other circuitry is also connected to the voltage source and is able to drain the returned energy. In case this returned energy is not absorbed, it will eventually dissipate through the junction diodes of the power transistors, thus increasing the risk of triggering a latch-up event.

3 Implementation details

The AFSM controller was described directly at gate level to avoid using automated synthesis logic transformations that could have caused hazards or glitches in the state signaling. While these glitches can be tolerated in synchronous circuits as long as they disappear before the next clock event, in asynchronous circuits, as it is the case, they pose significant problems since they can not be easily distinguished from real signal transitions. With gate-level descriptions, however, the hazards can be avoided if proper design techniques are used [38], while the advantage of using automatic place and route tools is still kept.

Each substate was implemented using gate-level descriptions of generalized C (gC) [55] elements, as depicted in Fig. 4. gC elements can be understood as SR latches without forbidden or restricted state, thus having the state transition table shown in Table 1. gC elements also provide static hazard or glitch isolation between the inputs and the output [38] that could cause the AFSM to malfunction. The set signal of each gC element is generated by performing a logical AND operation between the output of the substate the controller can jump from and the jump condition itself, while their reset signal is generated by performing a logical OR operation of the outputs of the substates the controller can jump to. This way, the previous state is not reset until a new one is active. This simple signaling technique provides both speed and reliance in the AFSM state transitions without the need of a clock.

Fig. 4
figure 4

Generalized C-element gate-level implementation. S is the set signal, R is the reset signal and Q is the output

Full size image
Table 1 Generalized C-element state transition table
Full size table

The power converter was manufactured using the ON Semiconductor C035U-A 0.35 μm CMOS process. As depicted in the microphotograph of Fig. 5, it integrates the full converter (including the power transistors) with the exception of the inductor L and the output capacitor C L . A very low ESR (Equivalent Series Resistance), metal-metal, comb-like, 8.7 pF input capacitor C IN (not shown in the schematic of Fig. 1) was added at the input V IN to reduce its high-frequency impedance and mitigate the effect of the pulsed-like nature of the current flowing through V IN . This capacitor was sized and placed in the unused space below the pad routing of the power transistors.

Fig. 5
figure 5

Microphotograph of the power converter. The dotted lines indicate the position of the six power transistors \(M_{1{\ldots}5},\) the input capacitor C IN , the pre-drivers, the comparators, the starving inverters working as delay lines and the AFSM. Area is 760 × 835 μm2

Full size image

Also, guard rings and deep wells (readily available in the manufacturing technology) were implemented around all blocks to reduce the noise and interference generated by the power transistors and digital blocks. Decoupling capacitors in the supply lines were also used to reduce interference. Guard rings and decoupling took more than 80 % of the comparators and delay lines layout area. Power transistors were sized in order to have a \(R_{ON}=0.5\,\Upomega\) and, in order to reduce the interconnection resistance, they were connected through a stack of the top three metal layers. Also, power line pads were sized so that double wirebonding could be used. The external inductor has a L = 10 μH and a series resistance of \(R_S=0.3\,\Upomega\) according to manufacturer technology datasheet. The load capacitance was set to C L  = 180 nF.

4 Experimental results

The manufactured integrated circuit has been successfully tested under various load, input voltage and reference voltage conditions. The power consumption of the controller itsef has been measured, and reaches 3.3 mW for the analog blocks (comparators and delay lines) and 2.7 mW for the digital blocks (AFSM and pre-drivers). According to simulations, around 25 % of the power consumed by the digital blocks belongs to the AFSM and the remaining 75 % is due to the pre-drivers. Analysis indicate that the power consumed by the controller would have been more than ten times higher if it would have been implemented with a synchronous digital circuit instead of an asynchronous one. On the other hand, the power consumption of the analog blocks is easily reduced if the bandwidth or delay specifications are relaxed, and the power consumption of the digital blocks significantly decreases as switching frequency is reduced. The presented prototype was designed to operate with a switching frequency up to 10 MHz and a tracking bandwidth of 1 MHz, but prototypes with lower switching frequencies (≈100 kHz) can reduce the power consumption of the converter to a small fraction of those values, well below the mW range.

Figure 6 shows a measurement of the steady state response of the power converter for a constant V REF of 3 V and a constant input voltage V IN of 3.3 V. The voltage V LIM , that limits the peak current drained by the inductor, was adjusted to a level so that the AFSM never enters the Idle nor the LtoV state (no energy is returned to the source) with the selected minimum load resistance R L of \(89\,\Upomega\) but yet the output voltage V OUT is still able to reach the reference. Measurement shows that the output ripple voltage is 84 mVpp, the efficiency is 77.3 % and the output power is 100 mW. The AFSM-state changes from ChgL to LtoC in a cyclic pattern with a 1.48 MHz frequency. Under those conditions, load resistance below \(89\,\Upomega\) will make the output voltage to drop since the converter is not able to deliver more energy to the load, and with load resistance above \(89\,\Upomega,\) the AFSM will enter in LtoV and Idle states and reduce its switching frequency until the peak-to-peak output ripple voltage equals V RIP .

Fig. 6
figure 6

Measurement of the steady-state response of the power converter. V IN was set to 3.3 V, V REF to 3 V and R L to \(89\,\Upomega.\) Efficiency reaches 77.3 % with a switching frequency of 1.48 MHz. Output ripple is 84 mVpp

Full size image

Figure 7 shows a measurement of the power converter efficiency versus output power and Fig. 8 shows the efficiency and output voltage for different resistive loads. In both plots, V IN was 3.3 V, V REF was set to 3 V and V LIM was calibrated so at \(R_L=125\,\Upomega\) no energy was returned to the source. With this load, steady state measurements indicated a 2.86 MHz switching frequency and a 80 % efficiency. As it can be seen, efficiency decreases as load resistance increases. Additional tests show that this is not due to losses caused by the returning to the source of the excess energy stored in the inductor (AFSM entering in the LtoV state), but mainly to losses caused by lack of optimization in the switching synchronization of the power transistors. The energy returning to the source only accounts for 1.25 % of the losses at \(R_L=300\,\Upomega,\) in consequence, implementation of deadtime optimization techniques could substantially improve the power conversion efficiency of this architecture.

Fig. 7
figure 7

Measurement of the power converter efficiency versus output power. V IN was set to 3.3 V and V REF to 3 V

Full size image
Fig. 8
figure 8

Measurement of the power converter efficiency (left axis, solid line) and output voltage (right axis, dashed line) for different load conditions. Vertical dotted line indicates the calibration point of V LIM at \(R_L=125\,\Upomega. V_{IN}\) was set to 3.3 V and V REF to 3 V

Full size image

Figure 8 also indicates that the output voltage is kept fairly constant with resistive loads above the calibration point of V LIM . Below the calibration point, the output voltage drops because the energy transferred by the inductor to the load is not enough to keep V OUT at the value specified by V REF . Increasing the value of V LIM gives an output voltage load regulation with <100 mV of variation over the range \(70\, \Upomega<R_L<350\,\Upomega\) without significantly affecting the efficiency.

Figure 9 shows the efficiency of the power converter for different values of the input voltage V IN . V REF was set to 3 V, so an input voltage below it makes the power converter to operate in boost mode and an input voltage above it makes the power converter operate in buck mode. Note how the efficiency drops when lower V IN input voltages are available due to the increased current flowing through the transistors (and hence, increased dissipated power) for the same load and output voltages. Additional measurements indicate that the output voltage drops 70 mV over the same range.

Fig. 9
figure 9

Measurement of the power converter efficiency for different values of the input voltage V IN . Load resistor R L was set to \(125\,\Upomega\) and V REF to 3 V. The vertical dotted line indicates the limit between boost (left side) and buck (right side) operating regions

Full size image

The static signal-tracking characteristics of the power converter is shown in Fig. 10. Measurement shows the output voltage V OUT and the tracking error respect to the reference voltage V REF , indicating a good linearity in all the range, with errors below 180 mV. Additional measurements show that near 100 mV of tracking error is caused by offsets in the voltage comparator U 2, leaving then a nonlinearity close to the output ripple.

Fig. 10
figure 10

Measurement of the static signal-tracking capabilities of the power converter. The plot shows the output voltage V OUT and the tracking error (V OUT  − V REF ) measured against the reference voltage V REF . R L was set to \(500\,\Upomega\) and V IN to 3.3 V

Full size image

The dynamic response of the converter in a signal-tracking application is depicted in Fig. 11. V REF input voltage reference was set to a 50 kHz triangle wave spanning between 0  and 3 V and V IN to 3.3 V. Note the asymmetry in the output voltage with respect to the triangle rising and falling edges. This is due to the contribution of the load resistor R L of \(500\,\Upomega\) in the discharging of the capacitor C L , which also explains the better tracking of the reference in the falling edge. In the falling edge, the energy not dissipated by the resistor is returned back to the source in a sequence of CtoL and DisL AFSM states, thus providing the output capacitor with the capability of discharging. This is useful in signal tracking applications with highly capacitive loads (with negative reactance at high frequency) or as a power supply for adiabatic digital circuits. Increased bandwidths can be easily obtained by decreasing the values of the inductor L and/or the capacitor C L . In Fig. 12, for example, the value of the inductor was decreased to L = 1.5 μH and the output capacitor to C L  = 12 nF, allowing the converter to track a 2.5 Vpp amplitude, 1 MHz square-wave signal.

Fig. 11
figure 11

Measurement of the dynamic signal-tracking capabilities of the power converter. V REF was a 50 kHz triangle wave spanning between 0  and 3 V. Note that the output voltage tracks more effectively the falling side of the triangle due to the contribution of the output resistor R L in the discharging of the output capacitor C L

Full size image
Fig. 12
figure 12

Measurement of the dynamic signal-tracking capabilities of the power converter. L was reduced to 1.5 μH and C L to 12 nF. V REF was a 1 MHz square wave spanning between 0 and 2.5 V

Full size image

A measurement of the power converter transient response to a load change is shown in Fig. 13. In t = 0, load resistor R L suddenly changes from \(500\) to \(100\,\Upomega,\) but note that no significant transient can be seen in the figure. This happens because the load change has only the effect of faster lowering the output voltage to the level where the comparator U 2 triggers, so a cycle of ChgL and LtoC states begin immediately to compensate for the voltage drop.

Fig. 13
figure 13

Measurement of the power converter transient response to a load change. In t = 0, load resistor R L changes from \(500\,\Upomega\) to \(100\,\Upomega. V_{IN}\) was set to 3.3 V and V REF to 3 V

Full size image

Table 2 summarizes the performance metrics of the proposed power converter and compares them with six state-of-the-art power converter architectures presented in the literature. Despite the simplicity of its architecture, this proposal can achieve high efficiency and good input and output voltage dynamic range, indicating its suitability in battery-powered SoC applications where a wide range of input and output voltages are required.

Table 2 Performance summary and comparison
Full size table

5 Conclusion

In this paper, we have shown the working principle and experimental results of an noninverting buck-boost power converter co-integrated with its AFSM digital zonal controller. The power converter can dynamically track a reference voltage and also efficiently drive a capacitive load. The digital approach upon which it is based and the minimal number of analog blocks required (only two comparators), allows the use of automatic place and route digital tools, significantly reducing its design cycle and the migration costs to different manufacturing technologies.

For the presented 0.35 µm CMOS design, measured efficiency of the power converter is 80 % with a switching frequency of 2.86 MHz. Additional techniques at the power stage, such as dead-time optimization, could be added to this proof-of-concept prototype to enhance efficiency performance.

Moreover, this controller has the capability of returning unused energy to the energy source, which notable increases the efficiency when driving highly capacitive loads at high-frequency. Measurements also indicate good voltage regulation under different loads and also a good signal-tracking behavior useful in applications where high-frequency driving of capacitive loads is required, in implementation of power management policies based on AVS or in the design of power modulators targeting Envelope Tracking RF transmitters.