Mismatch reduction technique for transistors with minimum channel length

Abstract

An analog calibration technique is presented to improve the parameter matching between transistors in the differential high-frequency signal path of analog CMOS circuits. It can be applied for mismatch reduction in differential broadband amplifiers and direct down-conversion mixers in which short-channel devices are utilized to minimize bandwidth reduction from parasitic capacitances. In general, the proposed methodology is suitable for radio frequency (RF) applications in which direct matching of the transistors is undesired because sophisticated layout practices would increase the coupling between the high-frequency paths. The approach involves auxiliary devices which sense the existing mismatch as part of a feedback loop for error minimization. This technique is demonstrated with a differential amplifier that has a loaded gain and −3 dB frequency of 12.9 dB and 2.14 GHz, respectively. It was designed in 90 nm CMOS technology with a 1.2 V supply. Monte Carlo simulations indicate that the 4.06 mV standard deviation of the amplifier’s anticipated input-referred offset voltage improves to 0.76–1.28 mV with the mismatch reduction loop, which is contingent on the layout configuration of the calibration circuitry. The associated drain current mismatch reduction for the transistor pair under calibration in the amplifier core is from 3.1% to 0.6–1.0%.

1 Introduction

Device mismatches become more severe as technology scaling continues, especially when minimum transistor lengths are used to optimize for high-frequency operation, or to bias with high overdrive voltage for yield enhancement [9]. In addition to higher percent errors with small fabrication dimensions, the threshold voltage mismatch worsens even for neighboring transistors due to the increasing effect of dopant fluctuations in modern CMOS processes [1]. The resulting offsets degrade the performance of analog circuits that rely on device matching. Moreover, rising variability from technology scaling has been identified as one of the main CMOS fabrication challenges due to its influence on the functionality, yield, and profitability of products [4]. Therefore, besides designing to meet specifications, it becomes increasingly important to decrease the statistical variations of circuit performance parameters in order to improve production yields and to reduce the manufacturing test cost by employing new statistical design approaches such as those described in [7]. A design technique towards this goal is presented in this letter. The method involves an analog calibration loop in which device mismatches are indirectly detected and reduced based on layout-based parameter correlations rather than directly measuring characteristics of the circuit as in typical RF built-in test and calibration schemes [6, 8, 12, 15, 17].

Device mismatches create second-order non-linearities in the RF front-end of receivers, which have to be minimized for direct down-conversion mixers and differential broadband low-noise amplifiers. For example, the second-order intercept point (IIP2) of mixers strongly depends on matching of transistors, for which a digital mismatch reduction scheme was proposed in [14] to separately adjust the gate bias voltage of each transistor. In [10], another digital approach was presented for differential transistor pairs within high-speed amplifiers and comparators, where 32 pairs with minimum channel length and a network of switches are included on the chip so that the best matching pair can be selected with the use of on-chip comparison circuitry. In this letter, an alternative analog mismatch reduction scheme is proposed that continuously operates in the background without requiring digital resources or switches in the signal path. Its short convergence time below 1 μs prevents excessive start-up calibration time for time-critical situations such as during production testing.

2 Mismatch reduction method

An issue in RF applications is that designers may choose to place transistors next to each other with a safe distance as shown in Fig. 1 instead of elaborately matching them in the layout. The advantage with such a configuration is that the physical separation of the devices provides isolation against RF signal leakage that leads to crosstalk between the differential signal paths. Often, each RF transistor is surrounded by a guard ring for enhanced isolation and by deep trenches (if available). A drawback in this scenario is that the unmatched devices have significant parameter mismatches which are observable through static drain current difference. Even though the use of non-minimum dimensions can reduce process variations, devices with large area in the signal path are often not feasible since they entail increased power consumption and/or performance degradation due to excessively large parasitic capacitances. Similarly, layout matching techniques such as interleaved or common-centroid styles create more high-frequency coupling through parasitic capacitances of crossing metal lines in addition to increasing the substrate leakage due to proximity of the devices.

Fig. 1

An unmatched RF transistor pair

To alleviate the aforementioned issues, the alternative approach visualized in Fig. 2 is proposed here. Instead of matching the RF transistors M₁ and M₂ to each other, they are individually matched to mismatch-sensing transistors M_1S and M_2S in a DC calibration loop. Thus, the currents I_1S and I_2S of the mismatch-sensing transistors are correlated to I₁ and I₂ of the main transistor pair, respectively. Even though it is optimal to use the same dimensions and number of fingers for M_1S and M_2S as for M₁ and M₂, they do not have to be identical. However, their electrical device parameters must be correlated to M₁ and M₂ through layout matching techniques. The feedback action in the loop compares I_1S to I_2S and adjusts the separate gate bias voltages V_B1 and V_B2 of the mismatch-sensing transistors until the currents are approximately equal. Consequently, the drain current difference in the main transistor pair is also reduced due to the parameter correlations between the matched transistors and the shared gate bias voltages. With this approach, the mismatches are mitigated while the RF isolation between the main transistors is maintained. Additionally, low-pass filter nodes within the calibration loop suppress any RF signal that might couple into it through layout parasitics.

Fig. 2

An RF transistor pair with DC mismatch reduction loop

To demonstrate the abovementioned concept, Fig. 3 depicts a differential amplifier consisting of a transistor pair, M₁ and M₂, with polysilicon resistor loads, R_L, where the resistor dimensions were selected large enough to ensure that the input-referred offset voltage is dominated by the transistor pair. The characteristics of M₁ and M₂ are ideally equal, but considerable deviations occur when they are not matched in the layout through interleaved, common-centroid, or similar configurations. Hence, crosstalk between the differential signal paths is avoided by separating them, while parameter variations of M₁ and M₂ should be treated as uncorrelated. However, M₁ and M₂ can be laid out with N (20 in this example) subdevices and matched to sensing-transistors M_1S and M_2S, respectively. In this configuration, M_1S and M_2S are part of the DC calibration loop that detects a mismatch between currents I₁ and I₂, and generates bias voltages V_B1 and V_B2 individually for each branch. In the absence of mismatches, the gate-source voltage overdrives and drain currents of M_1S and M_2S must be equal [1], which only occurs when V_C1 = V_C2 in Fig. 3. Here, M_1S and M_2S are placed in a differential amplifier configuration with a tail-current source (I_B/10) and active loads (M₃, M₄) for high gain with self-regulation via feedback resistors (R_cm). The capacitor (C_st) stabilizes the regulation loop by creating a dominant pole. If I₁ ≠ I₂ in the presence of variations, then the resulting imbalance of V_C1–V_C2 due to the correlated mismatches between I_1S and I_2S is amplified by the amplifier (A). The feedback action differentially adjusts V_B1 and V_B2 until I_1S ≈ I_2S to minimize mismatches without requiring on-chip digital resources. Capacitors (C_filt) are included to filter out high-frequency noise. The fully differential amplifier (A), whose schematic is shown in Fig. 4, controls the bias voltages V_B1 and V_B2 around a set common-mode output level (V_B = 0.85 V). Its transistor dimensions in the nominal corner case were selected according to this required DC level, which is regulated by the feedback resistors (R_fb).

Fig. 3

Differential amplifier with mismatch reduction loop

Fig. 4

Comparison amplifier (A) in the calibration loop

This scheme exploits the fact that the parameters of M₁/M_1S and M₂/M_2S are highly correlated so that the mismatch can be continuously extracted in the background to compensate for drifts from temperature changes as well as process variations. Since the calibration loop has low-pass filtering nodes, the differential signal integrity is not jeopardized by coupling between M₁ and M₂ through the loop. Instead, coupling to M_1S and M_2S via layout parasitics due to the matching arrangements only creates a small signal loss. The large bias resistors (R_B) prevent the input capacitances looking into the gates of M_1S and M_2S from causing any significant loading effects at the RF inputs (In+, In−).

The accuracy of the proposed method relies on the matching between M₁/M_1S and M₂/M_2S, which depends on their number of subdevices [5, 18]. Let σ_ΔVth be the standard deviation of the threshold voltage difference for an unmatched transistor pair. In a matched pair with N fingers and the same dimensions, this standard deviation of random threshold voltage variation decreases to

$$ \sigma_{{\Updelta {\text{Vth}}({\text{m}})}} = \sigma_{{\Updelta {\text{Vth}}}} /\sqrt {\text{N}} $$

(1)

for a stripe pair structure [18]. More complex common-centroid configurations are expected to improve the spread reduction [2, 11], but the aforementioned relationship will be used as a plausible worst-case estimate. Being outside of the signal path, the parasitic capacitances of the matched transistors in the core of the calibration loop do not affect the RF performance. Hence, their dimensions can be increased to ensure that their offsets are negligible. Therefore, non-minimum transistor lengths (L) and widths (W) were selected for matched pairs M₃/M₄, M_B, M_N, M_P, I_B (NMOS current mirror with L = 0.5 μm), and I_B/10, as annotated in Figs. 3 and 4. The large layout dimensions reduce variations according to the following proportionality from [13]:

$$ \sigma_{{\Updelta {\text{Vth}}}} \propto \tfrac{1}{{\sqrt {\text{WL}} }}. $$

(2)

Likewise, the dimensions of the polysilicon resistors R_cm and R_fb were chosen sufficiently large with the help of statistical device models and Monte Carlo simulations.

3 Simulation results

The test circuit of Figs. 3 and 4 was designed using UMC 90 nm CMOS technology (1.2 V supply), and simulations were performed with the foundry’s statistical device models. The loaded differential amplifier under calibration has a gain of 12.9 dB with a −3 dB bandwidth of 2.14 GHz. Its minimum AC input impedance magnitude within the passband is 1.77 KΩ, which changes less than 3% when the loop is added and activated. The amplifier’s input-referred noise density at 1 GHz is 1.8 ${\text{nV/}}\sqrt {\text{Hz}} ,$ which increases negligibly after inclusion of the mismatch reduction circuitry. Table 1 summarizes the simulation results for the amplifier’s main performance parameters without calibration circuitry as well as with the activated calibration loop. Since the mismatch reduction circuitry is outside of the signal path, it does not have a strong impact on specifications except of the increased power consumption (+15%) and layout area requirement (×5.3). However, as a result of the bias point adaptations through the calibration loop, it can be observed that the linearity parameters are slightly degraded in the fast corner while they are slightly better in the slow corner. The comparison amplifier (A) has a loaded DC gain of 18.3 dB, resulting in an overall gain of 38.6 dB in the loop starting at V_B1/V_B2 and traversing through V_C1/V_C2.

Table 1 Simulated amplifier performance at 2 GHz

Device matching was taken into account during the Monte Carlo analysis with the Cadence Spectre simulator (process and mismatch variations enabled). Based on (1), the expected spread reduction depends on the number of fingers in each matched pair. From this reduction, the corresponding correlation coefficient (C_m) was specified by the relation given in [3]:

$$ 1/\sqrt {\text{N}} = \sqrt { 1- {\text{C}}_{\text{m}} } \,. $$

(3)

For example, the N = 20 fingers (C_m = 0.95) of the matched pairs M₁/M_1S and M₂/M_2S implies an expected spread reduction by a factor of 4.47 with the proposed scheme when other offsets in the loop are negligible. Figure 5 displays the histograms of the input-referred offset voltage of the amplifier obtained with 100 Monte Carlo runs at 30°C, showing that its standard deviation decreases from 4.06 to down 1.28 mV when the calibration loop is added. In this circuit, an input offset voltage decrease from 4.06 to 1.28 mV corresponds to a drain current difference reduction from 3.1 to 1.0% for M₁ and M₂. At −40 and 100°C, 100 Monte Carlo runs revealed that the predicted offset decreases from 4.10 to 1.22 mV and from 4.25 to 1.40 mV, respectively. With the large-sized devices in the calibration circuit, the accuracy improvement heavily depends on the correlation of the parameters between M₁/M_1S and M₂/M_2S. For instance, using C_m = 0.99 in the simulation instead of the previous worst-case assumption, the input offset with calibration reduces to 0.76 mV (0.6% M₁/M₂ drain current difference), provided that 20 subdevices can be appropriately matched with a common-centroid layout.

Fig. 5

Monte Carlo simulation results (100 runs at 30°C) for the input-referred offset voltage of the differential amplifier: a before activating the calibration loop (ideal bias voltages: V_B1 = V_B2 = V_B), and b afterwards

The transient behavior in the mismatch reduction loop was assessed by purposely introducing offset voltages at the gates of the transistors M₂ and M_2S to emulate threshold voltage mismatches. Figure 6 shows the settling behavior of the two gate bias control voltages V_B1 and V_B2. In the test setup for this simulation, a 30 mV DC offset voltage source was injected at the gates of M₂ and M_2S after 250 ns. The equal offset conditions imply ideal parameter correlations between M₁/M_1S and M₂/M_2S instead of C_m = 0.95 as in the Monte Carlo simulations, but this difference is not significant when evaluating the settling time of the loop instead of the residual mismatch after settling. The short settling times below 1 μs of the control voltages in this background calibration scheme are viable for quick calibrations at system start-up as well as for in built-in test routines during manufacturing testing.

Fig. 6

Transient response of the control voltages, where a 30 mV threshold voltage offset between M₁/M_1S and M₂/M_2S is introduced at 250 ns

Instead of selecting 20 fingers for M_1S and M_2S in Fig. 3, the mismatch-sensing transistors M_1S and M_2S could be formed by two fingers. Since the tail current of the mismatch-sensing transistor pair is one tenth of the tail current in the main amplifier, this choice results in the same 25 μA current per finger in the main and the mismatch-sensing transistors. With regards to parameter matching, the equal current density in all identically sized fingers is optimal. Another advantage of this modification is that the mismatch-sensing transistors only occupy one tenth of the area compared to the main transistors. After 100 Monte Carlo simulation runs at 30°C using two fingers for M_1S and M_2S, the standard deviation of the amplifier’s input offset voltage improved from 4.06 mV to 2.83 mV with C_m = 0.95, and to 1.43 mV with C_m = 0.99. In contrast, when M_1S and M_2S consisted of 20 fingers each, the input offset was reduced from 4.06 mV to 1.28 mV with C_m = 0.95. The loss of calibration effectiveness with two mismatch-sensing fingers is explained by the fact that the Monte Carlo simulations are based on the worst-case assumption, which is the randomness of parameter variations among subdevices. In reality, parameter gradients are typically observed across the die because variations tend to be systematic, especially for devices that are not separated by excessive distances. Therefore, device matching characteristics can be modeled with linear and non-linear parameter gradients across the wafer [11], leading to partial cancellations of variation effects when common-centroid layout structures are employed [2, 5, 11]. When a parameter variation can be approximated with a linear gradient, then the center of a common-centroid structure corresponds to the mean value [11]. Thus, significant improvement of the mismatch reduction can be expected if the fingers of the sensing transistors are located directly around the center point. However, this improvement will depend on how well the devices at the center represent the mean parameter values of the other devices in the common-centroid. Even though the correlation coefficient for this case is unity in theory, the actual correlation between the parameters of the device(s) at the center with the mean of all others should be limited due to modeling inaccuracies. To the best knowledge of the authors, experimental data for such a scenario has not yet been published in the literature, which is why the worst-case estimates were presented in this section.

Previously reported alternative mismatch and offset reduction techniques have targeted circuits with diverse device dimensions, process technology variations, and optimizations for different applications. Therefore, the available data and incentive for quantitative comparisons are sparse. Nevertheless, a qualitative comparison of the proposed approach with some other alternative mismatch reduction methods is presented in Table 2 to highlight the main trade-offs.

Table 2 Overview of alternative mismatch reduction approaches

4 Conclusion

A methodology has been proposed to reduce the mismatch between a pair of transistors by indirectly matching them through a DC calibration loop as an alternative to matching the transistors within the RF signal path or increasing their dimensions. Monte Carlo simulation results demonstrate that the input offset standard deviation of the differential amplifier under investigation is expected to reduce from 4.06 to 1.28 mV or 0.76 mV, which depends on the layout-based quality of the matching between the RF and mismatch-sensing transistors. The main trade-offs with the scheme are an approximately 15% power increase and an estimated five times larger layout area.