1 Introduction

The rapid growth of portable applications, the devices reliability and the increased density of integrated circuits require the design of low-voltage and low-power CMOS circuits [1, 2]. In modern CMOS processes, the device sizes and the maximum allowable supply voltages are scaled down but this is not applied in threshold voltages V TH by the same amount [3–6]. The values of threshold voltage and supply voltage are mainly driven by the digital VLSI requirements, such as speed, leakage currents and noise margin. Unfortunately, the relatively large value of the threshold voltage, with respect to low supply voltage, is the main limitation in the design of low-voltage analog CMOS circuits.

One of the most widespread analog building blocks with very large number of applications is the operational amplifier. The traditional gate-driven CMOS operational amplifiers are insufficient for operation under low supply voltages due to limited common-mode input range. Several low supply voltage techniques that expand the common-mode range of the gate-driven amplifiers have been proposed. The most common technique is based on parallel connected PMOS and NMOS differential pairs, but it requires complex control circuits presenting also a dead-zone region in the middle of the input range [7–12]. Another technique is based on the use of dynamic level shifters and offers relatively large input common-mode range [13, 14]. An alternative technique employs quasi-floating gates MOS devices allowing rail-to-rail operation in deep-submicron CMOS processes, preventing also the gate leakage current [15–17].

In the last years, a very promising design technique for low supply voltage applications uses bulk-driven MOS devices. Based in this technique the input signal is applied to the bulk terminal of the input devices featuring rail-to-rail input common-mode range [3, 4, 6, 18–29]. The main limitation of the amplifiers, which are based on the bulk-driven technique, is that the input transconductance is equal to the small bulk transconductance which is 3–5 times smaller than the gate-transconductance. Also, due to the aforementioned limitation, a relatively large input-referred noise is occurred compared with the input-referred noise of gate-driven MOS devices [3, 4].

A new bulk-driven fully differential operational amplifier topology that operates under 0.8 V supply voltage is proposed in this paper. The input stage of the circuit employs a positive feedback loop in order to enlarge the inherent small bulk-transconductance. The usage of the positive feedback for voltage gain boosting of an amplifier has already been reported in the literature [3, 27–29]. In the aforementioned works, the input devices are simple bulk-driven transistors and consequently the input transconductance is still equal to the bulk transconductance. Also, the positive feedback loop, which is separated by the input bulk-driven devices, enhances only the voltage gain of the amplifier and not the actual input transconductance. The contribution of the proposed topology is that the input bulk-driven devices are simultaneously parts of the positive feedback loop boosting in this way the true input transconductance. Thus, the amplifier features relatively large effective input transconductance for rail-to-rail input common-mode range with improved noise performance.

The paper is organised as follows: in Sect. 2, the operation of the proposed amplifier is presented. Also, the amplifier’s auxiliary circuits and an explicit performance analysis are also given. Detailed simulation results that verify the proper operation of the proposed amplifier are provided in Sect. 3.

2 Bulk-driven fully differential operational amplifier

2.1 Circuit operation

The topology of the proposed low-voltage bulk-driven fully differential operational amplifier is presented in this Section. Its schematic is illustrated in Fig. 1(a), while the block diagrams of the common-mode amplifier and the biasing circuit are presented in Fig. 1(b, c), respectively. The bulk-driven differential pair M 1A-B with the conjunction of the common-gate transistors M 2A-B constructs the input stage of the amplifier. The first voltage gain stage is realized by the folded cascode transistors M 3A-B and M 6A-B . The second voltage gain stage is constructed by the common-source transistors M 7A-B and M 8A-B . The RC networks are used for the frequency compensation of the differential amplifier.

Fig. 1
figure 1

The circuit of the proposed amplifier (a), the block diagram of the common-mode amplifier (b) and the biasing circuit (c)

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Transistors M 5A-B , and M 4,4A-B form the current mirrors that bias the input stage. The constant voltages V BP1, V BN1, V BP2 and V BN2 are produced by the biasing circuit, shown in Fig. 1(c). It should be noted here that the voltages VBP2 and VBN1 have the appropriate values in order to force the drain-to-source voltage of transistors M 5A-B and M 4A-B to be about 150 mV, operating at the edge of the strong inversion [3]. The control voltage V CMFB that fed the gate terminals of M 6A-B is produced by the output of the auxiliary common-mode amplifier (Fig. 1(b)).

The differential input signal, v id = v p  − v n , is applied between the bulk terminals of M 1A and M 1B , where v p and v n are defined as the positive and negative input, respectively. The input transistors M 1A and M 1B have their gate terminals cross-connected with their drain terminals. The input stage produces the differential ac currents i p and i n which are fed the next gain stages. The source voltage of transistors M 2A and M 2B is fed back to the gate of M 1B and M 1A , respectively, modifying in this way their drain currents and also boosting the transconductance to a higher value. Intuitively, the small drain current of M 1A , M 1B , due to inherent small bulk-transconductance, simultaneously modulates the gates of M 1B , M 1A , respectively, and boosts the input transconductance without any extra circuitry. Thus, input bulk-driven transistors M 1A-B are involved into the positive feedback loop, as well.

Based on small signal equivalent circuit of the amplifier’s input stage and neglecting the channel conductance of M 1A-B and M 2A-B , the effective transconductance will be given by

$$ g_{{m , {\text{eff}}}} = g_{mb1} {\frac{{g_{mb2} + g_{m2} }}{{g_{mb2} + g_{m2} - g_{m1} }}} $$
(1)

where g mb1, g m1 are the bulk and gate-transconductance of M 1A-B , respectively, and g mb2, g m2 are the bulk and gate-transconductance of M 2A–B , respectively. According to Eq. 1, the transconductance improvement can be achieved by setting relatively small value of the difference g m2 + g mb2 − g m1 (assuming that g m2 + g mb2 ≫ g mb2). Thus, a large input transconductance can be realized if the difference value is close to zero. It is worth to notice at this point here that the maximum achievable transconductance depends on the worst case variation of g m2 + g mb2 (due to device mismatches, process and temperature) with regards to g m1.

2.2 Biasing circuit

The biasing circuit that is used to generate the appropriate bias currents and voltages of the amplifier is presented in Fig. 2. A constant current I B flows through each branch of the biasing circuit. The diode connected transistor M B1 produces the fixed voltage V BP1 while transistors M B4, M B5 and M B6 produce the fixed voltages V BN1, V BP2 and V BN2, respectively. Taking into account the value of current I B , the polysilicon resistors R 1 and R 2 must have such a value in order to produce a voltage drop across them equal to 150 mV.

Fig. 2
figure 2

Biasing circuit

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2.3 Common-mode amplifier

A common-mode feedback loop is necessary for differential circuits since it stabilizes the output common-mode voltage to a predetermine value. In order to achieve the maximum output swing, the output common-mode voltage should be equal to the mid supply. The circuit of the common-mode amplifier is presented in Fig. 3. Its input stage constructed by the simple bulk-driven differential pair M 10A -M 10B . The common-mode amplifier compares the output common-mode voltage, which is sensed by resistors R f , with the fixed voltage V CM. Due to negative feedback loop, the voltage V CMFB modifies the gates of M 5A-B , see Fig. 1, forcing the output common-mode voltage to be equal to the fixed voltage V CM. The choice of the value of R f is very important since it affects the differential gain due to the fact that it is connected as resistive load at the outputs of the amplifier.

Fig. 3
figure 3

Common-mode amplifier

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The common-mode amplifier ideally needs a voltage gain close to unity. Thus, the frequency compensation for the common-mode feedback loop can be achieved using the same R-C networks that are used for the frequency compensation of the differential amplifier. In our design the voltage gain of the common-mode amplifier is less than unity due to the usage of the simple bulk-driven differential pair M 10A -M 10B . Thus, a symmetrical structure of the common-mode amplifier is needed in order to minimise the systematic offset of the common-mode feedback loop. Also, using the folded cascode transistors M 12A -M 13A , M 12B -M 13B , and M 14, the input devices M 10A -M 1B are isolated from the output node V CMFB. Therefore, the input devices M 10A -M 1B can be easily remain in saturation, independently of the output node voltage V CMFB, featuring the higher possible transconductance.

2.4 Minimum supply voltage

Based on the circuit topology the minimum supply voltage for normal operation is given by,

$$ V_{{{\text{DD}},\min }} = V_{{{\text{DS}},M4}} + V_{{{\text{GS}},M1,A - B}} (V_{\text{TH}} ) + V_{{{\text{DS}},M5,A - B}} $$
(2)

where V GS,M1(V TH) is the gate-source voltage of M 1A-B which is a function of the threshold voltage and V DS,M4, V DS,M5,A-B are the drain to source voltages of transistors M 4 and M 5A-B , respectively. According to Eq. 2, the minimum supply voltage depends on the threshold voltage due to the factor \( V_{{{\text{GS}},M1}} (V_{\text{TH}} ) \). Thus, process with low value of V TH leads to circuits with low value of \( V_{{{\text{DD}},\min }} \).

The threshold voltage of a PMOS transistor is given by \( V_{\text{TH}} = \left| {V_{{{\text{TH}}0}} } \right| + \gamma \left( {\sqrt {\left| {V_{\text{BS}} + 2\phi_{F} } \right|} - \sqrt {2\phi_{F} } } \right) \), where V TH0 is the threshold voltage for V SB = 0, Φ F is the body Fermi potential, γ is the body effect coefficient and VBS is the bulk-to-source voltage. Based on Eq. 3a, for value of V BS lower than zero the threshold voltage decreases, lowering the minimum supply voltage as well.

2.5 Noise analysis

The major noise contributors of a MOS device are the flicker and thermal noise which are independent of the input terminal where the noise is referred. Based on the well-known noise expressions of the gate-driven transistor [4], the input-referred noise \( \overline{{V_{n}^{2} }} \) at the bulk terminal will be given by

$$ \overline{{V_{n}^{2} }} \approx \overline{{V_{n,(1/f)}^{2} }} + \overline{{V_{{n,{\text{th}}}}^{2} }} $$
(3a)

where \( V_{n,(1/f)}^{{}} \) is the input-referred flicker noise

$$ \overline{{V_{n,(1/f)}^{2} }} \approx {\frac{1}{{g_{mb}^{2} }}}{\frac{{K_{f} g_{m}^{2} }}{{{\text{WLC}}_{\rm ox} f}}} $$
(3b)

and \( V_{{n,{\text{th}}}} \) is the input-referred channel thermal noise

$$ \overline{{V_{{n,{\text{th}}}}^{2} }} \approx {\frac{1}{{g_{mb}^{2} }}}4{\text{kT}}{\frac{2}{3}}g_{m} $$
(3c)

where K f is the flicker noise parameter. All the other symbols have their usual meanings. The impact of both types of noise contributors to the input-referred noise are larger in a bulk-driven transistor compared to the gate-driven counterpart since the bulk-transconductance is smaller than the gate-transconductance [3, 4, 6].

The noise analysis for the proposed amplifier leads to the next expressions for the flicker and channel thermal input-referred noise:

$$ \overline{{V_{n,(1/f)}^{2} }} \approx {\frac{1}{{g_{{m,{\text{eff}}}}^{2} }}}\left\{ {\left[ {1 + \left( {{\frac{{g_{m1} }}{{g_{m2} }}}} \right)^{2} } \right]\left( {{\frac{{g_{m1}^{2} }}{{W_{1} L_{1} }}} + {\frac{{g_{m2}^{2} }}{{W_{2} L_{2} }}}} \right) + {\frac{{g_{m5}^{2} }}{{W_{5} L_{5} }}}} \right\}{\frac{{K_{f} }}{{C_{\rm ox} }}}{\frac{1}{f}} $$
(4a)
$$ \overline{{V_{{n,({\text{th}})}}^{2} }} \approx {\frac{1}{{g_{{m,{\text{eff}}}}^{2} }}}\left\{ {\left[ {1 + \left( {{\frac{{g_{m1} }}{{g_{m2} }}}} \right)^{2} } \right]\left( {g_{m1} + g_{m2} } \right) + g_{m5} } \right\}{\frac{8}{3}}{\text{kT}} . $$
(4b)

It is obvious from above equations that the noise performance is mainly dominated by transistors that included to the positive feedback such as M 2A-B , the input transistors M 1A-B and the current source M 5A-B . Also, both types flicker and thermal noise include, the factor \( 1 + \left( {{{g_{m1} } \mathord{\left/ {\vphantom {{g_{m1} } {g_{m2} }}} \right. \kern-\nulldelimiterspace} {g_{m2} }}} \right)^{2} \), which is appeared due to the positive feedback utilized into the input stage.

3 Results and discussion

The proposed amplifier was designed and optimized to operate for a supply voltage V DD equal to 0.8 V using a standard n-well 0.18 μm CMOS process. The threshold voltages of NMOS and PMOS devices were 0.48 and −0.55 V, respectively. Table 1 presents the transistor’s aspect ratios for the proposed amplifier, common-mode amplifier and biasing circuit.

Table 1 Transistors aspect ratios (in μm/μm)
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In order to maximize the output swing of the amplifier the input and output common-mode voltage was set equal to 0.4 V which is at the mid supply. The bias current I B was equal to 10 μA that produces a current consumption of about 100 μA for the amplifier’s core and 30 μA for the common-mode amplifier. The specification for the effective input transconductance is to meet the transconductance of the conventional gate-driven differential pair. For the used process, the bulk-transconductance of a PMOS device is about 4 times smaller than its gate-transconductance. The aspect ratios of the bulk-driven input transistors M 1A,B and M 2A,B were chosen to be 40/0.18 and 20/0.18 μm/μm, respectively. The bulk and gate-transconductance of M 1A-B were g mb1 = 60 μA/V and g m1 = 218 μA/V, respectively, and the bulk and gate-transconductance for M 2A-B were g mb2 = 52 μA/V and g m2 = 205 μA/V, respectively. The value of resistors R f of the common-mode amplifier was chosen to be 20 kΩ, in order to avoid extra loading of the output of the amplifier.

In Fig. 4, the effective input transconductance of the bulk-driven input stage of the proposed amplifier and the transconductance of the simple bulk-driven differential pair are presented. The aforementioned transconductances are illustrated as a function of the input common-mode voltage V CM,in with the supply voltage V DD as parameter taking the values 0.7, 0.8 and 1 V. The effective transconductance is equal to 240 μA/V for V DD = 0.8 V and it is decreased while V DD is scaled down. This occurred due to the fact that the channel conductance of the MOS devices becomes larger and comparable to bulk-transconductance of the MOS devices for such a low values of supply voltage.

Fig. 4
figure 4

Effective transconductances of the input stage of the proposed amplifier and of the simple bulk driven differential pair as a function of V CM,in with V DD as parameter

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The input-referred noise as function of frequency for the proposed bulk-driven amplifier is illustrated in Fig. 5, with the supply voltage V DD as parameter. Obviously, the noise becomes higher for low value of supply voltage since the effective transconductance is also decreased.

Fig. 5
figure 5

Input-referred noise as a function of frequency with V DD as parameter

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In Fig. 6 the gain and phase frequency response of the proposed amplifier is presented with V DD as parameter. It is clear that using the R-C frequency compensation network the system becomes a two poles system. On the other hand the positive feedback that imposed into amplifier had not effect on the frequency performance. The A DC gain decreased for low supplies since the device channel conductance and the available bias current from the biasing circuit are limited at such low drain-source and gate-source voltages.

Fig. 6
figure 6

Frequency response of gain (a) and phase (b) of the proposed bulk-driven amplifier with V DD as parameter

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Table 2 presents the performance summary of the proposed bulk-driven differential amplifier, where the values of several critical factors such as CMRR, IIP3 etc. are included.

Table 2 Performance summary of the proposed amplifier
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According to the Table 2, for supply voltages higher than the 0.8 V the current consumption takes a little higher value while the gain-bandwidth is almost constant and close to 6 MHz. As the supply voltage increases from 0.7 to 1 V the current consumption increased from 126 to 133 μA. The above results demonstrate that the amplifier is robust and maintains performances over a large power supply range.

Table 3 presents the worst case performances for the amplifier regarding process and temperature. The worst case variation of the open loop gain is about ±3 dB. The worst case phase margin is 52° that is large enough concluding that the circuit is stable.

Table 3 Process and temperature worst case performances
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Table 4 summarizes comparison results about the performance of the already published bulk-driven fully differential amplifier [3, 27, 29]. It should be noted here that the major number of the published bulk-driven amplifier is relevant to single-ended amplifier implementations. Also, the comparison between amplifiers is actually a difficult task since each circuit employed different process, output load, phase margin and different transistor aspect ratio that were relevant to the desired performance specification and/or applications.

Table 4 Comparison between fully differential bulk-driven amplifiers at sub-0.8 V operation
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Lets start the comparison of the proposed amplifier with the amplifier of ref. [3]. According to the Table 4, the implementation of [3] is a pseudo-differential amplifier since the tail current source transistor was omitted. Thus, the supply voltage is lower and equal to 0.5 V than the supply voltage of the proposed amplifier that is equal to 0.8 V despite they used the same process. As a consequence, the disadvantage of the pseudo-differential implementation of ref. [3] is the worst CMRR performance which is 78 dB at 5 kHz than 100 dB at the same frequency of our amplifier. The open loop gain and the unity gain bandwidth are lower than our design for the same load and phase margin and for the same power dissipation. Regarding the input noise performance is difficult to get a conclusion since different sized input transistors and the bias condition were used.

The implementations of [27, 29] used 0.35 and 0.18 μm triple-well processes, respectively, which are not actually standard CMOS process and less cost effective. They used parallel connected bulk-driven PMOS and NMOS differential pair in order to compensate the bulk-transconductance regarding the input common-mode level. The power consumptions were 190 and 100 μW for [27, 29], respectively. The differential gain is higher in both circuits than in our design since bulk-driven auxiliary amplifier was used to measure the output common voltage [27]. In our design, poly-silicon resistors R f were used since they can measure the output common-mode voltage even in case of large output signals. Large output signals affect the linear operation of the differential pair of the common-mode amplifier. Also, the open loop gain of 56 dB that proposed amplifier actually features is satisfactory high for many kinds of applications.

4 Conclusion

In this paper, a bulk-driven CMOS operational amplifier with 0.8 V supply voltage is proposed. The amplifier features improved input transconductance using a positive feedback, presenting also satisfactory noise performance. The amplifier was designed using standard 0.18 μm n-well CMOS process. The effective transconductance of the amplifier’s input stage was 240 μA/V for V DD = 0.8 V which is equivalent with the gate transconductance and the input referred voltage noise was 154 nV/√Hz at 100 kHz. The amplifier presents A DC = 56 dB and about 6 MHz unity gain bandwidth for 60° phase margin.