1 Introduction

Converters for urban air mobility or electric vehicle are required to be compact and light. Variable methods to attain high-power density and high-efficiency converters have been studied [1,2,3,4,5]. Miniaturization of magnetic components, such as a transformer and an inductor, is essential for high-density converters as they are typically bulky and heavy.

High-frequency (HF) operation decreases the size of magnetic components, leading to high-power density. Contemporary semiconductors with wide-bandgap (WBG) material enable HF operation to elevate switching frequency. However, conventional wire-wound magnetic components are limited in operating at high frequencies. Typical ferrite cores used in mass production are currently available up to 2 MHz [6]. Skin and proximity effects in copper wires increase winding loss at frequencies above 100 kHz [7]. Thin copper layers on a printed circuit board (PCB) in planar magnetic components replace conventional round copper wires. The utilization of flat conductors in planar magnetic components has been proven to reduce the skin and proximity losses in the windings, even though the converter operates at high frequency [8,9,10,11].

The benefits of planar magnetic components have prompted research on their design methodologies. Planar magnetic components inherently offer low profiles compared to wire-wound counterparts, allowing a reduction in the size of power converters. Planar magnetic components have high-power density, excellent mass productivity, and good thermal characteristics [12, 13]. Planar magnetic components also permit flexible winding configurations. Various PCB winding technologies have been covered in Refs. [8, 10], and [14,15,16,17,18] to optimize the magnetic components. An interleaved winding structure is applied to avoid voltage spikes at semiconductors by minimizing the leakage inductance [22]. The interleaved structure is often employed in planar transformers (PTs) to decrease winding losses and enhance efficiency [19]. However, it concurrently elevates inter-winding capacitance, posing challenges in HF operation. There is a trade-off between the winding loss and the inter-winding capacitance.

Despite the aforementioned advantages, one of the drawbacks of PTs is the parasitic capacitances. Overlapped copper traces in PCB cause the parasitic capacitances of a PT. The resonance with the parasitic capacitances and inductances at high frequencies leads to HF oscillations, inducing electromagnetic interference (EMI) issues. Bulky EMI filters hinder the high-power density converter. A low-impedance path along the parasitic capacitances results in voltage/current spikes at switch devices. Therefore, reducing the parasitic capacitances is critical to prevent converter performance from degrading.

Modeling the parasitic capacitances of the transformer was described in Refs. [20, 21]. Studies for multi-layer planar transformer (MLPT) were examined in Refs. [22, 23] based on Refs. [20, 21]. Simple methods to mitigate the parasitic capacitances are suggested to mitigate the parasitic capacitances in this paper. The parasitic capacitances of an MLPT are modeled and calculated. This paper also compares the values using finite-element analysis (FEA). Impedance analysis is implemented to establish the resonant frequency of the MLPT for the purpose of operating at a frequency below the resonant frequency. In Sect. 2, the process of constructing the equivalent circuit of MLPT is explained. Section 3 discusses two simple approaches of increasing the resonant frequency of the MLPT and verifies their effect by impedance analysis. Experimental results are shown in Sect. 4. The measured impedances of prototype PTs are compared with calculated and simulated impedances. Two improved PTs are compared to the measurement and calculation values, respectively. The conclusion is provided in Sect. 5.

2 Estimation of the parasitic capacitances

Parasitic capacitances arise from the overlap between the two consecutive copper layers of the PT, as demonstrated in Fig. 1. The HF components of the current or voltage that causes EMI issues flow along the low-impedance path provided by the parasitic capacitances. Parasitic capacitances also resonate with the inductance of the PT, causing oscillations in the current and voltage. Accurate estimation of the parasitic capacitances in the PT is essential to ensure optimal performance at high frequencies.

Fig. 1
figure 1

Cross-section of multi-layer PT

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This paper is based on Refs. [20,21,22,23]: Fundamental capacitance modeling for transformer is explained in Refs. [20, 21]; the analyses of the PT are presented in Refs. [21, 22]; modeling of MLPT is described in Refs. [22, 23]. Section 2.1 reviews parallel-plate capacitance model to precisely calculate the parasitic capacitance of the PT depending on the winding methods. Section 2.2 discusses the estimation of the capacitance for two adjacent layers from different windings. The equivalent circuit of the MLPT is derived in Sect. 2.3. Capacitances computed by modeling the MLPT and simulating by the FEA are also included in this section.

2.1 Capacitance model of the same winding in two adjacent copper layer

Various static capacitance models, including the parallel-plate and cylindrical models [23], have been studied. The parallel-plate model is adopted to represent the parasitic capacitances of the PT as illustrated in Fig. 2. The parallel-plate capacitance, denoted as C0, is computed using (1):

$$C_{{0}} = \varepsilon_{{0}} \varepsilon_{{\text{r}}} \frac{w \cdot l}{d} = \varepsilon_{{0}} \varepsilon_{{\text{r}}} \frac{A}{d}.$$
(1)
Fig. 2
figure 2

Parallel-plate capacitance model

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The parameters d, w, l, and A in Fig. 2 and (1) refer to the distance between two adjacent copper layers, the width, the length, and the area of the copper layer. Vacuum permittivity is defined by ε0, and relative permittivity is εr. The voltage distribution between the layers establishes the equivalent inter-layer capacitance, labeled as Cil, along with the electrical energy stored in capacitance C0. Charge distribution varies with voltage distribution, causing changes in Cil with the applied winding methods. A straight-connected winding method between two layers, as drawn in Fig. 3, is only examined in this paper. When Cil between the layers of windings in a PT, it is assumed that the layers are equipotential and the skin effect is negligible. The energy stored between two layers, WE,layer, is found in (2):

$$W_{{\text{E,layer}}} = \frac{2}{3}C_{0} \left( {\frac{{V_{{{\text{winding}}}} }}{{{\text{Number}}\,{\text{of}}\,{\text{layers}}}}} \right) = \frac{1}{2}C_{{{\text{il}}}} V_{{{\text{winding}}}}^{2} .$$
(2)
Fig. 3
figure 3

A straight-connected winding method

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The voltage of one winding is represented by Vwinding. The expression for the relationship between C0 and Cil is finally provided by (3):

$$C_{{{\text{il}}}} = \frac{{C_{0} }}{3}.$$
(3)

2.2 Capacitance model of the different winding in two adjacent copper layer

The equivalent capacitance constructing the different windings is represented by a two-layer transformer capacitance model. Intra-winding capacitance (capacitance in single winding) and inter-winding capacitance (capacitance between two different windings) are determined with the six-capacitance equivalent circuit as depicted in Fig. 4a. The intra-winding capacitances C1 and C6 and the inter-winding capacitances C2, C3, C4, and C5 are decided by considering the electrical energy WE in (4). The voltage across Ck is Uk (k = 1, 2, 3, 4, 5, or 6) as expressed by (5). A six-capacitance network in Fig. 4b is then constructed using the values calculated by (4) and (5). The voltages aV1 and bV1 are measured at nodes A and B to the end of the primary-side windings, respectively. The voltages on the secondary side, cV2 and dV2, are also found in the same way as the primary side. The voltage values are defined as the ratios of the input and output voltages, V1 and V2. For example, a, b, c, and d have the values of 3/4, 1/2, 1, and 1/2, respectively, in the network shown in Fig. 4b:

$$W_{{\text{E}}} = \frac{1}{2}\sum\limits_{{\text{k = 1}}}^{{6}} {C_{{\text{k}}} U_{{\text{k}}}^{2} } ,$$
(4)
$$\begin{gathered} U_{1} = (a - b)V_{1} \hfill \\ U_{2} = (c - d)V_{2} \hfill \\ U_{3} = - bV_{1} + dV_{2} + V_{3} \hfill \\ U_{4} = - aV_{1} + cV_{2} + V_{3} \hfill \\ U_{5} = - bV_{1} + cV_{2} + V_{3} \hfill \\ U_{6} = - aV_{1} + dV_{2} + V_{3} . \hfill \\ \end{gathered}$$
(5)
Fig. 4
figure 4

A Equivalent six-capacitance circuit; b six-capacitance network of MLPT

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By employing (4) and (5) to derive (6), C1 through C6 are acquired. The comprehensive calculation procedure is elaborated in Refs. [20, 23]:

$$\begin{gathered} C_{1} = - \frac{{C_{0} }}{6}(2a^{2} + 2b^{2} + 2ab - 3a - 3b) \hfill \\ C_{2} = - \frac{{C_{0} }}{6}(2c^{2} + 2d^{2} + 2cd - 3c - 3d) \hfill \\ C_{3} = \frac{{C_{0} }}{6}(6 - 3a - 3b - 3c - 3d + 2ac + 2bd + ad + bc) \hfill \\ C_{4} = \frac{{C_{0} }}{6}(2ac + 2bd + ad + bc) \hfill \\ C_{5} = \frac{{C_{0} }}{6}(3c + 3d - 2ac - 2bd - ad - bc) \hfill \\ C_{6} = \frac{{C_{0} }}{6}(3a + 3b - 2ac - 2bd - ad - bc). \hfill \\ \end{gathered}$$
(6)

2.3 Estimation of the parasitic capacitance model of multi-layer planar transformer

The parallel-plate capacitance in the multi-layer, C0,ij in (7), is important in calculating the equivalent capacitances of the n-layer MLPT [23]:

$$C_{{\text{0,ij}}} = \varepsilon_{{0}} \varepsilon_{{{\text{r\_ij,eff}}}} \frac{{A_{{\text{ij,eff}}} }}{{d_{{{\text{ij}}}} }}.$$
(7)

The variable i in (7) represents the layer number, i.e., i = 1, 2, 3, …, n – 1, and j is defined as j = i + 1. The distance between the two successive layers is expressed as dij, while the effective area between these layers is denoted as Aij,eff. The effective permittivity between the ith and jth layers, εr_ij,eff, is calculated using (8):

$$\varepsilon_{{{\text{r\_ij,eff}}}} = \frac{{\varepsilon_{{\text{r,1}}} \cdot z_{1} + \varepsilon_{{\text{r,2}}} \cdot z_{2} + \cdots + \varepsilon_{{\text{r,m}}} \cdot z_{{\text{m}}} }}{{z_{1} + z_{2} + \cdots + z_{{\text{m}}} }}.$$
(8)

In the context of a multi-layer PCB, the dielectric layers between two contiguous copper layers exhibit a permittivity designated as εr,m and their thickness as zm:

This paper investigates a six 2-oz layers PT in Fig. 5a with a 12:2 turns ratio, using Maxwell 3D on Ansys Electronics Desktop 2021 R2.2. The orange windings at the top and bottom layers are the secondary-side windings, while the blue windings in the middle layers indicate the primary-side ones. An exploded view in Fig. 5b facilitates a detailed examination of the winding configuration. The equivalent inter-layer capacitance Cil,ij at the same winding was obtained through Sect. 2.1. Figure 5c represents a cross-sectional view of the MLPT with the values determined by (8). Parameters in Fig. 5c are identified using the PCB stack-up information in Table 1. The equivalent Cil,pri is obtained according to (9). In (9), Cil,23, Cil,34, and Cil,45 are the inter-layer capacitances on the primary side:

$$C_{{\text{il,pri}}} = \frac{1}{{\frac{1}{{C_{{{\text{il,}}23}} }} + \frac{1}{{C_{{{\text{il,}}34}} }} + \frac{1}{{C_{{{\text{il,}}45}} }}}}.$$
(9)
Fig. 5
figure 5

A 3D view of the designed MLPT; b an exploded view of a; c a detailed winding configuration of a

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Table 1 PCB stack-up information
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The inter-layer capacitance on the secondary side is neglected because the distance between the top and bottom layers is large enough.

The equivalent circuit for the PT in Fig. 5 is demonstrated in Fig. 6. Each layer is denoted as Li, where i is 1, 2, 3, 4, 5, or 6. The parasitic capacitances between L2 and L5 are combined into a single capacitance Cil,pri. Inter-layer capacitance Cil,pri is connected to C1 in parallel. Layers L1 and L6 connect the six-capacitance network to L2 and L5. Layers L3 and L4 are excluded from the network as they do not construct different windings. Two six-capacitance networks are connected in parallel as described in Ref. [23]. The absolute capacitances of C1 to C6 are calculated as (10) using Figs. 4b and 6:

$$\begin{gathered} C_{1} = \frac{5}{48}C_{0,12} + \frac{5}{48}C_{0,56} \hfill \\ C_{2} = \frac{1}{6}C_{0,12} + \frac{1}{6}C_{0,56} \hfill \\ C_{3} = \frac{1}{12}C_{0,12} + \frac{5}{24}C_{0,56} \hfill \\ C_{4} = \frac{5}{24}C_{0,12} + \frac{1}{12}C_{0,56} \hfill \\ C_{5} = \frac{1}{24}C_{0,12} + \frac{2}{3}C_{0,56} \hfill \\ C_{6} = \frac{2}{3}C_{0,12} + \frac{1}{24}C_{0,56} . \hfill \\ \end{gathered}$$
(10)
Fig. 6
figure 6

Equivalent circuit of Fig. 5

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Assuming that the area between conductors on each layer is negligible, Aij,eff is equal for every layer. The calculated C1 to C6, employing C0,12 = C0,56 = 178.14 pF, are in the second column of Table 2. Simulated parallel-plate capacitances are provided in the third column using C0,12 = 214.9 pF and C0,56 = 189.66 pF from Ansys Maxwell 3D. Slight deviations in Aij,eff for each layer in Fig. 5b appear as discrepancies between the calculated and simulated capacitances. Section 4 compares the impedances of the two equivalent circuits derived from Table 2.

Table 2 Calculated and Simulated Parasitic Capacitances
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3 Decreasing the parasitic capacitances

Proper operation of the converter requires maintaining an adequate separation between the resonant frequency and the switching frequency. Two methods are proposed to achieve the difference. Section 3.1 discusses how thicker PCB is utilized to reduce the parasitic capacitances. The resonant frequency is increased by minimizing the overlapped area between PCB traces. Winding reconfiguration to achieve a higher resonant frequency is provided in Sect. 3.2.

3.1 Increasing the distance between the layers

A simple way to increase the resonant frequency is to reduce the parallel-plate capacitance in (1) and (3) by increasing the thickness of the dielectric layers on the PCB. Winding reconfiguration or transformer redesign is unnecessary. For example, the distance z3 between L1 and L2 of the PCB described in Fig. 7 is larger than z1 + z2 between L1 and L2 in Fig. 5c. Section 4 discusses the comparison result with the original PT to verify the resonant frequency shift to a higher frequency.

Fig. 7
figure 7

A cross-sectional view of the thicker PCB

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3.2 Improvement of the winding configuration

Parasitic capacitances amplify when copper traces in PCB are overlapped. Minimizing the overlapped area suppresses the parasitic capacitances. However, the limited width of the window area of the planar core necessitates the use of eight 2-oz PCB for the improved winding configuration as depicted in Fig. 8. The magnitude of the equivalent six-capacitance of the PT in Fig. 8 is derived as (11) following Sect. 2.3. Each capacitance is obtained by expanding Fig. 4b to 8 layers and applying the values to (6). Capacitances in (11) are used to analyze the total impedance to prove that the reconfiguration of the windings decreases the capacitances:

$$\begin{gathered} C_{1} = \frac{2}{27}C_{0,12} + \frac{2}{27}C_{0,78} \hfill \\ C_{2} = \frac{1}{6}C_{0,12} + \frac{1}{6}C_{0,78} \hfill \\ C_{3} = \frac{1}{18}C_{0,12} + \frac{2}{9}C_{0,78} \hfill \\ C_{4} = \frac{2}{9}C_{0,12} + \frac{1}{18}C_{0,78} \hfill \\ C_{5} = \frac{1}{36}C_{0,12} + \frac{25}{{36}}C_{0,78} \hfill \\ C_{6} = \frac{25}{{36}}C_{0,12} + \frac{1}{36}C_{0,78} . \hfill \\ \end{gathered}$$
(11)
Fig. 8
figure 8

A detailed reconfiguration of the windings

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4 Experimental results

The parasitic capacitances estimated in Sect. 2 and inductances are resonate. Impedance peaks near the resonant frequency generate undesirable oscillation that damages the switch devices or causes EMI issues. The resonance was validated with a prototype hardwareshown in Fig. 9 which realized the transformer shown in Fig. 5. The planar cores utilized in the analyses are E43/10/28 and PLT43/28/4.1, manufactured by 3F4 material from Ferroxcube.

Fig. 9
figure 9

Prototype hardware of the MLPT in Fig. 5

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The impedance curve was obtained by evaluating the primary side with the secondary side open. The curve is comparable to a typical LC resonant circuit. The magnetizing inductance dominates at low frequency, while the parasitic capacitances dominate at high frequency. The effect of the leakage inductance on the resonance is negligible. Impedance curves with calculated and simulated values in Table 2 are plotted using LTspice XVII. An LCR meter, IM3570 from HIOKI, was utilized for measuring the impedance of the prototype transformer.

4.1 Impedance analysis

Figure 10 displays the calculated, simulated, and measured impedance curves for the PT in Fig. 5. The green graph was drawn with the calculated capacitances in Table 2. Simulated values were used to plot blue lines, and the measured capacitances were in red. The measured resonant frequency was approximately 1.27 MHz, which is close to the calculated and simulated values of 1.11 MHz and 1.01 MHz, respectively. Inductances resonate with the parasitic capacitances at high frequencies, which causes impedance peaking.

Fig. 10
figure 10

Overall impedance curves of Fig. 5

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4.2 Planar transformer with thicker PCB

A modified PCB stack-up was proposed to prove that larger dij results in higher resonant frequency as mentioned in Sect. 3.1. The specification of the suggested PCB is tabulated in Table 3. It is about 0.4 mm thicker than the original PCB in Table 1. Figure 11 illustrates two measured curves for the PTs manufactured using the original and thicker PCBs. The red graph from the original PCB has a resonant frequency of 1.27 MHz, while the yellow from the thicker PCB has 1.63 MHz. Increasing the thickness of the dielectric layers is validated to attain a higher resonant frequency of about 0.4 MHz in the experiment. It should be noted that, however, increasing the thickness of the dielectric may decrease the cost effectiveness of the PCB and increase the winding loss if the windings are placed closer to the air gap of the cores due to the fringing magnetic flux.

Table 3 Modified PCB Stack-Up Information
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Fig. 11
figure 11

Comparison with the measured impedance curves of the original and modified PT

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4.3 Planar transformer with reconfiguration of windings

The winding configuration is revised for the reduction of the overlapped area according to Sect. 3.2. Table 4 shows the parasitic capacitances of the revised PT. Inter-layer capacitance, Cil,pri, and six-capacitance are derived from (11). Table 1 is also applied to calculate the effective permittivity, and εr_67,eff and εr_78,eff for the additional layers have the same value with εr_23,eff and εr_12,eff; accordingly, inter-layer capacitance on the secondary side is insignificant since the distance between the layers is sufficiently large, as indicated in Fig. 8. The parallel-plate capacitances C0,12 = 131.48 pF and C0,78 = 87.2 pF are computed through (11). The green curve in Fig. 12 was illustrated with the calculated capacitances from Table 2, and the values in Table 4 were represented with purple color. The reconfiguration of the windings yields a resonant frequency of 0.3 MHz than the original transformer.

Table 4 Calculated Parasitic Capacitances with Two PTs
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Fig. 12
figure 12

Comparison with the calculated values of the original and revised PT

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5 Conclusion

This paper introduced a detailed explanation of how to calculate the parasitic capacitances of the PT. Parasitic capacitances damage switch devices and generate EMI issues due to the low-impedance path in HF operation. Current oscillation, induced by the resonance with inductance, has a detrimental effect on the converter. Impedance analysis facilitates the verification of the parasitic capacitance effect. A prototype PT with a 12:2 turns ratio and six 2-oz layers is precisely modeled, simulated, and measured. Two methods are suggested for increasing the resonant frequency. Increasing the thickness of the dielectric layers was confirmed as a practical solution to achieve higher resonant frequency. Revising the winding configuration also showed its effectiveness in HF operation by improving the resonant frequency.