1 Introduction

In recent years, multilevel inverters (MLIs) have become attractive converters in numerous applications such as renewable energy systems, motor drives, distributed generation systems, UPS systems, and flexible alternating current transmission system (FACTS) [1,2,3]. When compared with the traditional two-level inverters, MLIs have many advantages such as lower total harmonic distortion, reduced dv/dt stresses, lower switching frequency, etc. [4]. In general, classic MLIs include neutral-point-clamped (NPC), flying capacitor (FC), and cascaded H-bridge (CHB) inverters. However, NPC and FC inverters employ a large number of clamping diodes and capacitors along with the increase of output levels, which inevitably raises the cost of topologies and the complexity of control strategies [5, 6]. Cascaded H-bridge MLIs have problems in terms of the lack of boost capacity and the need for multiple isolated dc sources [7, 8].

To alleviate the problems of traditional MLIs, switched-capacitor multilevel inverters (SCMLIs) have been proposed in [9,10,11,12,13,14]. SCMLIs can achieve multilevel output with a single dc source and fewer power devices. The five-level inverter proposed in [9] uses only eight switches, but the topology contains two extra diodes and the working states for most of the switch pairs are inconsistent. In [10], a seven-level inverter with a single dc voltage source and 12 switches was proposed. Although the topology in [11] employs ten switches to output seven levels, there are still four extra diodes and ten gate drivers are required. The same issue can be found in [13], where the nine-level inverter can achieve twice voltage gain using many diodes and drivers. In addition, two capacitors are discharged for most of a cycle, which may bring about a large voltage ripple and the imbalance of capacitor voltage.

Meanwhile, the extensible capability is important for SCMLIs to improve their output voltage. In many low-input dc voltage applications such as photovoltaic power generation and other renewable energy power generation systems, the output voltage needs to be promoted. Although the output voltage can be increased by adding a transformer to the AC side of the inverter [15, 16], this seriously increases the volume and weight of the inverter. Therefore, DC–AC SCMLIs with extensible capability to increase output voltage are also a focus of research.

In addition, the SCMLIs developed in [17,18,19,20] can realize the expansion of the topology, and increase both the output voltage gain and the number of output levels. The inverter in [21] can achieve the purpose of raising the voltage gain through the sequential charging of the dc source and the capacitors. By utilizing two capacitors, the four times voltage gain and the more output levels can be achieved. However, the losses of the capacitor are high.

The above-mentioned extensible topologies require the addition of H-bridge to achieve the changes of the positive and negative polarities of the output level. However, for the inverter with associated with H-bridge, the voltage stress on the switches grows with the increase of output voltage gain. Therefore, high-performance (expensive) switching devices are required, which increases the cost of extended structures. Voltage stress is a bottleneck limiting the application range. To address this problem, SCMLIs without H-bridge were proposed in [22,23,24,25]. In [23], the proposed multilevel inverter achieved a high-voltage gain. However, the voltage stress of the switching devices in the expanded topology cannot be kept constant. However, the SCMLI without H-bridge in [25] can keep the voltage stress of the switching devices constant. However, it cannot be ignored that the inverter has a problem in terms of its high total standing voltage (TSV).

Based on the above analysis, this paper presents a novel expansible switched-capacitor multilevel inverter, which can output five levels and achieve twice voltage gain with a single dc source. When compared with existing topologies, the proposed SCMLI has the following salient features.

  • The proposed topology removes backend H-bridge due to the inherent polarity reversal capability, and the polarity of the output level can be changed with proper control of switches.

  • Only two switches have voltage stress of 2Vdc, which significantly reduce the total voltage stress and maximum blocking voltage of switches.

  • Although the inverter uses ten switches, only five gate drivers are required. This is due to the fact that many pairs of switches have the same working state. Thus, the cost and complexity of control are both reduced.

  • The voltage of two capacitors can be self-balanced without any auxiliary circuits.

  • The inverter has the ability of expansion. With the increase of output levels, the maximum blocking voltage for all of the switches is kept within 2Vdc.

The remainder of this paper is organized as follows. Section 2 introduces the structure and operation principle of the proposed SCMLI. Section 3 gives the modulation method of the topology, analyzes self-balance of the capacitor voltage, and presents the capacitor selection method. Section 4 verifies the characteristics of the proposed inverter by comparing the proposed inverter with the existing topologies in terms of the power losses and the number of used circuit elements. Section 5 presents the simulation and experimental results of the proposed inverter. Finally, Sect. 6 gives some concluding remarks.

2 Proposed topology

2.1 Topology of proposed inverter

The topology of the proposed MLIs is shown in Fig. 1, which consists of a dc source and a switched-capacitor structure. The switched-capacitor structure is composed of the capacitors C1 and C2, and the switching devices S1–S10. Among them, S4 and S8 are IGBTs without anti-parallel diodes, and the other switching devices are IGBTs with anti-parallel diodes. By controlling the on and off of the switching device to control the charging and discharging state of the capacitor, the inverter can output five levels: 2Vdc, Vdc, 0, − Vdc, and − 2Vdc.

Fig. 1
figure 1

Topology of the five-level inverter

Full size image

2.2 Operating principle of the five-level inverter

To obtain a five-level voltage output, the different switch combinations of the proposed MLIs are listed in Table 1, where “C”, “D”, and “–” indicate the charging, discharging, and idle status in the capacitance, respectively. In Table 1, the five working stages are divided into one control period, and the corresponding working mode in each stage is shown in Fig. 2.

Table 1 Operation states of inverter components
Full size table
Fig. 2
figure 2

Working modes of the proposed inverter: a + 2 level; b + 1 level; c 0 level; d -1 level; e -2 level

Full size image

For ease of analysis, the following assumption are made:

  • All of the power devices are ideal, without on-resistance and forward voltage drop.

  • The voltage between capacitances remains at the rated voltage, and there is no obvious voltage fluctuation.

With the above assumptions, the working principle of the MLIs is summarized in Fig. 2.

 + 2 Level: As shown in Fig. 2a, the switches S2, S5, and S10 in the inverter are in the on-state, and the remaining switching devices are in the off-state. The capacitors C1 and C2 are discharged in series. Thus, the inverter output voltage is 2Vdc. In this situation, the inverter is in the + 2Vdc working mode.

 + 1 Level: As depicted in Fig. 2b, the switches S2, S3, S4, S6, S8, and S10 in the inverter are in the on-state, and the remaining switches are in the off-state. At this time, the dc source charges the capacitors C1 and C2, and the inverter output voltage is Vdc. Thus, the inverter is working in the + Vdc mode.

0 Level: As can be seen in Fig. 2c, the switches S1, S5, and S9 in the inverter are in the on-state, and the remaining switches are in the off-state. The capacitors C1 and C2 are in the hold state. Thus, the inverter output voltage is 0, which is working in the zero output level mode.

-1 Level: In Fig. 2d, the switches S1, S3, S4, S6, S8, and S9 in the inverter are in the on-state, and the remaining switches are in the off-state. The dc source charges the capacitors C1 and C2, and the inverter output voltage is -Vdc.

-2 Level: As shown in Fig. 2e, the switches S1, S7, and S9 in the inverter are in the on-state, and the remaining switches are in the off-state. The capacitors C1 and C2 are discharged in series. Thus, the inverter output voltage is -2Vdc.

It is worth pointing out that the proposed inverter can provide a closed current loop in any of the above operating modes. Therefore, the proposed inverter can be connected to inductive loads.

2.3 Expansion of the proposed inverter

From the above detailed analysis, the proposed five-level inverter topology is able to output five voltage levels with twice voltage gain. In addition, to further increase the both the number of output levels and the output voltage gain, as well as to broaden the scope of practical application, the proposed inverter is expanded in Fig. 3. The expanded topology only increases the switched-capacitor structure, which consists of a capacitor and five switches. The addition of every two switched-capacitor structures increases four output levels and enhances the voltage gain by twice. When the output voltage is nVdc, the number of output levels is 2n + 1. More importantly, the maximum voltage stress sustained by the switches does not increase with the expansion of the structure, which is still 2Vdc.

Fig. 3
figure 3

Proposed space-type switched-capacitor inverter

Full size image

3 Modulation and capacitance design

3.1 Modulation strategy

For the modulation of multilevel inverters, many pulse width modulation (PWM) strategies have been used, such as space vector pulse width modulation (SV-PWM), selective harmonic elimination pulse width modulation (SHE-PWM), sinusoidal pulse width modulation (SPWM), etc. [26]. The SV-PWM scheme is suitable for a small number of output levels, since the complexity of the modulation will increase with growth in the number of output levels. The SHE-PWM strategy can abate the switching frequency and improve the utilization of dc voltage. However, its implementation is not trivial. The most commonly used modulation technique is SPWM. This is because that it is easy to implement and the quality of output waveform is superb. The phase disposition pulse width modulation (PD-PWM) method, which is a kind of SPWM, is utilized to modulate the proposed inverter, and the schematic of the modulation is shown in Fig. 4.

Fig. 4
figure 4

Modulation schematic

Full size image

As shown in Fig. 4, the four triangular carriers u1 ~ u4 are compared with a sinusoidal reference wave to give rise to the basic pulse signals a1 ~ a4, and these carriers have the same amplitude (Ac) and frequency (fc). The amplitude and frequency of the sinusoidal reference wave are Aref and fref, respectively. The modulation index M is set to 0.9. It can be seen that the proposed inverter outputs five levels. The logical combination of switches can be seen in Fig. 5. It is worth noting that there are two complementary switch pairs (S1 and S10 and S2 and S9), and that the switches S3, S4, S6, and S8 have the same operation states in one cycle. Thus, only five gate divers are required.

Fig. 5
figure 5

Logic modulation of the proposed inverter

Full size image

3.2 Capacitance voltage self-balancing analysis

The operation status of the capacitors C1 and C2 is summarized in Table 2. From Table 2, it can be noted that the dc source charges or discharges the capacitors C1 and C2 at the levels of ± 1. Thus, by setting the charging and discharging states of the capacitors, C1 and C2 are in the same modulation wave period.

Table 2 Operation status of two capacitors
Full size table

According to the modulation of the proposed inverter in Fig. 4, it can be known that dc source only charges the capacitors C1 and C2 at the level of Vdc. Table 2 shows the charging and discharging working states of the two capacitors. It can be seen that the charging and discharging states of the capacitors C1 and C2 are the same in one modulation wave period. Thus, the capacitor voltage can be balanced.

3.3 Capacitance calculation

The capacitance is the key factor to determine the levels and the gain of the output voltage. In addition, the effect of the capacitor voltage ripple on the output voltage can be reduced effectively when the proper value for the capacitance is selected. Therefore, this part is devoted to analyzing the calculation of the capacitance.

The t1 and t2 in Fig. 4 can be calculated by

$$t_{1} = \frac{{\sin^{ - 1} (1/2)}}{{2{\uppi }f_{ref} }}$$
(1)
$$t_{2} = \frac{{\pi - \sin^{ - 1} (1/2)}}{{2\pi f_{{{\text{ref}}}} }},$$
(2)

fref is the frequency of the reference waveform.

The capacitor voltage ripple is related to the maximum continuous discharge of the capacitor. According to the analysis of the working principle in Sect. 2 and the working modes of each level in Fig. 2, it can be known that the longest discharge time of the capacitors C1 and C2 is [t1, t2]. Therefore, the maximum discharge of the capacitor can be calculated as

$$Q_{{C_{i} }} = \int_{{t_{1} }}^{{t_{2} }} {I\sin (} 2\pi f_{ref} t)dt.$$
(3)

In addition, the capacitor voltage ripple is set to k times the rated voltage of the capacitor, and k generally does not exceed 0.1. Thus, the value of the capacitor C1 should satisfy the following constraint:

$$C_{i} \ge \frac{{Q_{{C_{i} }} }}{{kV_{{C_{i} }} }} = \frac{{Q_{{C_{i} }} }}{{\Delta V_{{{\text{rip}}}} }},$$
(4)

Vci indicates the rated voltage of the capacitor, and ΔVrip represents the capacitor voltage ripple. Therefore, a proper capacitor needs to be selected to achieve the normal operation of the inverter.

4 Comparison analysis and losses calculation

4.1 Comparison analysis

In this section, to verify the effectiveness and superior performance of the proposed SCMLI, the non-extensible SCMLI in [10, 13], the extensible SCMLI in [17,18,19], and the SCMLIs without H-bridge in [22, 23] are also tested to make comparisons. The results of this comparison are summarized in Fig. 6 and Table 3, which includes the output voltage gain, number of levels, number of capacitors, diodes, and switches, etc.

Fig. 6
figure 6

Comparison of various SCMLIs: a levels; b MBV; c TSV

Full size image
Table 3 Parameter comparison of various inverters
Full size table

When the output voltages of these topologies are nVdc (the non-expandable inverters are calculated based on the maximum output voltage), comparison results of various parameters are shown in Table 3. This part makes a detailed analysis from the aspects of levels, maximum blocking voltage (MBV), and total standing voltage (TSV) to illustrate the advantages of the proposed inverter. MBV is the maximum voltage stress of the switching device.

Figure 6a presents a comparison of the output level number of the proposed inverter topology and several existing topologies with changes in the voltage gain. It can be seen from the figure that the proposed inverter and the expandable SCMLI have basically the same level number changes, while the non-extensible SCMLIs stop changing only to the number of their highest output level. With the increase of the number of output levels, the quality of the output voltage is greatly improved, and its output voltage waveform gets closer to a sine wave.

Figure 6b presents a comparison of the MBVs. The MBV in [12] and [15] is 3Vdc, while the output voltage gain does not increase. The MBVs in [19,20,21] and [24] increase with the number of capacitors. The topology in [25] keeps 4Vdc constant. Thus, not all of the non-H-bridges’ SCMLIs can keep the MBV unchanged. However, the MBV in the proposed inverter is only 2Vdc. When compared with the above inverters, the proposed inverter reduces the inverter requirements in terms of the performance of switching devices.

In Table 3, the available switches indicate whether the switch has to make the inverter work normally when the topology of the inverter expands. It can be seen that with the increase of output level, the MBV of the proposed inverter remains at a low value of 2Vdc. When it is expanded to a certain degree, there are no switches meeting the operating conditions of the inverter. However, the MBV in the proposed topology remains unchanged in an expanded structure. Thus, no matter how the topology of the proposed inverter expands, the switch devices are able to satisfy the conditions.

Figure 6c presents a comparison of the TSV. The non-extensible topology stops changing after its maximum output voltage, and the extensible topology changes with the increase of the output voltage. When compared with most of the existing inverter topologies, the TSV of the proposed inverter is greatly reduced. Thus, during the operation of the inverter, the switching losses can be effectively reduced, and the service life of the switching devices can be increased.

From the above comparative study, the salient features of the proposed SCMLI are summarized as follows.

  1. (1)

    The H-bridge is not utilized in the proposed SCMLI.

  2. (2)

    The MBV of switches remains unchanged with the increases of output levels in the expanded structure.

  3. (3)

    The number of the utilized capacitance, switch, and diode are all reduced.

  4. (4)

    The TSV of the proposed inverter is greatly reduced.

4.2 Calculation of losses

The proposed inverter losses are mainly composed of three aspects: the ripple losses in the capacitance, the conduction losses, and the switching losses in the power switch. This part analyzes and calculates these three losses.

  1. A.

    Ripple losses

When the capacitor is charging, there is a voltage ripple. The related energy loss in this voltage ripple can be calculated by

$$E_{rip} { = }\frac{1}{2}C_{i} \Delta V_{rip} ,$$
(5)

Erip is the energy losses during the capacitor charging process.

By combining (4) and (5), the value of Erip can be obtained by

$$E_{rip} { = }\frac{{Q_{{C_{i} }}^{2} }}{{2C_{i} }}.$$
(6)

After acquiring Erip, the ripple losses of the proposed inverter can be denoted as

$$\begin{gathered} P_{{{\text{rip}}}} { = }f_{o} \sum\limits_{1}^{2} {2E_{{{\text{rip}}}} } \hfill \\ \quad = 2f_{o} \left( {\frac{{Q_{{C_{1} }}^{2} }}{{2C_{1} }} + \frac{{Q_{{C_{2} }}^{2} }}{{2C_{2} }}} \right), \hfill \\ \end{gathered}$$
(7)

fo indicate the output voltage frequency.

  1. B.

    Conduction losses

The conduction losses are related to the total parasitic resistance of the conductive elements contained in the load current path. Due to the symmetry of the operating principle, the conduction losses of the topology can be analyzed in ½ of a cycle. The parasitic parameters in the load current path include the on-resistance rs of the switches, and the internal resistance rc of the capacitors. The equivalent circuit of the output load current path at + 2 level and + 1 level is shown in Fig. 7. It can be seen from Fig. 7a that the total equivalent parasitic resistance at the + 2 level can be expressed as

$$r_{eq(2)} { = }2r_{C} + 3r_{S} .$$
(8)
Fig. 7
figure 7

Equivalent circuit of the load current path considering the parasitic parameters: a at + 2 level; b at + 1 level

Full size image

The duration of the + 2 level is (t2 − t1). Thus, the conduction losses of the + 2 level at ½ of a cycle can be calculated as

$$E_{con(2)} { = }I_{R(2)}^{2} \cdot r_{eq(2)} \cdot (t_{2} - t_{1} ),$$
(9)

IR(2) is the output current, which can be calculated by

$$I_{R(2)} { = }\frac{{2V_{{{\text{dc}}}} }}{{R_{{{\text{Load}}}} }},$$
(10)

RLoad denotes the load resistance.

Therefore, the conduction losses of the + 1 level can be obtained by

$$\begin{gathered} E_{con(1)} { = }I_{R(1)}^{2} \cdot r_{eq(1)} \cdot \left( {\frac{T}{2} - t_{2} + t_{1} } \right) \hfill \\ \quad \quad = \left( {\frac{{V_{{{\text{dc}}}} }}{{R_{{{\text{Load}}}} }}} \right)^{2} \cdot 6r_{S} \cdot \left( {\frac{T}{2} - t_{2} + t_{1} } \right), \hfill \\ \end{gathered}$$
(11)

T is the working time of the inverter for one cycle.

Thus, the total conduction losses of the proposed inverter can be calculated by

$$P_{con} { = }E_{con(1)} + E_{con(2)} .$$
(12)
  1. C.

    Switching losses

The switching losses are usually caused by the inherent switching delay of the semiconductor device, which can be approximated by the parasitic shunt capacitor Cs of the switch. The energy losses of the switch Sj are

$$E_{{S_{j} }} { = }\frac{1}{2}C_{S} V_{b(j)}^{2} ,$$
(13)

j = 1,2,3…10, Vb(j) is the blocking voltage generated by the switch at the moment of on and off.

From the working principle and Table 1, the on–off conditions of the proposed inverter can be acquired. Thus, the total switching losses can be calculated by

$$P_{S} { = }f_{{\text{o}}} \sum\limits_{j}^{10} {N_{S(j)} } E_{{S_{j} }} ,$$
(14)

NS(j) is the total number of times that the switch Sj is turned on and off in one cycle.

In summary, the efficiency of the five-level inverter can be calculated as

$$\eta = \frac{{P_{{\text{o}}} }}{{P_{{\text{o}}} + P_{{{\text{rip}}}} + P_{{{\text{con}}}} + P_{S} }},$$
(15)

η and Po are the efficiency and output power of the proposed topology, respectively.

From the above analysis, the losses of the inverter can be obtained. It is worth noting that rs, rc, Cs, C1,2, and fo are set to 0.15 Ω, 0.06 Ω, 500 pF, 2200 μF, and 50 Hz, respectively. When the dc source is set to 30 V and the load is 50 Ω-15 mH, the three kinds of loss can be calculated as: Prip = 0.48 W, Pcon = 0.53 W, and PS = 0.18 W. A power losses’ distribution is shown in Figs. 8, and 9 shows the theoretical efficiency and experimental efficiency of the proposed inverter under different output powers. It can be seen that the overall efficiency is around 94.5%, while the overall efficiencies of the topologies proposed in [24] and [25] are 91.5% and 90%, respectively. Hence, it can be seen that the proposed inverter has better performance.

Fig. 8
figure 8

Power losses’ distribution

Full size image
Fig. 9
figure 9

Efficiency curves of the proposed topology

Full size image

5 Simulation and experiment analysis

5.1 Simulation results

To examine the performance of the proposed topology and modulation scheme, a simulation model of five-level inverter is developed in MATLAB/Simulink. The simulation parameters are shown in Table 4.

Table 4 Simulation parameters
Full size table

The simulation results are shown in Figs. 10, 11, 12. The output voltage and current of proposed inverter are shown in Fig. 10. It can be seen that voltage of the two capacitors can maintain stability with a small ripple. Figure 11 shows the voltage stress for each of the switches. It can be seen that only the voltages of S5 and S7 are 2Vdc. The current stress for each of the switches is shown in Fig. 12.

Fig. 10
figure 10

Simulation results of output voltage, load current, and capacitors’ voltage

Full size image
Fig. 11
figure 11

Voltage stress for each of the switches: a voltage across the switches S1 − S5; b voltage across the switches S6-S10

Full size image
Fig. 12
figure 12

Current stress for each of the switches: a current across the switches S1 − S5; b current across the switches S6-S10

Full size image

5.2 Experimental results

To validate the feasibility of proposed topology, a five-level prototype was established. The corresponding experiment results and experiment parameters are provided in Fig. 13 and Table 5, respectively.

Fig. 13
figure 13

Experimental results: a waveforms of output voltage, output current, and voltage of the capacitors C1 and C2 under pure resistive loading conditions; b waveforms of output voltage, output current, voltage of the capacitors C1 and C2 under resistive-inductive loading conditions; c, d, e voltage waveforms of switches; f, g output voltage and output current when the load changes; h output voltage and output current when the modulation changes; i. j output voltage and output current when the output frequency changes

Full size image
Table 5 Experimental parameters
Full size table

Figure 13a shows experimental waveforms of the output voltage, load current, and capacitors’ voltage under purely resistive load conditions. It can be seen from this figure that the output voltage levels are ± 60 V, ± 30 V, and 0, which are consistent with the theoretical analysis of ± 2Vdc, ± Vdc, and 0. In addition, the capacitors’ voltage waveforms are stable and can be maintained at near 30 V, which meets the inverter ripple setting requirements. These results confirm the correctness of the inverter structure and modulation method from the experimental point of view.

Figure 13b shows experimental waveforms of the inverter output voltage, load current, and capacitors’ voltage under a resistive-inductive load. The output voltage in the figure is a five-level wave, the output current is a standard sine wave, and the waveform is stable. The voltage waves of the capacitors C1 and C2 both fluctuate at 30 V. The capacitor voltage is self-balanced and the ripple fluctuations are less than 3 V, which is consistent with the theoretical analysis.

Figure 13c–e shows voltage waveforms for each of the switching devices of the inverter. It can be seen that the MBV withstood by the ten switches is 60 V, that is 2Vdc, which is consistent with the theoretical analysis.

The above experiment is a steady-state experiment. It can be seen that the proposed inverter shows good steady-state performance. To verify the stability of the proposed inverter structure, the following experiment verifies the dynamic performance of the inverter from three angles: load change, modulation change, and output frequency change. Figure 13f and Fig. 13g shows the waveforms of the output voltage and output current of the proposed inverter from a purely resistive load to a resistive–inductive load, and from a resistive–inductive load to a pure resistive load, respectively. It can be seen that when the load changes, the response is fast, and the proposed inverter can still work stably.

When the modulation index M of the inverter changes, the resulting experimental waveforms of the output voltage and output current are shown in Fig. 13h. When the index M varies from 0.9 to 0.4, the resulting output voltage changes from five levels to three levels. In this experiment, when M changes, the inverter works normally, and the output voltage and output current can quickly reach the expected waveform.

Figure 13i and j shows experimental results of the inverter output voltage and output current when the modulation frequency of the inverter is changed. In Fig. 13i, the inverter output frequency is changed from 50 to 100 Hz, and in Fig. 13j, the inverter output frequency is changed from 100 to 200 Hz. As can be seen from these results, when the frequency of the modulation wave changes, the output voltage and output current quickly reach the target waveform, and the inverter responds quickly.

Based on the above discussion, it can be seen that the inverter can respond quickly and operate stably when the modulation degree and output frequency change suddenly, which shows the good dynamic performance of the inverter.

6 Conclusion

This study presents an extensible single dc source five-level MLI based on a switched-capacitor structure. The proposed MLI eliminates the need for H-bridge due to the inherent polarity reversal capability. In addition, the voltage of two capacitors can be self-balanced without any auxiliary circuits. Although ten switches are employed, only two switches have a voltage stress of 2Vdc, and only five gate drivers are required, which significantly reduces the total voltage stress and cost of proposed inverter. In addition, the output levels and boosting factor can be raised by employing multiple switched-capacitor cells. Moreover, the maximum blocking voltage for all of the switches is kept within 2Vdc in the extended structure. A comparative study with other topologies showed that the proposed inverter has the advantages of reducing the TSV, the MBV, and the number of the power devices. Finally, the correctness and feasibility of the proposed multilevel inverter are validated through the simulation and experiment results obtained from a laboratory prototype.