1 Introduction

Recently, power electronics technology has been focusing on improving power density and power-conversion efficiency. For this, the use of advanced power semiconductor switches like GaNs or SiC MOSFETs has been considered [1,2,3,4]. In addition, new circuits that can improve the performance of existing converters have been developed to enhance power-conversion efficiency while improving or maintaining power density [5,6,7].

The phase-shifted full-bridge (PSFB) converter with a center-tapped transformer shown in Fig. 1 has many advantages such as zero-voltage switching (ZVS) operation without the help of any auxiliary circuits, clamped voltage stress, small RMS current stress of the primary switches, and low secondary-side conduction loss [8,9,10]. Due to these advantages, it has been one of the most promising topologies for low-voltage and high-current applications such as data-center power supplies, power supplies for communication equipment, and battery chargers for neighborhood electric vehicles [11,12,13]. Although the PSFB converter in Fig. 1 has been widely used in many applications, there exist many challenges when it comes to improving the performance of the converter. First, the ZVS operation of the lagging-leg switches in the PSFB converter fails under light load conditions. Figure 2 shows key waveforms of the PSFB converter in Fig. 1, where the lagging-leg switches are defined as Q3 and Q4 in the converter. The secondary rectifier stage is separated from the transformer primary side before Q3 or Q4 turn-off due to the zero-voltage interval of the voltage Vab, as shown in this figure. Therefore, the resonance between the series inductor Llk and the parasitic capacitors Coss3 and Coss4 occurs at the moment Q3 or Q4 turns off, and the zero-voltage switching of Q3 or Q4 can be achieved by this resonance. However, since the value of Llk is generally very small which makes the characteristic impedance of the resonant circuit become small, ZVS is not achieved as soon as the load drops even under slightly less than full load conditions. Due to this, its conversion efficiency is severely degraded when the load decreases [14,15,16]. Secondly, if the converter is suitable for wide operating ranges due to design considerations such as hold-up time requirements or wide output-voltage ranges like battery chargers, the operating duty-cycle becomes small under normal operating conditions and the freewheeling interval lengthens. As a result, the excessive circulating current appears on the primary side as shown in Fig. 2, which results in increasing the primary-side conduction loss and turn-off switching loss of the lagging-leg switches [17,18,19]. In addition, although the on-state of the switches Q1 and Q3 or Q2 and Q4 form a wide operating-duty in the Vab voltage waveform, the circulating current increases the duty loss Dloss and decreases the effective duty-cycle Deff, which contributes to the power transmission. As a result, the area of the transformer primary voltage Vpri, which is really transmitted to the transformer secondary coils, decreases. Thus, the desired output voltage is not obtained. To overcome this problem, the transformer turn-ratio n should be lower than the case of no circulating current, at which point both the primary-side current and secondary-side voltage stresses significantly increase [20].

Fig. 1
figure 1

Phase-shifted full-bridge (PSFB) converter with a center-tapped transformer

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Fig. 2
figure 2

Key waveforms of the PSFB converter in Fig. 1

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Many PSFB converters have been presented to overcome the abovementioned disadvantages. To reduce the circulating current, the PSFB converters in [16, 20,21,22,23,24,25] require auxiliary circuits consisting of capacitors, diodes, and active switches in the secondary rectification circuit. The PSFB converters in [26, 27] deviate from the problem of circulating current by decreasing the value of a DC (direct current) blocking capacitor in series with a transformer. However, in this case, the voltage drop across the DC blocking capacitor is increased due to its small capacitance. Therefore, the transformer's primary voltage becomes lower. This makes it difficult to regulate the desired output voltage or current without an unfavorable design of the transformer turn-ratio in terms of primary-side current and secondary-side voltage stresses. The PSFB converters in [28,29,30,31,32] are integrated with other DC/DC converters such as half-bridge pulse-width-modulation (PWM) converters or LLC resonant converters to guarantee a wide ZVS range in the presence of load variations without the loss of an effective duty-cycle. As a result, the circulating current is alleviated and the secondary-side voltage stress is significantly reduced. However, they require two or more transformers to highlight their advantages. Although the performance can be improved by replacing the output inductor with a single coupled inductor, this solution is limited to PSFB converters with a full-bridge rectifier that uses four diodes [33].

This paper focuses on the development of new circuits for improving power-conversion efficiency while overcoming the abovementioned challenges of the PSFB converter in Fig. 1. Figure 3 shows the PSFB converter proposed in this paper for improving the performance of the converter in Fig. 1. As can be seen in Fig. 3, the primary-side structure of the proposed converter is the same as that of the conventional PSFB converter. Meanwhile, the rectification circuit is structured by rearranging the secondary circuit shown in Fig. 1, and adding an additional diode Da after replacing the output inductor with a coupled inductor. This structure reduces the circulating current in Fig. 1 and enables the proposed PSFB converter to operate with larger effective duty-cycles over a wide operating range. Due to this, the transformer turn-ratio can be designed better in terms of primary-side conduction loss and secondary-rectifier voltage stress. Due to the reduction in the secondary-side voltage stress, diodes with a lower forward-voltage drop can be used in the proposed converter, which results in an additional reduction of the power loss on the secondary side. With these advantages, the proposed converter can achieve a higher power-conversion efficiency when compared to the conventional converter in Fig. 1.

Fig. 3
figure 3

Proposed converter

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The remainder of this paper is organized as follows. In Sect. 2, both a description and the operation principle of the proposed converter are presented. Relevant analysis results are given in Sect. 3. In Sect. 4, experimental results and a comparison of the conventional and the proposed converters are presented. Finally, some conclusions are made in Sect. 5.

2 Operation principle

Figure 4 shows key operating waveforms of the proposed converter in the steady-state. The proposed converter has 18 operation modes in one switching cycle. However, only the operation during the first half-switching cycle is analyzed  as in Fig. 5 due to symmetry. For analyzing the steady-state operation, the following assumptions are made.

  • The input and output voltages are constant with respect to Vin and Vout.

  • The parasitic capacitors of the switches have the same capacitance as Coss.

  • The coupled inductor has a turn-ratio of 1:1. In addition, it has turns of NCI, a magnetizing inductance of LCI, and a high coupling-coefficient.

  • The influence of parasitic capacitors of rectifier diodes is ignored.

Fig. 4
figure 4

Key operating waveforms of the proposed converter in the steady-state

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Fig. 5
figure 5

Operating circuits: a Mode 1; b Mode 2; c Mode 3; d Mode 4; e Mode 5; f Mode 6; g Mode 7; h Mode 8; i Mode 9

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Mode 1 [t0, t1]: In mode 1, the switches Q1 and Q3 are in the on-state. Hence, the primary-winding voltage of the transformer VP is the input voltage Vin, which is transmitted to the secondary windings by the transformer turn-ratio. In addition, the diode D1 is forward-biased and the diodes D2 and Da are reverse-biased. Then, the voltage across the coupled inductor VCI becomes Vin/n − Vout, which linearly increases the current flowing via the magnetizing inductance of the coupled inductor. The primary-side current iP is the sum of the transformer magnetizing currents iLm and iCI flowing through the coupled inductor. The current and voltage equations in this mode are as follows.

$$V_{{{\text{CI}}}} = V_{{{\text{in}}}} /n - \,V_{{{\text{out}}}}$$
(1)
$$i_{{{\text{CI}}}} (t) = i_{{{\text{CI}}\_lkg1}} (t) = i_{D1} (t) = i_{{{\text{CI}}}} (t_{0} ) + \frac{{V_{{{\text{CI}}}} }}{{L_{{{\text{CI}}}} }}(t - t_{0} )$$
(2)
$$i_{Lm} (t) = i_{Lm} (t_{0} ) + \frac{{V_{in} }}{{L_{m} }}(t - \,t_{0} )$$
(3)
$$i_{P} (t) = i_{Lm} (t) + i_{CI} (t)/n$$
(4)

Mode 2 [t1, t2]: Mode 2 starts when the switch Q3 is switched off. Then, the parasitic capacitors COSS3 and COSS4 of the leading-leg switches Q3 and Q4 are charged or discharged. The voltages across Q3, Q4 and VP can be expressed as follows.

$$V_{{Q_{3} }} (t) = \frac{{i_{P} (t_{1} )}}{{2C_{{{\text{OSS}}}} }}(t - t_{1} ) = V_{{{\text{in}}}} - V_{{Q_{4} }} (t) = V_{{{\text{in}}}} - V_{P} (t)$$
(5)

During this mode, the primary-side voltage VP linearly decreases from the input voltage as in Eq. (5). Under this influence, the coupled inductor voltage VCI linearly decreases toward − Vout/2 and the voltage across Da, VDa also decreases toward 0 V. Then, VDa becomes 0 V at the end of this mode and diode Da turns on.

Mode 3 [t2, t3]: Mode 3 starts with the turn-on of the auxiliary diode Da in the rectifier circuit. At this time, the voltage VP is 0 V and the body diode of Q4 is conducted. Figure 6c shows an equivalent circuit for the analysis of this mode. Assuming that the two leakage inductances in the coupled inductor have the same value, the voltages in the equivalent circuit can be determined as follows:

$$L_{{{\text{CI}}\_lkg1}} = L_{{{\text{CI}}\_lkg2}} = L_{{{\text{CI}}\_lkg}}$$
(6)
$$V_{{{\text{CI}}\_lkg1}} = - V_{{{\text{CI}}\_lkg2}} = - \frac{{L_{{{\text{CI}}\_lkg}} }}{{2L_{{{\text{CI}}\_lkg}} + \frac{{4L_{lkg} }}{{n^{2} }}}}V_{{{\text{out}}}}$$
(7)
$$V_{Llkg} = - V_{{L_{m} }} = - \frac{{nV_{{{\text{out}}}} L_{lkg} }}{{n^{2} L_{{{\text{CI}}\_lkg}} + 2L_{lkg} }} \approx - \frac{{nV_{{{\text{out}}}} }}{2}$$
(8)
Fig. 6
figure 6

Equivalent circuits of the proposed converter during: a Mode 3; b Mode 7; c Mode 8

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From Eq. (8), it is noted that since the leakage inductance of the coupled inductor is very small due to its high coupling coefficient design, the transformer leakage inductance voltage VLlkg is nearly 50% of the negative output voltage with a turn-ratio. Then, the transformer primary current iP can be determined as follows:

$$i_{P} (t) = i_{P} (t_{2} ) - \frac{{nV_{{{\text{out}}}} }}{{2L_{lkg} }}(t - t_{2} )$$
(9)

Equation (9) gives the currents of the coupled inductor as follows:

$$i_{{{\text{CI}}\_lkg1}} (t) = i_{D1} (t) = i_{{{\text{CI}}\_lkg1}} (t_{2} ) - \frac{{V_{{{\text{out}}}} }}{{2L_{lkg} }}(t - t_{2} )$$
(10)
$$i_{{{\text{CI}}\_lkg2}} (t) = \frac{{V_{{{\text{out}}}} }}{{2L_{lkg} }}(t - t_{2} ) = i_{Da} (t)$$
(11)

Mode 4 [t3, t4]: Mode 4 starts when Q4 turns on under zero-voltage switching (ZVS). During this mode, the voltages applied to the leakage inductance of the transformer are the same as the analysis results from Mode 3. Therefore, the currents flowing through the coupled inductor continue to linearly decrease or increase as in Eqs. (10) and (11). The current of the rectifier diode D1 also decreases linearly.

During the interval from time t2 to t4, the primary-side current iP is not transmitted to the transformer secondary-side since VP is 0 V. It only circulates through Q1, Q4, and the transformer. However, due to the negative output voltage applied to the transformer leakage inductance as in Eq. (9), iP continues to decrease until it reaches the transformer magnetizing current iLm as shown in Fig. 4. This mechanism verifies that the proposed converter has smaller circulating currents when compared to the conventional PSFB converter. This fact will be explained in detail in the next section.

Mode 5 [t4, t5]: Mode 5 starts when iP reaches iLm. At this moment, the diode D1 is turned off with zero current and the currents via the coupled inductor become the same. In this mode, the voltage VLm becomes 0 V and iLm only flows in the primary side. The currents of the coupled inductor can be expressed as follows:

$$i_{{{\text{CI}}\_lkg1}} (t) = i_{{{\text{CI}}\_lkg2}} (t) = i_{Da} (t) = i_{{{\text{CI}}\_lkg1}} (t_{4} ) - \frac{{V_{{{\text{out}}}} }}{{2L_{{{\text{CI}}}} }}(t - t_{4} )$$
(12)

Mode 6 [t5, t6]: Mode 6 starts when the switch Q1 is turned off. Then, the parasitic capacitors of the lagging-leg switches Q1 and Q2, COSS1 and COSS2 are charged or discharged. The voltages across Q1 and Q2 can be expressed as follows:

$$V_{Q1} (t) = \frac{{i_{Lm} (t_{5} )}}{{2C_{{{\text{OSS}}}} }}(t - t_{5} ) = V_{{{\text{in}}}} - V_{Q2} (t) = - V_{P} (t) \approx - V_{Lm} (t)$$
(13)

In this mode, the primary voltages VP and VLm linearly decrease from 0 V to a negative input voltage as shown in Eq. (13). When VLm reaches − nVout/2, the rectifier diode D2 voltage becomes 0 V and D2 conducts.

Mode 7 [t6, t7]: Mode 7 starts when the diode D2 conducts in mode 6. Figure 6g shows an equivalent circuit for the analysis of this mode. From this analysis, the voltages and current in this mode can be determined as follows:

$$V_{Q1} (t) = \frac{{nV_{{{\text{out}}}} }}{2} + \sqrt {\frac{{L_{lkg} }}{{2C_{{{\text{OSS}}}} }}} i_{P} (t_{6} )sin\frac{1}{{\sqrt {2C_{{{\text{OSS}}}} L_{lkg} } }}(t - t_{6} )$$
(14)
$$V_{Q2} (t) = V_{{{\text{in}}}} - V_{Q1} (t) = V_{{{\text{in}}}} + V_{P} (t)$$
(15)
$$V_{{L_{m} }} (t) = - nV_{{{\text{out}}}} /2$$
(16)
$$i_{P} (t) = i_{P} (t_{6} )\cos \frac{1}{{\sqrt {2C_{{{\text{OSS}}}} L_{lkg} } }}(t - t_{6} )$$
(17)

From Eqs. (14), (15), and (17), it is noted that the voltages of the lagging-leg switches increase or decrease in sinusoidal form due to the resonance between the transformer leakage inductance and the switch parasitic capacitances. This mode ends when the voltage of Q2 reaches zero.

Mode 8 [t7, t8]: Mode 8 starts when the Q2 voltage becomes 0 V. Figure 6h shows an equivalent circuit for an analysis of mode 8. Analyzing the equivalent circuit gives the voltages in this figure as follows:

$$V_{{{\text{CI}}\_lkg1}} = - V_{{{\text{CI}}\_lkg2}} = - \frac{{L_{{{\text{CI}}\_lkg}} }}{{2L_{{{\text{CI}}\_lkg}} + \frac{{4L_{lkg} }}{{n^{2} }}}}\left( {\frac{{2V_{{{\text{in}}}} }}{n} - V_{{{\text{out}}}} } \right)$$
(18)
$$V_{Llkg} = - \frac{{L_{lkg} (2V_{{{\text{in}}}} - nV_{{{\text{out}}}} )}}{{n^{2} L_{{{\text{CI}}\_lkg}} + 2L_{lkg} }} \approx - \left( {V_{{{\text{in}}}} - \frac{{nV_{{{\text{out}}}} }}{2}} \right)$$
(19)

In Eq. (19), if the coupling coefficient of the coupled inductor is high and its leakage inductance is exceedingly small, the transformer leakage inductance voltage VLlkg is the sum of the negative input voltage and half of the output voltage with a turn-ratio and is negative. Then, the transformer primary current iP in this mode can be determined as follows:

$$i_{P} (t) = i_{P} (t_{7} ) - \frac{{V_{{{\text{in}}}} - 0.5nV_{{{\text{out}}}} }}{{L_{lkg} }}(t - t_{7} )$$
(20)

Equation (9) gives the currents of the coupled inductor as follows:

$$i_{{{\text{CI}}\_lkg1}} (t) = i_{Da} (t) = i_{{{\text{CI}}\_lkg1}} (t_{7} ) - \frac{{(V_{{{\text{in}}}} /n - 0.5V_{{{\text{out}}}} )}}{{L_{lkg} }}(t - t_{2} )$$
(21)
$$i_{CI\_lkg2} (t) = i_{CI\_lkg2} (t_{7} ) + \frac{{(V_{in} /n - 0.5V_{out} )}}{{L_{lkg} }}(t - t_{7} )$$
(22)

Mode 9 [t8, t9]: Mode 9 starts when Q2 is turned on under ZVS. Since the equivalent circuit explaining the operation of this mode is the same as that shown in Fig. 6c, the voltage and current equations in this mode are identical to the analysis in mode 8. This mode ends when the auxiliary diode Da reaches zero, and D2 supplies all of the load current.

3 Relevant analysis results

3.1 Circulating current

Figure 7 shows a comparison of operation waveforms of the proposed and conventional converters.

Fig. 7
figure 7

Comparison of operating waveforms: a conventional converter; b proposed converter

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Figure 7a shows the circulating current flowing through the transformer and the switches for an interval with a primary-side voltage VP of 0 V, which is indicated by the shaded areas in the figure. This current, which does not contribute to power transmission, continuously flows through the inverter-stage switches and the transformer primary-winding, which results in additional conduction loss. In addition, this current increases the turn-off switching loss when the lagging-leg switches Q1 and Q2 are turned off.

Figure 7b shows the circulating current in the proposed converter, which is indicated by the shaded area in the figure. From a comparison with the conventional converter, it can be clearly seen that the proposed converter features a smaller circulating current when compared to the conventional converter. Its principle can be explained by the following mechanism. In the mode where the primary-side voltage VP is 0 V, the auxiliary diode Da is in the on-state. Then, the transformer leakage inductance gets a voltage that resets the current flowing to 0A from the output stage due to the coupled-inductor circuit. As a result, the primary current iP is reset to the transformer magnetizing current iLm for an interval of with a primary-side voltage VP of 0 V. This results in a reduced circulating current and lower current stress when compared to the conventional converter.

3.2 Voltage gain analysis

As shown in Fig. 4, the voltage applied to the coupled inductor VCI is Vin/n − Vout during the power transmission mode and − Vout/2 during the freewheeling mode. Then, the voltage gain of the proposed circuit can be obtained with the voltage-second-balance principle as follows:

$$M = \frac{{V_{{{\text{out}}}} }}{{V_{{{\text{in}}}} }} = \frac{{4D_{{{\text{eff}}}} }}{{n(1 + 2D_{{{\text{eff}}}} )}}$$
(23)

In Eq. (23), Deff refers to an effective duty-cycle. Figure 8 shows the normalized voltage gain according to the effective duty-cycle. From this analysis, it can be clearly seen that the proposed converter has higher voltage gains when compared to the conventional converter. This advantage enables the proposed converter to have a much better turn-ratio n in terms of primary-side current and secondary-side voltage stresses when compared to the conventional converter.

Fig. 8
figure 8

Normalized voltage gain

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3.3 Voltage stress analysis

The rectifier diodes in the conventional and proposed converters experience the highest voltage stress in the power transmission mode. In the case of the conventional converter with a center-tap rectifier circuit shown in Fig. 1, the rectifier diode has voltage stress of more than two times the voltage of the secondary-side windings of the transformer when considering that voltage rigging occurred by the parasitic components. This can be expressed as the following equation:

$$V_{{D_{1} {\text{or}}\,D_{2} }} = \frac{{2V_{{{\text{in}}}} }}{n} + V_{{{\text{ringing}}}}$$
(24)

The voltage stress applied to the rectifier diode in the proposed converter is similar to Eq. (25). However, as explained in the previous part, the proposed converter can be designed with a higher transformer turn-ratio n than the conventional converter under the same duty-cycle due to higher voltage gains. As a result, the voltage stress of the rectifier diodes in the proposed circuit is lower than that of the conventional converter. This means that when an RCD snubber circuit with the same time-constant is used, the snubber loss in the proposed circuit is much lower than that in the conventional converter. In addition, diodes with lower forward-voltage drop can be used for the proposed converter due to its lower voltage stress, which can enable an improvement of the conduction loss at the rectifier stage.

3.4 ZVS condition analysis

Zero-voltage switching (ZVS) of the leading-leg switches in the proposed converter can be easily achieved over a wide load variation due to the large magnetizing inductance of the coupled inductor. This principle is similar to that of the leading-leg switches in the conventional converter [16, 28].

The ZVS operation of the lagging-leg switches in the proposed converter was explained in the analysis of mode 7 in the previous section. From Eq. (14) and Fig. 4, the ZVS condition for the lagging-leg switches of the proposed converter can be set up as follows:

$$V_{Q1} (t_{7} ) = \frac{{nV_{{{\text{out}}}} }}{2} + \sqrt {\frac{{L_{lkg} }}{{2C_{{{\text{OSS}}}} }}} i_{P} (t_{6} )sin\frac{1}{{\sqrt {2C_{{{\text{OSS}}}} L_{lkg} } }}(t_{7} - t_{6} ) > > V_{{{\text{in}}}}$$
(25)

The iP(t6) in Eq. (14) can be easily obtained as in Eq. (15) by analyzing Fig. 4.

$$i_{P} (t_{6} ) \approx \frac{{D_{{{\text{eff}}}} T_{S} V_{{{\text{in}}}} }}{{2L_{m} }}$$
(26)

When assuming the interval of mode 7 with Tdead, which is the dead-time between Q1 and Q2, the ZVS condition of Eq. (25) can be expressed as follows:

$$\begin{gathered} \sqrt {\frac{{L_{lkg} }}{{2C_{{{\text{OSS}}}} }}} i_{P} (t_{6} )sin\frac{1}{{\sqrt {2C_{{{\text{OSS}}}} L_{lkg} } }}(T_{{{\text{dead}}}} ) > > V_{{{\text{in}}}} - \frac{{nV_{{{\text{out}}}} }}{2} \hfill \\ \Rightarrow \sqrt {\frac{{L_{lkg} }}{{2C_{{{\text{OSS}}}} }}} i_{P} (t_{6} )\frac{{T_{{{\text{dead}}}} }}{{\sqrt {2C_{{{\text{OSS}}}} L_{lkg} } }} > > V_{in} - \frac{{nV_{{{\text{out}}}} }}{2} \hfill \\ \end{gathered}$$
(27)

By putting Eq. (26) into Eq. (27), the design equation for the transformer magnetizing inductance guaranteeing the ZVS operation of the lagging-leg switches can be obtained as follows:

$$L_{m} < < \frac{{D_{{{\text{eff}}}} T_{S} T_{{{\text{dead}}}} }}{{2C_{{{\text{OSS}}}} }}\left( {2 - \frac{{nV_{{{\text{out}}}} }}{{V_{{{\text{in}}}} }}} \right)^{ - 1}$$
(28)

3.5 Duty-cycle loss

The conventional converter in Fig. 1 requires an additional inductor in series with the transformer to extend the ZVS range of the lagging-leg switches. However, this additional inductor reduces the effective duty-cycle and narrows the power transmission interval. Then, the wanted output voltage or current cannot be achieved. To compensate for this, the transformer turn-ratio n should be lowered, which greatly increases the primary-side current and secondary-side voltage stresses. It also causes an increase in snubber loss and conduction loss.

On the other hand, ZVS of the lagging-leg switches in the proposed converter can be extended by decreasing the transformer magnetizing inductance as in Eq. (28). The transformer magnetizing inductance has the advantage of not generating the problems related to duty-cycle loss since it forms a parallel connection with the output load.

4 Experimental results

To demonstrate the validity of the proposed converter, prototype converters were designed and manufactured with the following specifications. To mitigate voltage overshoots and oscillation, prototype converters were built by adding snubber circuits. The design specifications for the prototypes are as follows:**

  • Input voltage: Vin = 300–400 V

  • Output voltage: Vout = 50 V

  • Maximum output current: Iout(max) = 20 A

  • Switching frequency: ƒs = 100 kHz

Table 1 shows a list of the components used to build the prototypes, and Fig. 9 shows photos of the manufactured converters.

Table 1 Prototype converter components
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Fig. 9
figure 9

Prototype photos: a conventional converter; b proposed converter

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The equation for designing the coupled inductor in the proposed converter can be set up from Fig. 4, Eq. (1) and (2).

$$L_{{{\text{CI}}}} > \frac{{D_{{{\text{eff}}}} T_{S} }}{{\Delta I_{{L_{CI} }} }}\left( {\frac{{V_{{{\text{in}}}} }}{n} - V_{{{\text{out}}}} } \right)$$
(29)

For a small core loss, an appropriate current ripple is selected. Then, the magnetizing inductance LCI can be designed with Eq. (29). The size of the core for the coupled inductor can be selected with the required LCI and the magnitude of the current flowing through the coupled inductor. Once the size of the core is determined, the turns of the windings can be determined from Faraday’s law from the effective cross-sectional area of the core and the level of the voltage across the coupled inductor in Fig. 4. The proposed converter needs a coupled inductor with a turn-ratio of 1:1 and a high coupling coefficient. For a high coupling coefficient, the coupled inductor for the proposed converter was made with the bifilar winding method in [34].

The prototype converters were regulated with a TMS320F28335-based controller.

4.1 Waveforms

Figures 10 and 11 show key operating-waveforms of the proposed and conventional converters at a 300 V or 400 V input and 50 V and 20 A outputs. From Figs. 10b and 11b, it is confirmed that all of the measured waveforms follow the operation analyzed in Fig. 4 and Sect. 2 well. It is also confirmed that the proposed converter has a significantly reduced circulating current when compared to the conventional converter. In addition, it is clearly verified from the value of Ip(rms) in the figures that the primary RMS (root-mean-square) current stress is decreased due to the reduction of the circulating current.

Fig. 10
figure 10

Key waveforms of the prototype converters at input voltage 300 V and 100% load: a conventional converter; b proposed converter

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Fig. 11
figure 11

Key waveforms of the prototype converters at input voltage 400 V and 100% load: a conventional converter; b proposed converter

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Figures 12, 13, and 14 show the inverter output voltage Vp(t), primary current ip(t), and rectifier diode voltages of the proposed converter at input voltages of 300 V and 400 V according to the load currents. These experiments verify that the ZVS of the lagging-leg switches in the proposed converter can be effectively achieved over wide load conditions.

Fig. 12
figure 12

Key waveforms of the proposed converter at 10% load: a input voltage 400 V; b input voltage 300 V

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Fig. 13
figure 13

Key waveforms of the proposed converter at 50% load: a input voltage 400 V; b input voltage 300 V

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Fig. 14
figure 14

Key waveforms of the proposed converter at 80% load: a input voltage 400 V; b input voltage 300 V

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4.2 Diode voltage stress

Figure 15 shows the voltage stress of the rectifier diodes at an input voltage of 400 V and an output of 50 V and 1 kW using the same snubber circuit. The snubber circuit design can be seen in Table 1. As shown by the experimental results in Fig. 15, since the proposed converter is made with a higher transformer turn-ratio n due to higher voltage gains than the conventional converter, it is confirmed that the voltage stress is reduced by more than 39 V. The reduced voltage stress means that the proposed converter has a lower snubber loss when compared to the proposed converter.

Fig. 15
figure 15

Rectifier diode voltage stress of the prototype converters at input voltage 400 V and 100% load: a conventional converter; b proposed converter

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4.3 Efficiency

Figure 16 shows the efficiency measured using a power analyzer (WT500, YOKOGAWA) under input voltage 300 V and 100% load conditions. As can be seen from these experimental results, the proposed converter achieves a higher power conversion efficiency. Figure 17 shows an efficiency curve according to the output load conditions. As shown in Fig. 17, the proposed converter has a maximum efficiency of 94.7%, and its efficiency is greatly improved when compared to the conventional converter. This is due to the fact that the conduction loss of the proposed converter is reduced as a result of the reduction in the circulating current and the turn-off switching loss. In addition, the reduction in the snubber loss due to lower voltage stress on the secondary-side rectifier diode also contributes to improved efficiency. Figure 18 shows the loss reduction factor of the proposed converter by analyzing the losses for each of the elements in the proposed and conventional converters.

Fig. 16
figure 16

Measured Efficiency at input voltage 300 V, output voltage 50 V, and output power 1.0 kW: a conventional converter; b proposed converter

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Fig. 17
figure 17

Measured efficiencies according to the load conditions

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Fig. 18
figure 18

Loss breakdown of the prototype converters at input voltage 400 V, output voltage 50 V, and output power 1.0 kW

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5 Conclusions

This paper presents a PSFB converter that can improve the performance of a PSFB converter with a center-tap rectifier circuit. To achieve this improvement, the proposed converter relaces the output inductor with a single coupled inductor and adds an auxiliary diode. With these structural changes, the proposed converter achieves the following advantages:

  1. (1)

    Reductions in the conduction loss and turn-off switching loss due to a reduction in the circulating current.

  2. (2)

    Reductions in the rectifier diode voltage stress and snubber loss by the feature of a higher voltage gain.

  3. (3)

    Soft-switching of the lagging-leg switches independent of load conditions due to the transformer magnetizing inductance.

Due to the above advantages, the proposed converter can achieve higher efficiency than the conventional converter. To confirm the superiority of the proposed converter, this paper presents the operating principle, steady-state analysis, and experimental results under a 1.0 kW, 300–400 V input voltage, and a 50 V output voltage. From the theoretical analysis and experimental results, it can be concluded that the proposed converter is applicable to low voltage, high current, and wide input or output operating applications such as data-center power supplies, communication equipment power supplies, and battery chargers for neighborhood electric vehicles.