1 Introduction

The energy demand is rising day by day due to the advancement of the industrial sector. To preserve fossil fuels for the future, the scope of energy generation relies heavily on renewable energy sources. The installation of a PV plant in the industry serves non-critical loads, thus reducing tariff stress in the industry [1]. The power extracted from PV is DC that must be converted to AC for further use by integrating it with an inverter. The design of the conventional H-bridge inverter for medium and high load ratings makes the system size larger and more expensive. The Level of THD is also high while combining solar PV with a conventional H-bridge inverter. Multilevel inverters (MLIs) were introduced with different topologies [2] to improve the quality of inverter power. Generally, classified MLI topologies are voltage source inverters (VSI) and current source inverters (CSI) [3]. Some of the notable VSI classified designs are Neutral Point Clamped (NPC), Flying capacitors (FC), and Cascaded H-Bridge (CHB) inverters [4]. The nature of robustness, reliability, and efficiency in the synthesisation of quality output signals makes CHB an appropriate tool for integrating it into the Renewable Energy conversion systems [5]. The CHB can be modeled either in symmetric or asymmetric operating mode. CHB is said to operate in symmetric mode when it has similar DC source as input and produce linear output voltage upon input source voltage. In asymmetric mode, CHB has dissimilar input DC voltage sources and produces either linear or non-linear output depending on the input voltage source [6, 7]. The modified CHB topology is developed to address the problem of non-balancing voltage [8] to reduce the number of switches requirement. An MLI system [9] was designed to operate under symmetrical and asymmetrical operating modes for high voltage applications. MLI structures with the modified H-Bridge Topology were proposed [10, 11] and these topologies use a high number of switching devices. This entire setup is used as a basic unit to generate AC output signals from the DC source. The main objectives of Multilevel Inverters are reducing the number of switches; Low switching losses; increasing the output voltage levels and reducing the total harmonic distortion. The schematic drawing of generalized MLI with multiple DC sources is presented in Fig. 1.

Fig. 1
figure 1

Schematic drawing of MLI topology

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This article presents a Multi-Source Cascaded Multilevel Inverter (MSCMLI) topology with a reduced number of switches. Without altering the structure and number of switches, the presented topology can be used for both Symmetric Multilevel Inverter (SMI) and Asymmetric Multilevel Inverter (AMI). It consists of ‘n’ number of basic units that is described by several factors such as the required output voltage, number of levels, Total Harmonic Distortion (THD), number of switches or control drivers, etc. This topology has the advantage of being able to supply the power to load continuously if any of the input sources are in malfunctions.

2 The Recommended Topology

The presented topology has ‘n’ number of series-connected basic units to supply the required range of output levels. A basic unit consists of two sources V1,1 controlled by a switch S1,1 and V1,2 controlled by a switch S1,2 as shown in Fig. 2a. Both sources are connected with the load if the switch S1,1is turned on and bypassed by the switch S1,3 when the switch S1,1 and S1,2 are off. Each basic unit will produce an output voltage of ±2VDC when connected to the Load. This circuit employs a level booster module which consists of a voltage source connected with a switch SA in series as shown in Fig. 2b. A bypass switch SB is employed to bypass the source to produce zero voltage level in the output.

Fig. 2
figure 2

a Basic Module of MSCMLI Topology b Level Booster Circuit

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The general structure of the Multi-Source Cascaded Multilevel Inverter (MSCMLI) topology is given in Fig. 3a which contains ‘n’ number of basic units and a level booster circuit. Voltage sources used in the first basic unit are V1,1 and V1,2 while, the voltage sources used in the nth basic unit are represented as Vn,1 and Vn,2. The presented topology can be used as a Symmetric Topology if all the input Voltages are equal (V1,1 = V1,2 = …. = Vn,1 = Vn,2 = VA = VDC) and an Asymmetric Topology if the input voltages are unequal. This paper presents a Symmetric topology A1 and two Asymmetric topologies A2 and A3.

Fig. 3
figure 3

a General structure of Recommended MSCMLI topology with Level Booster Circuit b Seven Level circuit

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The basic parameters of the presented topology are, number of switches Sswitch and the required number of sources Ssource is given by (1),

$$S_{SWITCH} = 4_{n} + 6$$
(1)

The actual requirement of the number of input DC sources is (2),

$$S_{SOURCE} = 2_{N} + 1$$
(2)

Where n – number of basic units

(1) & (2) are common for the presented symmetric topology A1 and for the asymmetic topologies A2 and A3. The other parameters like the number of output voltage levels (NLEVEL), maximum output voltage (VAC), and total blocking voltage (VBLOCK) are described by the number of basic units ‘n’ and the number of sources used in the circuit. For the symmetric topology A1,

$$N_{LEVEL} = 4n + 3$$
(3)
$$V_{AC} = \left( {2n + 1} \right)V_{DC}$$
(4)

Figure 3b shows a seven-level Symmetric MSCMLI topology for n=1 in A1. It consists of a basic unit and one level booster unit. From (1) and (2), the number of switches and sources of the given topology is described as 10 and 3 respectively. Similarly, (3) and (4) describes that the MSCMLI topology produces seven levels in the output waveform and the maximum output voltage will be 3VDC.

Figure 4 shows the three different modes of operation of the presented topology at the positive half cycle of the output voltage. By considering the value of input voltage sources V1,1 = V1,2 = VA = VDC, this topology can produce an output level of −3VDC to +3VDC. Figure 4a shows the operation of A1 for +VDC output. Only V1,1 is connected to the load through S1,1 and the other sources are bypassed using S1,3 and SB. +2VDC level is produced by connecting V1,1 and VA through the switch S1,1 and SA while V1,2 is not connected as shown in Fig. 4b. Figure 4c shows the operating mode for +3VDC output in which all input sources are connected with the load. During the negative half cycle of output, switches S2 and S4 will be turned on for the same modes of operation.

Fig. 4
figure 4

Operating modes of MSCMLI in Positive Half cycle a for output +V1,1 b for output +V1,1+ VA c for output +V1,1+ V1,2+ VA

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2.1 Harmonic Reduction in MLI

The Selective Harmonic Elimination (SHE) algorithm is implemented, which removes the particular harmonic order by calculating the optimum angles of triggering using mathematical expressions [12]. Literature reviews show that the tailored selective harmonic elimination algorithms can be extracted to reduce THD in multi-level inverters [13,14,15]. For MLI, different switching angles for each level such as β1, β2, β3, …βN is desirable for reduction of lower order harmonics and the conditions are as follows,

$$\beta _{1} < {\text{ }}\beta _{2} < {\text{ }} \ldots {\text{ }} < \beta _{{(n - 1)}} < {\text{ }}\beta _{N} < ~90$$
(5)
$$cos\left( {\beta_{1} } \right) + cos\left( {\beta_{2} } \right) + cos\left( {\beta_{3} } \right) + \ldots + cos\left( {\beta_{N} } \right) \, = \, \left( {N_{LEVEL} - 1} \right) \, * \, M_{a} /2$$
(6)

Where,

NLEVEL – Number of output levels.

$$N = \frac{{N_{LEVEL} - 1}}{2}$$
(7)

Ma – modulation index and the equation expressed as

$$M_{a} = \frac{{V_{R} }}{{N.V_{DC} }}$$
(8)

Where, VR – Reference Voltage

VDC – Input Voltage

The expression to evaluate the lower order harmonics is given by the equation (9),Where,

$$V_{h} \left( t \right) = \mathop \sum \limits_{h = 3,5,7, \ldots } \frac{{4V_{in} }}{n\pi }\left[ {\cos \left( {h\beta_{1} } \right) + \cos \left( {h\beta_{2} } \right) + \cos \left( {h\beta_{3} } \right) + \ldots . + {\text{cos}}\left( {h\beta_{N} } \right)} \right]$$
(9)

h – Order of the harmonics.

Normally, calculations required for the firing angles are the sum of individual harmonic with all firing angles are considered as zero. For an NLEVEL output voltage, N-1 individual harmonic values can be eliminated using (10). So for the seven-level Symmetric MSCMLI, any two individual harmonic orders can be eliminated.

$$\mathop \sum \limits_{h = 3,5,7, \ldots } \frac{{4V_{in} }}{n\pi }\left[ {\cos \left( {h\beta_{1} } \right) + \cos \left( {h\beta_{2} } \right) + \cos \left( {h\beta_{3} } \right) + \ldots . + {\text{cos}}\left( {h\beta_{N} } \right)} \right] = 0$$
(10)

2.2 Control Strategy

Reduction in THD and lowered switching losses improve the quality of output voltage significantly. To achieve a distortion-less output voltage, a higher rate of switching control strategy is essential. Hence, the recommended topology use Phase Opposition Disposition (POD) has to reduce the power loss in the inverter circuit and reduce the THD. In this method, ‘N’ values of triangular waveforms with equal phase-amplitude are compared with a sinusoidal reference waveform of fundamental frequency or grid frequency. Using(5), the seven-level MSCMLI topology, three triangular waveforms are compared with the reference waveforms as shown in Fig. 5a and we get three pulses with firing angles β1, β2, and β3. In addition to that, the Optimal Firing Angle Control (OFA) strategy is also used to compare the performance of the presented MLI schemes. OFA strategy works on fundamental frequency and generates the triggering gate signals for semiconductor switching devices. This method generates the gating signals by taking the reference signal as pure sine waveform with fundamental frequency or grid frequency and compared with the required DC voltage levels as shown in Fig. 5b. The advantage of using the OFA strategy is that it avoids synchronizing problems when used in grid-connected systems. The determined gating signals with required firing angles achieved from OFA and POD schemes are used for the MSCMLI system to obtain the required stepped output voltage waveform with the reduced THD. From (5) to (10), for the proposed 7-level symmetric MLI, the 7th and 11th order harmonics are mitigated by calculating suitable firing angles β1, β2, and β3.

Fig. 5
figure 5

Generation of gate pulse for the MSCMLI using the comparison of carrier and reference sinusoidal signal in a OFA b POD

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The reference DC voltage for the respective firing angle is calculated in OFA based on the following expression,

$$DC_{i} = \, M_{a} V_{R} sin\left( {\beta_{i} } \right)$$
(11)

Where, i = 1, 2,….N,Ma – modulation index, and β – Required firing angle, \(N = \frac{{N_{LEVEL} - 1}}{2}\), VR – Maximum value of sine reference voltage

From (11), it is described that three DC voltage levels are required to compare with a sine wave to produce the firing angles β1, β2, and β3 using the OFA method.

2.3 Efficiency Calculation

The efficiency of the MSCMLI is calculated to compare its performance with other topologies of MLI. The efficiency of MLI is determined by accounting for the conduction loss and the switching loss in the power electronic devices. The total losses (PT) of the inverter circuit in a cycle is given by [16],

$$P_{T} = \mathop \sum \limits_{n = 1}^{{N_{IGBT} }} P_{c,IGBTn} + P_{SW,Tn} + \mathop \sum \limits_{n = 1}^{{N_{DIODE} }} P_{c,Dn} + P_{SW,Dn}$$
(12)

Where, Pc,IGBT – conduction loss of IGBT

PSW,T – switching loss of IGBT

Pc,D – conduction loss of Diode

PSW,T – switching loss of Diode

It is inferred from the above expression that the losses continue to increase on increasing the power electronic devices in the system. The efficiency of the inverter circuit is determined by (13) after including the conduction and switching losses.

$$\eta = \frac{{P_{L} }}{{P_{L} + P_{T} }} \times 100$$
(13)

Where output power, \(P_{L} = \frac{{V_{rms}^{2} }}{R}\) and the Vrms denotes the output rms voltage of the inverter. Hence, the reduction in switches in the inverter reduces the switching losses associated with it and increases the efficiency of the inverter. Taking the prescribed values of the parameters, the theoretical efficiency of the inverter is 98.6%, with a maximum output voltage of 300V.

3 Asymmetric Topologies

This paper presents Two Asymmetric Topologies A2 and A3 based on the structure shown in Fig. 3a, in which the input voltage sources have unequal magnitudes. Table 1 shows the basic parameters like the output voltage Levels (NLEVEL), the maximum value of output voltage (VAC), and total blocking voltage (VBLOCK) of the presented algorithms based on the number of basic units ’n‘.

Table 1 Multi-source Cascaded Multilevel Inverter (MSCMLI) Algorithm with Related Parameters
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For n=1 in all presented algorithms, the basic parameters of Asymmetric Topology A2 will be

NLEVEL = 6(1)+3 = 9 and VAC = [3(1)+1]VDC = 4VDC

and the basic parameters of Asymmetric Topology A3 will be NLEVEL = 11 and VAC = 5VDC

Table 2 gives the switching sequence for a 9-level inverter derived from asymmetric mode A2 and for an 11-level inverter derived from asymmetric mode A3 as per Table 1. Eventhough the number of basic modules required is the same for A2 and A3, the number of output voltage levels is higher for A3. Figure 6 shows the output voltage waveforms of Asymmetric Topologies A2 and A3. It shows that A3 has two more levels than A2 which has nine levels for the single basic module used.

Table 2 Switching sequence for A2 and A3 asymmetric algorithms with one basic module (n=1)
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Fig. 6
figure 6

output waveform of Asymmetric Topologies A2 and A3 for n=1

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4 Comparison with other Topologies

In the recommended topologies, the number of switches and diodes count is less when compared with other topologies of MLI as discussed in the literature as shown in Table-3. The graph is plotted between the number of DC sources versus the number of switches required and the number of levels versus the number of switches. The recommended topology is compared with the other topologies such as DCMLI, FCMLI and CHB MLI [4], modified MLI-b [17] modified MLI-c [18], modified MLI-d [19], modified MLI-e [11], modified MLI-f [20], modified MLI-g [21], modified MLI-h [22], modified MLI-i [23] and modified MLI-j [24]. Since the number of switches and the number of sources is equal in all suggested algorithms, only two algorithms A1 and A2 are considered for comparison shown in Fig. 7. The MLI-d and f structures use bi-directional switches so that a single bi-directional switch is considered to be two unidirectional switches. MLI- g and i use diodes in the structure to produce multiple levels in the output regardless of having a good level to source ratio and a single source.

Fig. 7
figure 7

Comparison of A1 and A2 with contemporary MLI topologies

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The comparison shows that the number of switches required for a given number of DC sources is lower for the recommended topology when the number of sources is four or more. Figure 7 shows the number of levels for the given number of switches for the recommended topology with the topologies suggested in various articles. As mentioned earlier, the number of levels in symmetrical topology A1 is higher than other topologies mentioned in the literature. The number of output levels is almost doubles in A1concerning other topologies. As A2 is concerned, it has the same number of switches as A1 and the output level is higher since it has asymmetric input sources. Another asymmetric algorithm A3 is not considered for comparison because it is also having an asymmetric structure and it gives a very high number of output levels for the given number of switches which is practically difficult to achieve. Apart from the conventional comparisons, the MSCMLI inverter has equal load sharing and bypassing capabilities when any one of the inputs malfunctions. The other topologies that have these capabilities are CHB and MLI-e. In the view of the number of switches, drivers, levels, and blocking voltage concerned, the presented topology is a good alternative for the conventional MLIs and the other topologies presented in the works of literature compared. Table 3 gives a comparative analysis of the different topologies for Number of Levels (NLEVEL), Number of Sources (NSOURCES), and number of switches (NIGBT), Number of Drivers (NDRIVER), and Number of Diodes (NDIODE) with respect to number of basic units (n)

Table 3 Comparison of Device count for symmetrical and Asymmetrical configurations
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5 Results and Discussion

The simulation circuit with hardware setup of the recommended 7-Level symmetric topology and 9-level asymmetric topology are developed and results are discussed in this section.

5.1 Simulation Results and Discussion

The simulation model of the recommended 7-level SMI circuit is modeled using MATLAB using the input sources voltage VDC = 100V in each section and the R-L loads R=200 Ω and L=35mH. POD PWM and OFA PWM technique were adopted to generate gate signals and to produce a 7-level waveform at the output. The OFA scheme uses the standard or load frequency to minimize the output frequency deviation, while the POD has a higher carrier frequency suitable for minimization of THD. The output voltage and current waveforms of the recommended 7-level SMI with POD-PWM technology subject to different load conditions are shown in Fig. 8a-c with a THD value of 8.28% as shown in Fig. 8d. It is clearly described from the waveforms shown that the switching transients have been reduced in output and the current waveform is smooth. To improve visibility, the current waveform is amplified. Figure 8e-f show the waveform of the output voltage and current under various load conditions using the OFA technique. Figure 8e portrays load voltage and load current values under maximum load condition and Fig. 8f displays the load voltage and load current values under the half load condition of the system proposed. Besides, the magnitude of the voltage is the same as the 300 V peak value at each degree of load conditions. From both examples, the load current is sinusoidal like waveform. This indicates that the suggested method has reduced distortion and that the harmonics are not present in the output waveforms.

Fig. 8
figure 8

a-c Output voltage and current waveforms of A1 with POD PWM for various load conditions d THD spectrum of the Symmetric topology A1 e-f Output voltage and current waveforms with OFA PWM for various load conditions

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Figure 9 depicts the output of algorithm A2 with one basic module and a level booster. Figure 9a and b portray load voltage and load current values under maximum load and half load conditions respectively with the POD-PWM scheme. Figure 9c and d show the output of Asymmetric MLI structure A2 full load and half load conditions respectively for NVL-PWM method employed for same operating conditions. Figure 9e depicts the voltage harmonic spectrum of asymmetric topology A2 at full load condition. The THD value of A2 is 6.96% in comparison with the THD value of 8.28 % for A1. Figure 9f shows the output voltage and current waveform for A3 algorithm with the output voltage of 11 levels.

Fig. 9
figure 9

output voltage and current waveforms of AMI-A2 (a, b) with POD-PWM at 100% and 50% Load conditions (c, d) with NVL-PWM at 100% and 50% Load conditions (e) THD spectrum of A2 (f) output voltage and current of A3

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Table 4 represents a comparison between the fundamental voltage THD value with the presented PWM strategies like, (a) Phase Opposition Disposition (POD) technique & (b) Optimal Firing Angle Control (OFA) technique against several modulation indices. From this table, it is clear that the suggested POD method is having a better THD value in comparison with other methods and it is proven that the proposed method is minimizing the harmonics present in the output voltage with a reduced number of switches. This guaranteed the effectiveness of the recommended method. The minimum value of Total Harmonic Distortion (THD) is 8.28 as described earlier is taken at a modulation index of 0.9 by using the POD-PWM method.

Table 4 Fundamental Voltage and %THD values of SMI topology for various PWM methods
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5.2 Hardware Results and Discussion

To validate the results of the MATLAB simulation, the experimental hardware setup is developed and the trigger gate pulses are generated using the FPGA SPARTAN kit as shown in Fig. 10. Among other microcontrollers, FPGA is chosen for its ability to troubleshoot loops and parallelism. FPGA produces gating pulses using VHDL code with the help of software called ALTERA QUARTUS-II Version 7.2. The experiment was performed with each VDC = 100V with R-L load condition. The output voltage of the recommended 7-level SMI is shown in Fig. 11a which has an amplitude of 300V. From Fig. 11b, the output voltage has a period of 20ms for a single cycle hence the output frequency is equal to the power frequency 50Hz. The current waveform of the recommended 7-level SMI is shown in Figure 11c, which has an amplitude of 1.5A current for a load of 200Ω and 35mH. This waveform has less distortion and near sinusoidal. Harmonic analysis of recommended SMI is shown in Fig. 11d. The THD value of output voltage is 22% for an RMS value of 184.4V. The output voltage has higher THD levels as compared with simulation results; it is because of the practical conditions.

Fig. 10
figure 10

Hardware prototype of the MSCMLI topology

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Fig 11
figure 11

a-c Output voltage and current waveforms for the symmetric topology A1 with POD-PWM d THD spectrum of A1 e output voltage of the asymmetric topology A2 f THD spectrum of A2

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Figure 11e indicates the output voltage waveform of the Asymmetric MSCMLI topology A2, which follows the sinusoidal reference waveform of the reference voltage of the POD-PWM technique and thus reduces the filtering requirements at the output stage. Finally, Fig. 11f shows the THD value of A2that is 16% forthe output voltage of 300V at full load. The harmonic analysis shows the 19th and 21st order harmonics are more dominant and can be eliminated using filters.Losses were calculated for the inverter designed with the following parameters [17] VT = 2.5V, VD = 1.5V, RT= 0.85, RD = 0.15, λ = 1, ton = toff= 2ms. Practically, with a loss of 16W on the circuit, the overall efficiency of the system is 96.4% for an input voltage and a current of 300 V and 1.5 A respectively. From the waveforms, it is clearly stated that the THD values have been reduced by increasing the number of levels in the circuit. The output current is also nearly sinusoidal waveform with fewer distortions.

5.3 Comparisons of Simulation and Hardware Results

The simulation and hardware results were analyzed and compared for the same load conditions. From the Table 5, one can understand that the Simulation and hardware parameters of the symmetric topology A1 and asymmetric topology A2 are same. The maximum obtained output voltage is also equal but the hardware THD % only higher than the simulation result. This THD can be reduced by designing passive filter for the given circuit. This extension work will be carried out as a future scope.

Table 5 Comparison of simulation and hardware parameters
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6 Conclusion

This article presented a seven-level Symmetric Multi-Source Cascaded Multilevel Inverter (MSCMLI) topology with a reduced number of switches. The simulation results of the presented topologies under various load conditions were executed and the results were drawn up. The hardware setup was implemented to verify the output of the simulation and the results were analyzed. The absence of bidirectional switches is the primary advantage of the MSCMLI topology that reduces the overall switch count, driver requirement and switching losses in the inverter circuit. Moreover, the symmetric MSCMLI was compared to the other topologies presented in the literature. Eventhough the number of sources is equal in all SMI topologies, the simplicity and of the presented topology reduces the complexity of the control algorithms during the implementation of the hardware prototype. In addition to that, the MSCMLI would have the bypassing capacity to supply the load if there is a problem with any of the switches in the level circuit. This article also presented a nine level and eleven level asymmetric topologies that increase the number of levels without increasing the number of basic units.Simulation and hardware outputs were presented and analysed for the AMI topology.THD values were also compared for the simulation and harware findings.Performance of the presented topologies have been verified with two different PWM techniques and the POD-PWM produced the lesser THD value.The MSCMLI topology can be used in renewable energy integration applications where there are discrete DC sources with fewer electronic switches.