1 Introduction

The increasing demand for more and more powerful logic devices drives the continued size and operational scaling of complementary metal oxide semiconductor (CMOS) devices. Performance benefits and greater complexity gained by scaling enable many advancements in electrical equipment. Researchers have devised a number of techniques to shrink the dimensions of a particular CMOS device without sacrificing performance. By incorporating fin field effect transistor (FinFET) [1], GAA nanowire transistors [2,3,4], and other possible architectures, one essential objective is to enhance the static control of the gate.

Many manufacturing firms consider the GAA nanowire transistor to be a good contender for next-generation CMOS devices due to its higher degree of efficiency and compliance with the fabrication process. But still GAA nanowire FET is not perfect to be used under 32 nm process due to short channel effects. In order to make this transistor more unsusceptible to short channel effects (SCE), a replacement of the conventional channel material silicon is needed. In this regard, Daniel Nagy et al., developed a Si-NW-GAAFET with good transistor characteristics at room temperature having a Subthreshold Swing of 70 mV/dec, DIBL of 55 mV/V, Ion of 1590 uA/um and Ioff about 9.9 uA/um [5]. In 2018, Rafael Vinicius Tayette da Nobrega et al. evaluated the modeling of nanowire GAAFET with several Group III-V [6]. The oxide material used in Rafael Vinicius’ device is SiO2, which is linked at the gate interface. But still performance was not found satisfactory, the reason being the lower relative permittivity or dielectric constant (k) [7] of SiO2 in comparison to the other contenders for the gate oxide materials [5, 6, 8]. However, in order to improve the electrical characteristics of FETs, gate oxides based on high-k materials have significantly improved the performance of GAA nanowire FET [6, 8]. In this regard, a simulation based comparative analysis of the electrical performance of silicon (Si) and Group III-V materials in GAA nanowire FETs has been presented. Secondly, the effect of hafnium dioxide (HfO2) and zirconium dioxide (ZrO2) as inorganic gate insulators on the device performance has been evaluated.

2 Methodology and Device Specifications

The method followed in the simulation process is shown in Fig. 1. To begin, the majority of study on the physical and electrical characteristics of channel materials, dielectric values of the gate oxides as well as the work function of the gate metal has been examined through the literature survey, which is cited as [9,10,11,12,13,14,15,16,17,18,19,20,21]. To develop a device with high speed and low power, a range of channel materials including Silicon (Si), Gallium Antimonide (GaSb), Gallium Nitride (GaN), Aluminum Gallium Arsenide (AlGaAs), Gallium Arsenide (GaAs), and Indium Phosphide (InP), as well as high-k gate oxides namely Hafnium Dioxide (HfO2, k ~ 22) and Zirconium Dioxide (ZrO2, k ~ 32) are examined. Figures 2 and 3 demonstrate the outer 3D structure of the proposed GAA nanowire FET and the cross-section device structure of a GAA n-channel nanowire FET respectively.

Fig. 1
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Methodology followed in the simulation process

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Fig. 2
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3D structure of the proposed GAA nanowire FET

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Fig. 3
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Cross-section device construction in 2D for geometry x and geometry y of GAA nanowire FET

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The proposed nanowire FET includes thickness of gate oxide (Tox), diameter of channel (Dch), Gate Length (Lg), length of Source and Drain terminals (Ls and Ld respectively). Tox, the thickness of oxide is retained at 1.5 nm and remained constant throughout the simulations. The source & drain extension lengths were each chosen at 30.8 nm for simulation purposes, while the gate length is retained at 22 nm, and the channel diameter was kept at 12.76 nm. The doping of the drain and source is kept constant at 5E + 19 cm−3, while the channel is doped at 1E + 15 cm−3. The gate bias is set between 0 and 1 V, whereas the drain bias is set between 0.05 and 1 V for I-V characteristics while all other parameters are measured at Vd = 1 V. Gate overlap with the source and gate overlap with the drain have not been taken into account. Gaussian doping for source and drain is kept at 7.1 nm and penetration into oxide was kept at 0.05 nm (Table 1).

Table 1 GAA nanowire FET device dimensions and parameters
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3 Results and Discussion

MUGFET (Multi-Gate Field Effect Transistor) software [22] is used to simulate the device at the nanoscale level. Before carrying out the simulations, the device is calibrated. For the calibration purpose, we compared our proposed model with the existing one in [5] at two parameters namely subthreshold swing and DIBL. A slight variation in the parameters is observed due to the simulator limitations. The respective calibration data for DIBL and SS is shown in Fig. 4 in form of bar Graphs.

Fig. 4
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Calibration of GAA nanowire transistor model parameters

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We recovered the DIBL, SS, Ion, transconductance and ratio of Ion/Ioff parameters after verifying the simulator. The study is extended to include ZrO2 as other gate dielectric and the substitution of GaAs, GaN, GaSb, AlGaAs and InP for Si nanowire. The respective I–V Curves for different channel materials with HfO2 as gate oxide and I-V Curves for different channel materials with ZrO2 as gate oxide are shown in Fig. 5a and b respectively. Table 2 and 3 depict the findings of these studies and their comparison with Daniel Nagy’s transistor model [5] at 22 nm of technology node and Fig. 6a, b, 7a, b, 8a, b and represent the findings of our study in the form of bar graphs. All the results have been derived at Vd and Vg = 1.0 V.

Fig. 5
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a Comparison of I-V curves for various channel materials with HfO2 as gate oxide. b Comparison of I-V curves for various channel materials with ZrO2 as gate oxide

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Table 2 Performance analysis of different channel materials using different parameters with HfO2 as gate oxide
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Table 3 Performance analysis of different channel materials using different parameters with ZrO2 as gate oxide
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Fig. 6
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a Subthreshold Swing comparison for various channel materials with HfO2 as gate oxide. b Subthreshold Swing comparison for various channel materials with ZrO2 as gate oxide

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Fig. 7
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a DIBL comparison for various channel materials with HfO2 as gate oxide. b DIBL comparison for various channel materials with ZrO2 as gate oxide

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Fig. 8
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a Transconductance comparison with various channel materials using HfO2 gate oxide. b Transconductance comparison with various channel materials using ZrO2 gate oxide

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For the perfect transistor, a smaller subthreshold swing is always preferred because Subthreshold Swing is the gate voltage needed to shift the drain current by an order of magnitude, or one decade. Group III-V materials and AlGaAs delivers the better Subthreshold Swing than Silicon except GaN GAA-NW transistor. Lowest Subthreshold Swing was registered for InP, which is followed by AlGaAs GAA-NW transistor at second place in terms of performance. Based on the data in Tables 2 and 3, replacing the HfO2 gate oxide with ZrO2 resulted in a DIBL decrease for all transistors. The Subthreshold Swing of all NW-GAA-FETs also decreases when gate oxide dielectric constant increases.

The short channel effect known as DIBL describes a transistor's threshold voltage being reduced at a greater drain voltage. Low threshold voltage leads to more leakage current. When scaling a transistor, it is usually preferable to keep it as low as possible. For Drain Induced Barrier Lowering all of the proposed materials performed better than Silicon with GaAs and AlGaAs registering the lowest of the values. In comparison to [5] our transistor model has registered a huge improvement by decreasing DIBL from 57 to 1.58 mV/V while using AlGaAs as the channel material and ZrO2 as gate oxide. This proves that a transistor using AlGaAs can maintain its threshold voltage and hence minimize the leakage current.

In the case of transconductance or the transistor gain GaN and GaAs registered the best performance numbers, followed by AlGaAs at third place which performed marginally better than Silicon. As can be seen from the comparative Tables 2 and 3, the transistor has highest gain, when the gate oxide is replaced with the dielectric of high dielectric constant (ie. ZrO2 with k = 32.57). In this case the comparison with [5] is not possible because a proper study of transconductance parameter has not been included in the study.

Group III-V materials might have benefits in terms of some performance parameters, but they have their own disadvantages. The Group III-V materials showed a considerable drop in the electrical characteristics due to poor Leakage Current (Ioff) performance. The comparatively lighter masses of electrons and holes of Group III-V materials result in better mobility and saturation velocity of both the carriers in the channel and hence it results in a high “On current” (Ion) but it also results in a high leakage current (Ioff) therefore the ratio (Ion/Ioff) is poor for Group III–V materials. Also, in comparison to AlGaAs the DIBL of Group III–V materials was high which was another factor resulting in high leakage current of Group III–V materials. However, AlGaAs is the only material which not only outperformed Silicon but every single Group III-V material by its electrical performance, due to its better DIBL performance, larger band gap and slightly heavier masses of the carriers. If we compare our AlGaAs/ ZrO2 model with the Si/High-k model from [5] a significant improvement in the current ratio from 1.60E+04 in [5] to 5.91E+09 in our work can be seen. The comparison of Ion/Ioff ratio is shown in Fig. 9a, b respectively.

Fig. 9
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a Comparison of current ratio Ion/Ioff of various channel materials using HfO2 as gate oxide. b Comparison of current ratio Ion/Ioff of various channel materials using ZrO2 as gate oxide

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4 Conclusions

In this work, results on performance analysis of Gate All Around Nanowire FET with Group III-V Compound Channel Materials and High-k Gate Oxides have been presented. A nanowire FET structure based on gate all around technology has been investigated to study the impact of replacing conventional gate dielectrics with high-k gate dielectrics and conventional channel material, silicon with group III–V materials and their compounds. The electrical performance parameters under consideration were drain induced barrier lowering (DIBL), subthreshold swing (SS), threshold voltage (VT), current on–off ratio (Ion/Ioff) and transconductance. The major findings and related conclusions are summarized and some ideas on future works are suggested.

2-D Numerical simulation model of nanowire FET with GAA technology was carried out at 22 nm gate length using an open-source nanoscale simulation tool MUGFET (multi-gate field effect transistor) available at nano-hub [22]. The nanowire FET model was simulated using high performance channel materials such as Silicon (Si), Gallium Nitride (GaN), Indium Phosphide (InP), Gallium Antimonide (GaSb), Gallium Arsenide (GaAs), and Aluminum Gallium Arsenide (AlGaAs). The effect of electric field on charge transport in the channel is investigated with high-k gate oxides; Hafnium Dioxide (HfO2, k ~ 22) and Zirconium Dioxide (ZrO2, k ~ 32).

The simulation results suggest that using combination of hafnium dioxide (HfO2) with Aluminum Gallium Arsenide (AlGaAs) semiconductor channel material shows significant improvement in DIBL ~ 1.84 mV/V, subthreshold swing SS ~ 72.54 mV/dec, Ion/Ioff ~ 4.82 × 109, transconductance (gm ~ 8.68E−4) and comparable value in terms of threshold voltage VT ~ 0.60 V) with respect to rest of the materials. In second investigation, combination of Zirconium Dioxide ZrO2 with Aluminum Gallium Arsenide (AlGaAs) results in improved DIBL ~ 1.58 mV/V, Ion/Ioff ~ 5.91 × 109, transconductance (gm ~ 1.04E−03) and comparable values in terms of threshold voltage VT ~ 0.59 V) and subthreshold swing SS ~ 72.41 mV/dec. The combination of Zirconium Dioxide ZrO2 with Aluminum Gallium Arsenide (AlGaAs) clearly stands out as preferred gate oxide and semiconductor over Si/SiO2 and AlGaAs/HfO2 combination as specific and other combinations as general.