Abstract
A fully differential energy-efficient switching scheme for binary-weighted capacitor digital-to-analog converter (DAC) is presented. It is observed that the proposed switching scheme reduces energy consumption of DAC by 97% and the capacitance area by 50% over the conventional ones. The effect of supply and common mode voltage variations on the linearity of successive approximation register (SAR) analog-to-digital converter (ADC) is reduced. Moreover, with this switching scheme, one can achieve the same dynamic range as the conventional one, with half the supply voltage as compared to the existing schemes. This makes the proposed switching method suitable for ultra-low-voltage SAR ADCs, which are widely used in biomedical applications. The proposed method is modelled using MATLAB. The results show that the nonlinearity (INL and DNL) caused by capacitor mismatch is reduced. The circuit-level implementation of 10-bit SAR ADC is simulated using UMC 90nm CMOS 1P9M process technology.
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McCreary, J.L.; Gray, P.R.: All-MOS charge redistribution analog-to-digital conversion techniques. I. IEEE J. Solid State Circuits 10(6), 371–379 (1975)
Ginsburg, B.P.; Chandrakasan, A.P.: An energy-efficient charge recycling approach for a SAR converter with capacitive DAC. In: IEEE International Symposium on Circuits and Systems (ISCAS), pp. 184–187. IEEE (2005)
Chang, Y.K.; Wang, C.S.; Wang, C.K.: A 8-bit 500-KS/s low power SAR ADC for bio-medical applications. In: IEEE Asian Solid-State Circuits Conference (ASSCC), pp. 228–231. IEEE (2007)
Liu, C.C.; Chang, S.J.; Huang, G.Y.; Lin, Y.Z.: A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure. IEEE J. Solid State Circuits 45(4), 731–740 (2010)
Zhu, Y.; Chan, C.H.; Chio, U.F.; Sin, S.W.; Seng-Pan, U.; Martins, R.P.; Maloberti, F.: A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS. IEEE J. Solid State Circuits 45(6), 1111–1121 (2010)
Yuan, C.; Lam, Y.: Low-energy and area-efficient tri-level switching scheme for SAR ADC. Electron. Lett. 48(9), 482–483 (2012)
Rahimi, E.; Yavari, M.: Energy-efficient high-accuracy switching method for SAR ADCs. Electron. Lett. 50(7), 499–501 (2014)
Xie, L.; Su, J.; Liu, J.; Wen, G.: Energy-efficient capacitor-splitting DAC scheme with high accuracy for SAR ADCs. Electron. Lett. 51(6), 460–462 (2015)
Tong, X.; Chen, Y.: Low-power high-linearity switching procedure for charge-redistribution SAR ADC. Circuits Syst Signal Process 36(9), 3825–3834 (2017). https://doi.org/10.1007/s00034-016-0483-4
Babayan-Mashhadi, S.; Lotfi, R.: Analysis and design of a low-voltage low-power double-tail comparator. IEEE Trans Very Large Scale Integr (VLSI) Syst 22(2), 343–352 (2014)
Yazdani, B.; Khorami, A.; Sharifkhani, M.: Low-power DAC with charge redistribution sampling method for SAR ADCs. Electron. Lett. 52(3), 187–188 (2015)
Yazdani, B.; Khorami, A.; Sharifkhani, M.: Low-power bottom-plate sampling capacitor-splitting DAC for SAR ADCs. Electron. Lett. 52(11), 913–915 (2016)
Tong, X.; Ghovanloo, M.: Energy-efficient switching scheme in sar adc for biomedical electronics. Electron. Lett. 51(9), 676–678 (2015)
Tong, X.; Zhang, Y.: 98.8% switching energy reduction in sar adc for bioelectronics application. Electron. Lett. 51(14), 1052–1054 (2015)
Pelgrom, M.J.; Duinmaijer, A.C.; Welbers, A.P.: Matching properties of mos transistors. IEEE J. Solid State Circuits 24(5), 1433–1439 (1989)
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Polineni, S., Bhat, M.S. & Rajan, A. A 10-Bit Differential Ultra-Low-Power SAR ADC with an Enhanced MSB Capacitor-Split Switching Technique. Arab J Sci Eng 44, 2345–2353 (2019). https://doi.org/10.1007/s13369-018-3478-6
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DOI: https://doi.org/10.1007/s13369-018-3478-6