Abstract
Security in embedded systems is considered to be more important and needs to be a diagnosis for every minute. Also with the advent of the Internet of Things (IoT), security in the embedded system has reached its new peak of dimension. A Mathematically secure algorithm was formulated and runs on the cryptographic chips which are embedded in the systems, but secret keys can be at risk and even information can be retrieved by the prominent side-channel attacks. Fixed encryption keys, non-intelligent detection of side-channel attacks are some of the real-time challenges in an existing system of encryption. Following the limitations of existing systems, this research article focuses on the integration of powerful machine learning algorithms by retrieving the secret key information with countermeasures methodology using the chaotic logistic maps and includes the following contributions: (a) Preparation of Data Sets from the Power consumption traces captured from ARTIX-7 FPGA boards while running the Elliptical Curve Cryptography(ECC) on it (b) Implementation of High Speed and High Accurate Single feed-forward learning machines for the detection and classification of side-channel attacks (c) Design of Chaotic Countermeasures using 3-Dlogistic maps for attacked bits. The test_bed has been developed using the integration of FPGA along with Cortex-A57 architectures for experimentation of the proposed work and various evaluation parameters such as Accuracy, F-calls, Precision rates, sensitivity, and correlation co-efficient, entropy were calculated and analyzed. Moreover, the parameters of the proposed system which has been analyzed prove to outperform the other existing algorithms in terms of performance and detection.
Similar content being viewed by others
Explore related subjects
Discover the latest articles, news and stories from top researchers in related subjects.Avoid common mistakes on your manuscript.
1 Introduction
Embedded systems have been characterized by low power consumption, increased lifetime, compactness and high security. With all these characteristics, security is gaining hawk eye importance in embedded systems and has become a core requirement in embedded system designs. This leads to the design of more complicated cryptographic algorithms that runs on the embedded processors to protect the data and keys against the attacks. Even though it has been ensured that there are no mathematical relations between plaintext, ciphertext, and data, side-channel attacks are considered to be a major threat to the embedded systems. In the side-channel attacks, physical characteristics leakages were exploited to retrieve the keys and information. Paul Kocher was first to introduce the Side-channel attacks in the early 90′s (Kocher et al. 1996, 1999; Rivest 1991) which was followed by the exploration of many side-channel attacks on the hardware implementation of various encryption algorithms such as AES, RSA, DES, and even ECC (Genkin et al. 2014; Kadir et al. 2011; Standaert et al. 2003) All these algorithms are prone to various types of side-channel attacks such as simple power analysis (SPA), differential power analysis (DPA), electromagnetic analysis attacks (EAA) and timing analysis (TA). Several algorithms were proposed by one more than researchers, such as Mulder et al. have proposed the statistical models for retrieving the keys by analyzing the various Electromagnetic power attacks. Based on the results, many authors have proposed the side-channel attacks methodology and many statistical tools have been proposed for the analysis of different side-channel attacks. (Hospodar et al. 2011; Souissiet al. 2010; Gilmore et al. 2015). Recently machine learning and neural networks are gaining more and more insight among the researchers to perform the efficient side-channel attacks analysis. This requires huge datasets and an efficient classifier to perform the recovery of key from the hardware implementation of various encryption algorithms such as AES, RSA, DES and even ECC (Ors et al. 2003; Longo et al. 2015; Bhasin et al. 2015; Lerman et al. 2013). The implementation of machine learning algorithms for side-channel attacks faces major challenges such as over fitting and high dimensional data, which may lead to the inaccurate detection of attacks.
Implementation of machine learning algorithms for side-channel attacks was detailed in the limited literature but incorporating the countermeasures along with the Machine learning detection systems seems to be presented by only a few researchers (Javed et al. 2020) has presented the machine learning algorithm and integrated the countermeasures with the hamming distance redistribution principle. The author has used the Sukura FPGA boards and tested for AES encryption schemes. Moreover, the strong integration of machine learning with countermeasures still needs its brighter light of research for an efficient implementation.
2 Contribution of the research work
Our contribution is tri-fold. First, the design of new capturing and recording software for storing the raw power traces from the ECC integrated FPGA. The whole methodology has been formulated for the dataset formations which has been used as the input for the proposed machine learning algorithms. Also, it is to replace the traditional methods for recording the raw traces from the CPU with the automatic recording and storing of features with the inclusion of different attack methodologies. Secondly, we propose to use the single feed forward Extreme Learning machines to replace the other traditional machine learning algorithms. Extreme Learning machines are considered to be the most powerful and can have the highest accuracy of classification. This section deals with the preliminary usage of the Extreme learning machines and mode of using ELM for the classification of attacks. Finally, we have integrated the chaotic countermeasure methodology along with the detection/prediction of the attacks. We have introduced lightweight 3D Lorentz Logistics maps with the different initial conditions to more system more resistant against the side-channel attacks.
The remaining of the paper is arranged as follows, Sect. 2 explain the related works by more than one author. Sect. 3 discusses the proposed methodology, ECC on ARTIX-7 FPGA, Extreme Learning Machines (ELM) for classification of attacks and 3D logistic maps for countermeasures. Experimental setup, results, performance evaluations were presented in Sect. 4 while Sect. 5 concludes the paper along with the future improvisation.
3 Related works
Zhao and Edward Suh (2018) developed a software-based power monitor to analyze the power consumption on side channels. The proposed model includes three stages initially on-chip power monitor using ring oscillators (ROs) have been developed. In the second stage, the power side-channel introduced in FPGA and experimentally observed the effects on FPGA-FPGA and FPGA-CPU. Using the proposed model, diverse power analyses are recorded. The power monitor can observe the power consumption of programs on a CPU and be used for attacks against a timing-channel mitigation countermeasure.
The authors in Srivastava and Ghosh (2019), proposed an efficient memory deletion technique called MBIST (Zeroization technique) to protect the memory data before the hacking process. In recent days, many attacks such as cold, boot, side-channel attacks, and physical attacks are high effects the memory data. Traditionally memory data are protected using deletion method in minimum time by initializing the memory to all zeros. The drawback of the traditional deletion method requires specialized hardware in SoCs to delete the memory data before the attacks and also it is based on IPs which can be hacked easily. To overcome these challenges, the authors developed an individual memory zeroization technique integrated with MBIST (Memory built-in self-test) to avoid the specialized hardware and also improved the performance.
In Singh et al. (2019) proposed a design space of the SIMON128 encryption engine and a lightweight block cipher for power image sensor node to enhance the side-channel security and optimize the power, area and PSCA resistance. Initially, serial and parallel data path architectures are implemented and observed diverse metrics. In the second phase, round unrolling can significantly enhance the side-channel security through deep diffusion of the input key when sufficient rounds are unrolled. Finally, energy-efficiency and performance of the proposed SIMON128 are compared with AES128.
Ehsan saeedi, developed the learning vector quantization (LVQ) neural network for detection of side-channel attacks in the FPGA architectures. Power consumption and electromagnetic emission of instruction are recognized automatically using LVQ. This machine learning classifier experimentally tested in the ECC cryptosystem for the detection of side-channel leakage. The limitation of the proposed LVQ model is higher in complexity and trained with lower datasets (Ehsan et al. 2017).
Liu et al. proposed a resource-efficient ring-LWE cryptographic processor to secure the system from side-channel attacks. The processor design includes the discrete Gaussian sampler and a modular processing element. Discrete Gaussian sampler mainly focused on the minimization of side-channel attacks in-ring-LWE cryptography and highly secured the systems compared to the traditional model. The modular processing element is designed to improve the speed of the basic modular operations in the proposed processor. The ring-LWE processor performed both encryption and decryption in the range of 256-bit message in 4.5/0.9 ms whilst it consumes only 1307 LUTs, 889 FFs, and 4 BRAMs. Ring-LWE cryptographic processor is tested in the Xilinx Spartan -6 FPGA platform (Liu et al. 2019).
In Mukhtar et al. (2018), the authors adopted the machine learning algorithms to secure the embedded systems from side-channel attacks. The main objective of the proposed framework is to retrieve the secret-key information bits on the leaked power signals. For this, the authors adopted the ECC double-and-add-always algorithm to encrypt the data with a secret key. Initially, power signals are generated with side-channel attacks to observe the data and collected different features such as amplitude and attacked bits, etc. In the second stage, Support Vector Machines (SVM), Naive Bayes (NB), Random Forest (RF) and Multilayer Perceptron (MLP) classification algorithms are analyzed with the collected datasets. Debayan Das et.al developed Cross-device Deep Learning side-Channel Attack(X-DeepSCA) with different traces are analyzed in this work. The proposed 256-classifier DNN algorithm is used to differentiate the correlational power attacks and side-channel attacks with different traces in the AES encryption system. X-DeepSCA is a single trace attack which works under low-SNRs and achieves the ~ 10X lower minimum traces (Das et al. 2019).The authors in (Shan et al. 2017), developed analyzed the machine learning model in a side-channel attack with a hamming distance in AES encryption standard. In this work, the author utilized the machine learning classifier to classify the correct and incorrect sub-keys which resists the SCA. The side-channel attack resistance method identified the best hamming distance for redistribution mapping in AES. Frequency overhead is the only metric optimized by the proposed algorithm.
3.1 Proposed architecture
In this section, proposed architecture which includes FPGA implementation, proposed machine learning algorithms and chaotic countermeasure methodology are discussed in the preceding section. The overall architecture for the proposed architecture is shown Fig. 1.
3.2 Elliptical curve cryptography on artix-7 FPGA
In this section, brief mechanism about the working of elliptical curve cryptography (ECC) and its efficient implementation on FPGA has also been discussed.
3.2.1 Elliptic curve cryptography-a brief overview
In the early 1980s, Koblitz and Millers have introduced the ECC (elliptical curve cryptography), which is now considered as the most powerful public-key cryptosystem which finds its place in various applications such as smart cards, RFID and IoT based networking applications. The ECC is proved to be more vital which includes several mathematical operations such as addition, multiplication, doubling, and division. The point multiplication is considered to be a more unique feature of ECC, requires the successive additions of ECC points by itself and also considered to be hardware-expensive operations. Let 'P' be the points and 'k' be the number of times 'P' is required to be added, then ‘Q’ be the multiplication of P and K which is given in the equation.
ECC multiplication otherwise referred to as Elliptical curve scalar multiplication (ECSM) whose security depends on the elliptical discrete problems. For the implementation of ECSM, we have adopted a simple double and add algorithm in which the operations depends on the 'k' bits. The point-double operations and point addition operations are considered to be the most important operations in ECC and it is performed on the 'k' bits. Depends on the key k-bit, either point-double or point addition operations are chosen for operations. The pseudo-code for the double and add method is presented below.
Further, we have adopted y3 = x3 + ax + b mod P where a = 0 and b = 2256–232–25–24–23–22–1. Moreover, the selection of co-ordinates for point-double and point addition and elaborate design of the ECC can be found in Blake et al. (1999).
3.2.2 Implementation on artix-7 FPGA
Elliptical curve scalar multiplication has been considered as the most important operation of ECC. The designed ECC core gets its points on elliptical curves which are discussed. The overall ECC core design is shown in the figure. Since these multiplication techniques are an area-consuming mechanism, high speed pipelining architectures are adopted for effective implementation of Artix-7 FPGA architecture. Figure 2 illustrates the overall implementation of the ECC point doubling and point addition mechanism. The number of multipliers, no of pipelining stages and clock cycles which are used for effective implementation in FPGA are depicted in Table 1.
3.3 Power traces capture mechanism
The next phase of the proposed methodology is to capture the power traces from the ECC implemented FPGA. Normally, the resistor is connected in series of FPGA to record the current traces in digital oscilloscopes. But the paper presents the novel software design to collect different power traces from the FPGA to analysis the SPA and DPA. The four major units of proposed software designs are discussed as follows.
3.3.1 Reconfigurable collection unit (RCU):
The software has a special unit for collecting the encrypted data from the hardware. The proposed has been designed with the inbuilt feature of getting the data from the UART (Universal Synchronous Receiver Transmitter) of any boards. Moreover software stores the encrypted data in the memory where it calculates the physical behaviors and records the data in terms of the power traces with different sampling rates. The whole software was developed in Python 3.6.3 with the integrated tools of numpy, matplotlib, and gtinker. Figure 3 illustrates the RCU of the proposed software.
3.3.2 Attack inducing unit (AIU)
The software has another important feature of inducing the attacks on data bit-streams. This unit will induce a bit change in the original bit location, which is then called as attacks. Each attack will have different samples such as X0, X1, X2, and X3 samples. The attack inducing 4-Unit in the software is shown in Fig. 4.
Attack levels are designed on the bit locations of the data which are then named as LBD where LB is called location bits and D is called attack induced data. The working of attack methodology is defined as follows (Fig. 5).
LB3: In this mode, LSB ‘3’ is targeted in which the third location bits are replaced with the ‘0’ and ‘1’ respectively.
LB2: In this mode, LSB ‘2’ is targeted in which the second location bits are replaced with the ‘0’ and ‘1’ respectively.
LB1: In this mode, LSB ‘2’ is targeted in which the first location bits are replaced with the ‘0’ and ‘1’ respectively.
LB0: In this mode, LSB ‘2’ is targeted in which the zeroth location bits are replaced with the ‘0’ and ‘1’ respectively.
3.3.3 Intelligent recording and capturing unit (IRCU)
This recording unit in the software is to record and capture the raw traces of data which is then used to analyze the SPA (Simple power analysis) and Differential Power Analysis (DPA) attacks. Figures 6 and 7 represents the data collection unit and the integration of attack methodology mechanisms.
3.4 Feature extraction and data set preparation
The figure shows the different power traces of encrypted ECC data. After capturing and recording the labeled raw traces of different categories of data, the next step is to calculate the features. The time-domain characteristics of raw traces were calculated and then used for the classification. The following features were extracted from the raw traces of the signals, which are discussed as follows.
3.4.1 Mean
In this case, the mean of the signal is calculated.
3.4.2 Peak detection
The sharpness and peak of raw traces are calculated before and after attacks.
3.4.3 Median
The median of the signal is calculated in the frequency domain.
3.4.4 Correlation coefficients
The similarity between the attacked traces and reference data was calculated (Correlation Coefficient) in the frequency domain again.
After calculating the features, we have normalized the data as a preprocessing technique, which is adopted for classification.
3.5 Extreme learning machine
In this section, the adoption of extreme learning machines which is used for classification of attacks based on the features obtained above (Huang et al. 2006; Lu et al. 2016) proposed the Extreme Learning Machines which are considered as the category of neural networks, in which the network utilizes a single feed-forward hidden layers, high speed and accuracy with the great speculation/exactness (Wang et al. 2015).
In this category of neural machines, the 'N' neurons in the hidden layers are required to work with differential activation functions such as sigmoidal and radial basis functions. These kinds of feed-forward networks don't require t any tuning methodology for the hidden neurons which makes it more suitable for high-speed detection and classification.
For a single hidden layer feed-forward Extreme Learning Machines, the characteristics equation is given
where x is the input feature
To determine output vector O which is called as the target vector, the hidden layers are entitled by Eq. (4)
The basic implementation of the ELM uses the minimal non -linear least square methods which are represented in Eq. (5)
where Ω ∗ → inverse of Ω known as Moore−Penrose generalized inverse. Above equation can be represent as follows
The above equation is used to determine the output values from the classifier. A further detailed description of ELM ‘s equations can be found in Dongsheng Liu et al. (2019). The pseudo-code for Extreme Learning machines used for the classification of attacks are given as follows.
3.6 Chaotic countermeasures
After classification of attacks in the particular bit location, attacked bits are then recycled to the chaotic counterpart in the hardware, which is then used for transmission in the networks. The lightweight 3D logistic maps with variable initial conditions were designed and implemented for the further prevention of the attacks (Fig. 8).
Among the three dimensional chaotic maps, the paper uses the 3D Lorentz logistic maps for the countermeasure methods. The differential equations for the 3D logistic which are given as follow as
where numerical solutions for s = 10, g = 20 d = 35 gives the chaotic characteristics of the above equations. The chaotic characteristics obtained for different values of s, g and d are shown in Figs. 9 and 10.
-
a.
For Initial condition s = 10, g = 20 d = 35
-
b.
For other initial condition s = 15, g = 23 d = 37
The above chaotic equation with the initial conditions is used to generate the key with high randomness. Every ECC points which are given as the Inputs are diffused with the newly generated keys. For the diffusion process, newly generated keys are formulated for ‘N’ times and the 'D' vector is formulated based on the XORED Operation of ECC points and proposed chaotic systems. After the formation of the new key, the 'D' vector is arranged into the matrix E and the length of the E matrix is scaled to the input data streams to prevent the data aliasing problems. The overall diffusion process which is used in the proposed methodology is given as follows:
where α is the diffusion constant and β is the diffusion process.
4 Experimental setup
This section details the experimental methodology for the hardware and software setup for implementing the proposed algorithm.
4.1 Data traces capture mechanism
To conduct our experiments, we must capture power traces from the ECC that remain be the greatest challenge. To overcome this challenge, we have adopted the hardware setup to capture the power trace signals for ECC FPGA ARTIX-7 EDGE, operating at 450 MHz. To implement our research, we have designed the python-based software to capture the power traces of the FPGA which has been implemented. The switches on the board have been used to create the different M set points in ECC and UART has been used for interfacing with software designed. The features of the board which is used for the proposed research has been listed in the Table 2.
Moreover, the features of the software which have been designed were also listed in the table. The overall setup used for the experimentation is shown in Fig. 11.
4.2 Results and discussion
Results are discussed as bi-folded analysis such as performance evaluation of the proposed classifiers and strength of chaotic countermeasure methodology.
4.3 Performance evaluation
The features which are obtained from 24,000 raw power traces of FPGA are used for evaluation, in which we used training purposed is 70% and remaining testing 30% is used. The determination is carried out for the 2 different data-sets with the based on the following parameters.
where TP and TN represent true positive and true negative values and DR and TNI represents number of detected results and total number of Iterations.
4.4 Accuracy evaluation
For accuracy evaluation, the above mathematical expression is used for the proposed extreme learning machines and other machine learning algorithms. Figure 12 shows an accurate evaluation of the proposed extreme learning machines with different hidden neurons.
From the above Fig. 13, proposed extreme learning machines have reached its convergence point at 120 neurons for obtaining the maximum accuracy of 98%. Moreover, after its RoC point, the proposed algorithm has been tested with the different activation function whose results are tabulated in Table 3
Table 3 clearly shows the accuracy is found to be high as 98.5% for the usage of the sigmoidal activation function in the proposed extreme learning machines. Also, the proposed extreme learning machines are compared with other machine learning algorithms which are shown in Fig. 13.
From the above Fig. 13, it is clear that the proposed Extreme Learning machines have the highest accuracy of detecting the attacks with 98.5% accuracy and also outperforms the other machine learning algorithms.
4.4.1 Sensitivity and selectivity analysis
The sensitivity and selectivity have been calculated by using the above mathematical expressions (15), (16) and compared with the other machine learning algorithms.
Figure 14 shows the comparative analysis for sensitivity for the proposed extreme learning machine along with the other machine learning algorithms. The sensitivity is found to be high as 95% for the proposed extreme learning machines. Also, Fig. 14 shows that selectivity is also high as 94% for the ELM when compared with other machine learning algorithms in the detection of side-channel attacks.
4.4.2 Time computation analysis
The training and testing time has been calculated for the proposed ELM and compared with the other existing algorithms. The mathematical expression for calculating the training and testing time of the proposed network is given by expression. The Table 4 shows the comparative analysis of training time and testing time for different networks.
4.5 Sensitivity analysis
To ensure the security of the overall proposed process, different medical image data sets have been used for the transmission and different parameters such as sensitivity and entropy were measured. This section details the performance of overall proposed systems when the medical image datasets were used for transmission in an IoT network. The medical Image datasets such as Mammogram Images, MRI Images, and Diabetic Retinopathy images were used for evaluation. These image data sets were downloaded from UCI respiratory and randomly chosen for evaluation. The proposed algorithm has been tested with number of negative permutation of image data bits such as the changing the input data bits with the gradual change of 1%, 5%,10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 75% and 100% changes and the following parameters such as Number of Pixel Change Rate(NPCR) and Entropy conditions were calculated by the following Eq. (13) which is used in [28]. We have used different medical images for testing the strength of the proposed chaotic countermeasure methodology.
The NPCR and entropy conditions were calculated for the different image data sets which are mentioned above and tabulated in following Tables 5 and 6.
Tables 6, 7 depicts the complete analysis for the strength of the proposed methodology with the iterations of different medical image data sets. Tables clearly state the NPCR is maintained as the constant of 99.75% for every medical data sets and entropy is also maintained at 1.30. This clearly shows that the proposed methodology is considered to be more resistant to SPA even when the different medical images are permutated at different bit levels (Table 8).
5 Conclusion and future scope
The paper analyses the results from the raw power traces from ARTIX-7 boards in which we can conclude the power leakage properties can be used as the feature for detection the various side-channel attacks. Also, the paper details the scalable new python-based software for recording and capturing the above-mentioned features. From the different classification algorithms, the paper focusses on the Extreme Learning machines which have produced more than 95% accuracy in detecting the side-channel attacks. Subsequently, the chaotic methodology was introduced and analyzed with the different parameters out of which sensitivity was found to be 99.7% for the different permutations of medical image data sets. Even though the integration of chaotic systems along with the machine learning algorithms provides more advantages such as high accuracy and high sensitivity, the replacement of machine learning algorithms along with the deep learning algorithms will make the proposed system versatile, scalable and more robust.
Change history
29 June 2022
This article has been retracted. Please see the Retraction Notice for more detail: https://doi.org/10.1007/s12652-022-04236-7
References
Bhasin S, Danger J, Guilley S, Najm Z (2015) Side-channel leakage and trace compression using normalized inter-class variance. In: Proceedings of the 3rd international workshop on hardware and architectural support for security and privacy, HASP, Portland, OR, USA, 14 June 2015, p 7
Blake I, Seroussi G, Seroussi G, Smart N (1999) Elliptic curves in cryptography. Cambridge University Press, Cambridge
Das D, Golder A, Danial J, Ghosh S, Raychowdhury A, Sen S (2019) X-DeepSCA: Cross-device deep learning side channel attack. In: proceedings of the 56th ACM/IEEE design automation conference (DAC)
Genkin D, Shamir A, Tromer E (2014) RSA key extraction via low-bandwidth acoustic cryptanalysis. In: Proceedings of the advances in cryptology—CRYPTO 2014: 34th annual cryptology conference, Santa Barbara, CA, USA, 17–21 August 2014, pp 444–461
Gilmore R, Hanley N, O'Neill M (2015) Neural network-based attack on a masked implementation of AES. In: Proceedings of the hardware oriented security and trust (HOST), Washington, DC, 5–7 May 2015, pp 106–111
Hospodar G, Mulder ED, Gierlichs B, Verbauwhede I, Vandewalle J (2011) Least squares support vector machines for side-channel analysis. In: Proceedings of the 2nd workshop on constructive side-channel analysis and secure design (COSADE), Darmstadt, Germany, 24–25 February 2011
Huang G-B, Zhu Q-Y, Siew C-K (2006) Extreme learning machine: theory and applications. Neurocomputing 70(1):489–501
Javed AR, Beg MO, Asim M et al (2020) Alpha logger: detecting motion-based side-channel attack using smartphone keystrokes. J Ambient Intell Human Comput. https://doi.org/10.1007/s12652-020-01770-0
Kadir SA, Sasongko A, Zulkifli M (2011) Simple power analysis attack against elliptic curve cryptography processor on FPGA implementation. In: Proceedings of the 2011 international conference on electrical engineering and informatics, Bandung, Indonesia, 17–19 July 2011, pp 1–4
Kocher PC, Jaffe J, Jun B (1999) Differential power analysis. In: Proceedings of the advances in cryptology—CRYPTO’ 99: 19th annual international cryptology conference, Santa Barbara, CA, USA, 15–19 August 1999; Springer, Berlin/Heidelberg, pp 388–397
Kocher PC (1996) Timing attacks on implementations of Diffie–Hellman, RSA, DSS, and other systems. In: proceedings of the advances in cryptology—CRYPTO ’96: 16th annual international cryptology conference, Santa Barbara, 18–22 August 1996; Springer, Berlin/Heidelberg, pp 104–113
Lerman L, Bontempi G, Markowitch O (2013) A machine learning approach against a masked AES. J Cryptogr Eng 5:123–139
Liu D, Zhang C, Lin H, Chen Y, Zhang M (2018) A resource-efficient and side-channel secure hardware implementation of ring-lwe cryptographic processor. IEEE Trans Circ Syst I Reg Pap 66(4):1474–83
Longo J, DeMulder E, Page D, Tunstall M (2015) SoCittoEM: electromagnetic side-channel attacks on a complex System-on-chip; cryptographic hardware and embedded systems—CHES; lecture notes in computer science, vol 9293. Springer, Berlin, pp 620–640
Lu S, Lu Z, Yang J, Yang M, Wang S (2016) A pathological brain detection system based on kernel based ELM. Multimed Tools Appl 77(3):3715–28
Mukhtar N (2018) Mohamad ali mehrabi, yinan kong and ashiq anjum, “machine-learning-based side-channel evaluation of elliptic-curve cryptographic fpga processor”. Appl Sci 9:64. https://doi.org/10.3390/app9010064
Ors SB, Oswald E, Preneel B (2003) Power-analysis attacks on an FPGA—first experimental results. In: proceedings of the cryptographic hardware and embedded systems (CHES), Cologne, 8–10 September 2003. Springer, Berlin/Heidelberg, pp 35–50
Rivest RL (1991) Cryptography and machine-learning. In: proceedings of the advances in cryptology—ASIACRYPT ’91: international conference on the theory and application of cryptology, Fuji Yoshida, Japan, 11–14 November 1991; Springer, Berlin/Heidelberg, pp 427–439
Saeedi E, Kong Y, Hossain MS (2017) Side-channel attacks and learning-vector quantization. Front Inform Technol Electron Eng 18(4):511–8
Shan W, Zhang S, He Y (2017) Machine learning based side-channel-attack countermeasure with hamming-distance redistribution and its application on advanced encryption standard. Electron Lett 53(14):926–8
Singh A, Chawla N, Ko J-H (2019) Energy efficient and side-channel secure cryptographic hardware for IoT-edge Nodes. IEEE Internet Things J. https://doi.org/10.1109/JIOT.2018.2861324
Souissi Y, Nassar M, Guilley S, Danger JL, Flament F (2010) First principal components analysis: a new side-channel distinguisher. Proc Int Conf Inf Secur Cryptol Seoul Korea 1–3:407–419
Srivastava A, Ghosh P (2019) An efficient memory zeroization technique under side-channel attacks. In: IEEE-32nd international conference on VLSI design and 2019 18th international conference on embedded systems (VLSID), pp 76–81. https://doi.org/10.1109/VLSID.2019.00032
Standaert FX, Tot Oldenzeel LVO, Samyde D, Quisquater JJ (2003) Power analysis of FPGAs: how practical is the attack? In: Cheung P YK, Constantinides GA (eds) Proceedings of the field programmable logic and application, Lisbon, Portugal, 1–3 September 2003; Springer, Berlin/Heidelberg, Germany, pp 701–710
Wang B, Huang S, Qiu J et al (2015) Parallel online sequential extreme learning machine based on MapReduce. Neurocomputing 149:224–232
Zhao M, Edward Suh G (2018) FPGA-based remote power side-channel attacks. In: 2018 IEEE symposium on security and privacy
Author information
Authors and Affiliations
Corresponding author
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
This article has been retracted. Please see the retraction notice for more detail:https://doi.org/10.1007/s12652-022-04236-7
About this article
Cite this article
Illuri, B., Jose, D. RETRACTED ARTICLE: Design and implementation of hybrid integration of cognitive learning and chaotic countermeasures for side channel attacks. J Ambient Intell Human Comput 12, 5427–5441 (2021). https://doi.org/10.1007/s12652-020-02030-x
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s12652-020-02030-x