Abstract
Due to Silicon (Si) material abundance and specific properties, monolithic integration of III-V semiconductors on (Si) is of paramount importance for the next-generation in Optoelectronic devises. An alternative approach to lattice mismatched single silicon crystal substrates for heteroepitaxy is proposed. In this work, we have suggested a design of a compliant virtual substrate and we have explored the modulation of stress/lattice parameter of a window layer based on porous silicon pseudo-substrates allowing a defect free epitaxial growth. We prepared a silicon window layer with low porosity and variable thicknesses whose stress is modulated by the succession of several layers with gradual porosity. As a result, we evaluated the stress and the lattice parameter in compliant substrate before and after thermal annealing. The pores reorganization process was supported in Argon atmosphere at constant temperature (900 °C). The samples were studied morphologically by Field Emission scanning Electron Microscope (FE-SEM) and structurally by High Resolution X-Ray Diffraction (HR-XRD) and Nano-Raman.
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Acknowledgements
We gratefully thank Ahmed Benmanaa, Technical Support Manager at LaboServices, for his contribution in HR-XRD analysis.
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- Imen Zeydi: Validation/ visualization/ writing -original draft/ writing-review and editing - Aicha Saidi: Investigation/Validation/ visualization/ writing -original draft/ writing-review and editing - Badreddine Smiri: Editing - Isabelle Berbezier: Resourses - Ridha Mghaieth: Supervision.
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Saidi, A., Zeydi, I., Smiri, B. et al. Stress Engineering of a Window Porous Silicon Layer based on Pseudo Substrate Suitable for III-V Monolithic Integration. Silicon 15, 6085–6097 (2023). https://doi.org/10.1007/s12633-023-02486-4
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DOI: https://doi.org/10.1007/s12633-023-02486-4