1 Introduction

Resistors, capacitors and inductors are the three well known fundamental elements of any electrical and electronic circuits. The fourth fundamental element “memristor” was hypothesized by Leon Chua in 1971 [1], and its generalized concept of memristive devices was reported in 1976 [2]. The memristor was just a concept until the realization of the first physical memristor using TiO2 by Stanley Williams and his group in 2008 [3]. Thereafter, researchers have shown interest towards the realisations of memristors and their extensive usage in different applications of electrical and electronics engineering. Memristor is now viewed as the element having memory inside it that remembers the past events and reflects the reminiscence in the form of changing its resistance. Therefore, the property of remembrance of memristor (memory and resistor) is extended to two more elements namely memcapacitor (memory and capacitor) and meminductor (memory and inductor) [4]. These three elements (memristor, memcapacitor and meminductor) that are commonly referred as memelements having memory storage properties and thus their performances are dependent on the history of the system [5]. Memelements possess interesting characteristics that can be utilized in many areas of science and engineering. Memristors are available commercially but meminductor and memcapacitor are not widely available thereby improvement in the performance of mem-elements is still needed. Researchers and engineers are continuously trying to mimic the properties of these memelements with the help of emulator and mutator circuits. Various mutator circuits that can convert memristors into meminductors and memcapacitors have been reported in the literature. The emulators of both memcapacitors and meminductors have been realized using one traditional voltage operational amplifier (OP-AMP), memristor, resistor and a grounded capacitor [6]. Single and double-outputs current conveyors based memcapacitor and meminductor have been realized using memristor, inductor, resistor and capacitor [7]. Another meminductor and memcapacitor emulators have been realized using two AD844 types current feedback operational amplifiers (CFOAs) [8], one memristor emulator, resistor and capacitor [9]. A floating memristor-less meminductor emulator has been designed that uses four current conveyors, three traditional voltage OP-AMPs, one multiplier, seven resistors and two capacitors [10]. Another charge controlled memristor-less meminductor emulator has been realized using three conventional OP-AMPs, multiplier, inductor, MOSFETs, resistors and capacitors [11]. A mutator based meminductor emulator has been reported using two current conveyors, three traditional voltage OP-AMPs, one buffer, seven resistors, two dependent current sources, one multiplier and two capacitors [12]. A floating meminductor emulator has been realized using one memristor emulator, one AD844 type CFOA, one traditional voltage OP-AMP, three resistors and a capacitor [13]. The mutator based on the SPICE model has been reported in [14], that converts memristor into meminductor. A universal mutator has been suggested using trans-impedance OP-AMPs, buffers, resistors and capacitors [15]. A memristor-less meminductor emulator has been realized using three second generation current conveyors, one analog multiplier, three resistors and two capacitors [16]. A floating meminductor emulator has been reported using voltage controlled transconductor, resistors and capacitors [17]. The gyrator based meminductor emulator has been reported that converts memristor into meminductor using two traditional voltage OP-AMPs, few resistors and a capacitor [18]. A mutator has been reported using four AD844 type CFOAs, one traditional voltage OP-AMP, varactor diode, few resistors and capacitors that transform memristor into meminductor and memcapacitor [19]. A universal mutator has been reported using off-the-shelf components such as AD844 type CFOAs, AD633 four quadrant analog multiplier [20], few resistors and capacitor for the implementation of memristor, meminductor and memcapacitor [21]. Memristor, meminductor and memcapacitor emulators have been designed using several OP-AMPs, multipliers, resistors and capacitors [22]. A voltage differencing transconductance amplifier (VDTA) based meminductor emulator has been reported in both grounded and floating configurations that employs two VDTAs, one multiplier and two capacitors [23]. Fractional order memristor, meminductor and memcapacitor emulators have been designed using second-generation current conveyor, differential-input double-output transconductance amplifier, balanced-output current conveyor, differential voltage current conveyor, analog multiplier, resistor and capacitor [24]. A simple realization of meminductor and memcapacitor emulator has been reported using a current backward transconductance amplifier and grounded capacitor [25]. A meminductor emulator has been reported using nine OP-AMPs, five multipliers, several resistors and two capacitors [26]. A floating flux controlled meminductor emulator has been designed that employs an OTA, three AD844s, an analog multiplier, one OP-AMP, eight resistors and two capacitors [27]. Operational amplifier based grounded meminductor emulators have been reported using a memristor, resistors and capacitors [28]. Other meminductor emulators using VDTA, CDBA and grounded capacitor have been realized in [29]. VDCC based floating meminductor emulator has been reported using memristor and capacitor [30].

It has been observed in the literature survey that meminductor emulator’s realizations fall under two categories. In the first category, meminductor emulators have been realized using a mutator circuit that transforms memristor emulators into meminductor emulator circuits. The main disadvantage of the first method is that the characteristics of meminductor emulators are dependent on the memristor emulators’ characteristics. Additionally, the resulting circuit of the meminductor emulator is complex due to the usage of memristor emulator. The second method is based on memristor-less design of meminductor emulators. Some circuits of meminductor and memcapacitor emulators have been reported in the literature without using memristor [6, 10,11,12,13, 16, 17, 19, 21,22,23, 26, 27]. But, analog multipliers or an excess number of active and passive components are used in many realizations that lead to complex circuitry [11,12,13, 15, 16, 21, 26, 27]. Therefore, the main aim of this paper is to design memristor-less and resistor-less grounded/floating meminductor emulators using less number of active and passive components without using mutator and multiplier. The proposed meminductor emulator circuit consists of operational transconductance amplifiers (OTA), current differencing buffered amplifier (CDBA) and a capacitor. The advantages of the proposed circuit are (1) simple realization, (2) grounded and floating configurations and (3) resistor-less, memristor-less and multiplier-less realization. The content of this paper is presented in eight sections including introduction. The review of memelement is described in section 2. The characteristics of OTA and CDBA are explained in section 3. Section 4 covers the mathematical analysis of the proposed grounded and floating meminductor emulators. Simulation results of the proposed meminductor emulators in grounded/floating configurations have been shown in section 5. Section 6 shows the comparison of the proposed meminductor emulators with the existing meminductor emulators. Section 7 covers the application of the proposed meminductor emulators. Conclusions are given in section 8.

2 Review of mem-elements

Memristor, memcapacitor and meminductor are commonly referred to as mem-elements. The behaviours of mem-elements depend on the history of the devices. Memristor, the first component of mem-element, provides relation between two circuit variables namely flux (ϕ) and charge (q). Flux (ϕ) is the time integral of applied voltage V (t) whereas charge (q) is the time integral of current I (t) as given in Eqs. (1) and (2). The other mem-element namely memcapacitor establish relation between circuit variable σ and flux (ϕ) whereas meminductor relates ρ and charge (q). The circuit variables σ and ρ are the time integrals of charge (q) and flux (ϕ), respectively as given in Eqs. (3) and (4). The memristor (MR) can be defined as the derivative of flux (ϕ) with respect to charge (q). Similarly, memcapacitor (Mc) is defined as derivative of σ with respect to flux (ϕ) whereas meminductor is defined as derivative of ρ with respect to charge (q). These relations are given in Eqs. (5), (6) and (7). The pinched hysteresis loops among q–ϕ, q–V and I–ϕ planes are plotted for memristor, memcapacitor and meminductor, respectively. The current-voltage relationships of memristor, memcapacitor and meminductor are given in Eqs. (8)–(10). The summary of inter-relations between mem-elements is shown in figure 1.

$$ {{\upvarphi }}\left( {\text{t}} \right) = \mathop \int \limits_{ - \infty }^{t} {\text{V }}\left( {\text{t}} \right)dt $$
(1)
$$ {\text{q}}\left( {\text{t}} \right) = \mathop \int \limits_{ - \infty }^{{\text{t}}} {\text{I}}\left( {\text{t}} \right){\text{dt}} $$
(2)
$$ \sigma \left( t \right) = \mathop \int \limits_{ - \infty }^{t} q\left( t \right)dt $$
(3)
$$ {\uprho }\left( {\text{t}} \right) = \mathop \int \limits_{ - \infty }^{{\text{t}}} {{\upvarphi }}\left( {\text{t}} \right){\text{dt}} $$
(4)
$$ M_{R} = \frac{d\phi \left( q \right)}{{dq}} $$
(5)
$$ M_{C} = \frac{d\sigma \left( \phi \right)}{{d\phi }} $$
(6)
$$ M_{L} = \frac{d\rho \left( q \right)}{{dq}} $$
(7)
$$ V\left( t \right) = M_{R} I\left( t \right) $$
(8)
$$ q\left( t \right) = M_{C} V\left( t \right) $$
(9)
$$ \phi \left( t \right) = M_{L} I\left( t \right) $$
(10)
Figure 1
figure 1

System defining the inter-relation between the mem-elements [31].

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3 Characteristics of voltage tunable OTAs and CDBA

The symbol of voltage tunable OTA is shown in figure 2. The input voltages \({\text{V}}_{1}\) and \({\text{V}}_{2}\) are applied to the input terminals of OTA that are converted into two output currents (\({\text{I}}_{{{\text{X}} + }}\) and \( {\text{I}}_{{{\text{X}} - }}\)) by the transconductance gain (\({\text{G}}_{{\text{m}}}\)) as given in Eq. (11). The transconductance gain (\({\text{G}}_{{\text{m}}}\)) of voltage tunable OTA depends upon the value of biasing voltage (\({\text{V}}_{{\text{B}}}\)) as given in Eq. (12) where µn is the mobility of electron, Cox is the gate-oxide capacitance and W/L is the aspect ratios of MOSFETs. The CMOS implementation of OTA is shown in figure 3 where biasing current (IB) of differential pair MOSFETs (M1 and M2) is provided with the help of MOSFETs M5, M6 and M7. The value of voltage (VB) applied at the gate terminal of MOSFET M7 is changed in order to change the value of transconductance gain (Gm).

$$ I_{X \pm } = \pm G_{m} \left( {V_{in + } - V_{in - } } \right) $$
(11)
$$ G_{m} = \frac{{\mu_{n} C_{ox} \frac{W}{L}}}{\sqrt 2 }\left( {V_{B} - V_{SS} - 2V_{th} } \right) $$
(12)
Figure 2
figure 2

Symbol representation of OTA [32].

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Figure 3
figure 3

CMOS implementation of operational transconductance amplifier.

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The active block, namely current differencing buffered amplifier (CDBA) has four terminals out of which “P” and “N” are low impedance input terminals whereas “W” and “Z” are output terminals as shown in figure 4. The input currents (IP and IN) are applied to “P” and “N” terminals of CDBA and the difference of these currents are conveyed at the “Z” terminal. The voltage across the “Z” terminal of CDBA is copied to the “W” terminal. The terminal characteristics of CDBA are given in Eq. (13). The circuit diagram of CDBA is shown in figure 5.

$$ V_{p} = 0,V_{N} = 0,I_{Z = } I_{P } - I_{N } ,V_{W} = V_{Z} $$
(13)
Figure 4
figure 4

Symbolic representation of CDBA [33].

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Figure 5
figure 5

CMOS implementation of CDBA.

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4 Proposed grounded and floating decremental/incremental meminductor emulator

The proposed grounded decremental/incremental meminductor emulator using OTAs and CDBA is shown in figure 6. In figure 6, input terminals “+” and “−” of OTA-1 are connected to the output terminals “X2−” and “X2+” of OTA-2, respectively. The output terminal “X1−”of OTA-1 is shortened to input terminal “+” of OTA-2 and is connected to capacitor C1. The other input terminal “−”of OTA-2 is grounded. The bias voltage “VB” is connected to the “W” terminal whereas the bias voltage “VB1” of CDBA is set to −0.1 V. The current “IX1+” of OTA-1 is given to the “P” terminal of CDBA that result in decremental meminductor emulator whereas incremental meminductor is realized if the current “IX1+” of OTA-1 is given to “N”. terminal of CDBA.

Figure 6
figure 6

Proposed grounded meminductor emulator.

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Capacitor C2 is connected to the “Z” terminal of CDBA. The voltage across the “Z” terminal of CDBA is copied to the “W” terminal of CDBA that is connected to biasing voltage “VB” of OTAs. The voltage “Vw” controls the transconductances (gm1 and gm2) of OTAs. The output current “IX1+” of OTA-1 is passed through the “P” or “N’ terminal of CDBA. CDBA transfers the applied input current (IX1+) to “Z” terminal either in the same or opposite direction and finally capacitor C2 gets charged. The same voltage is copied to the “W” terminal of CDBA that controls the value of meminductance by controlling the transconductance gains (gm1 and gm2) of OTAs. The value of meminductance (ML) depends on the value of transconductances of OTAs. Thereby, the value of meminductance is controlled according to the previous history i.e., charge stored in capacitor C2 of the circuit and the meminductor property is obtained. A pinched hysteresis loop has been achieved that validates the proposed configuration as a decremental or incremental meminductor emulator.

The routine analysis of the proposed grounded decremental meminductor emulator is as follows:

$$ I_{X1 + } = G_{m1} V_{in} $$
(14)
$$ I_{X1 - } = - G_{m1} V_{in} $$
(15)
$$ I_{X2 - } = I_{in} = G_{m2} V_{in2 + } $$
(16)

where Vin2+ is voltage across capacitor C1 that can be written as

$$ V_{in2 + } = \frac{1}{{C_{1} }}\int I_{X1 - } dt $$
(17)

Substituting the value of \(I_{X1 - }\) from Eq. (11) into Eq. (17) results in the same equation as in [23]

$$ V_{in2 + } = \frac{1}{{C_{1} }}\int - G_{m1} V_{in} dt $$
(18)
$$ V_{in2 + } = - \frac{1}{{C_{1} }}G_{m1} \varphi \left( t \right) $$
(19)

where \(\int V_{in} dt\) = \(\varphi \left( t \right)\) is the flux generated in meminductor emulator.

With the help of Eqs. (16) and (19), the value of input current (Iin) is obtaines as in [23]

$$ I_{in} = - \frac{{G_{m1} G_{m2} }}{{C_{1} }}{ }\varphi \left( t \right) $$
(20)

Bias voltages (VB) of both OTAs are the same as can be seen from figure 6. Therefore, the transconductances (Gm1 and Gm2) of both OTAs are equal.

Substituting Gm1 = Gm2 = Gm into Eq. (20) result into

$$ I_{in} = - \frac{{G_{m}^{2} }}{{C_{1} }}{ }\varphi \left( t \right) $$
(21)

The relation between flux Φ (t) and current I (t) is given by

$$ I\left( t \right) = M_{L}^{ - 1} \varphi \left( t \right) $$
(22)

Therefore, after comparing Eqs. (21) and (22), the value of inverse meminductance is obtained as

$$ M_{L}^{ - 1} = - \frac{{G_{m}^{2} }}{{C_{1} }} $$
(23)

Rearranging Eq. (23) will result in the value of meminductance as

$$ M_{L} = - \frac{{C_{1} }}{{G_{m}^{2} }} $$
(24)

The voltage across capacitor (C2) that is connected to “Z” terminal of CDBA can be written as

$$ V_{Z} = \frac{1}{{C_{2} }}\int I_{z} \left( t \right)dt $$
(25)

From the terminal equations of CDBA, the value of current (Iz) can be easily obtained as

$$ I_{Z} \left( t \right) = I_{P} = I_{X1 + } = G_{m} V_{in} $$
(26)

Substituting the value of current Iz (t) from Eq. (26) into Eq. (25), we get

$$ V_{Z} = \frac{1}{{C_{2} }}\int G_{m} V_{in} dt $$
(27)

The voltage Vz is copied to the “W” terminal of CDBA by an internal buffer. Thus, the voltage Vw can be written as

$$ V_{W} = V_{B} = \frac{1}{{C_{2} }}\int G_{m} V_{in} dt = \frac{{G_{m} }}{{C_{2} }}\varphi_{in} $$
(28)

Substituting the value of bias voltage VB from Eq. (28) to Eq. (12) results in

$$ G_{m} = \frac{{ - \frac{{\mu_{n} C_{ox} }}{\sqrt 2 }\left( {V_{SS} + 2V_{th} } \right)}}{{1 - \frac{{\mu_{n} C_{ox} }}{\sqrt 2 }\frac{{\varphi_{in} }}{{C_{2} }}}} $$
(29)

Substituting the value of Gm from Eq. (29) into Eq. (23), we get

$$ M_{L}^{ - 1} = - \frac{{\left[ {\frac{{ - \frac{{\mu_{n} C_{ox} }}{\sqrt 2 }\left( {V_{SS} + 2V_{th} } \right)}}{{1 - \frac{{\mu_{n} C_{ox} }}{\sqrt 2 }\frac{{\varphi_{in} }}{{C_{2} }}}}} \right]^{2} }}{{C_{1} }} $$
(30)

After simplifying Eq. (30) the value of meminductance (ML) is obtained as

$$ M_{L} = - \frac{{C_{1} \left[ {1 - \frac{{\mu_{n} C_{ox} }}{\sqrt 2 }\frac{{\varphi_{in} }}{{C_{2} }}} \right]^{2} }}{{\frac{{\left( {\mu_{n} C_{ox} } \right)^{2} }}{2}\left( {V_{SS} + 2V_{th} } \right)^{2} }} $$
(31)

Rearranging the terms of Eq. (31) results in the value of meminductance (ML) for decremental meminductor as

$$ M_{L} = - \frac{{2C_{1} }}{{\begin{array}{*{20}c} {\left( {\mu_{n} C_{ox} } \right)^{2} \left( {V_{SS} + 2V_{th} } \right)^{2} } \\ { \leftarrow {\text{Fixed}}\;{\text{part}} \to } \\ \end{array} }} - \frac{{2C_{1} \varphi_{in} \left[ {\frac{{\mu_{n} C_{ox} \varphi_{in} }}{{2C_{2} }} - \sqrt 2 } \right]}}{{\begin{array}{*{20}c} {\mu_{n} C_{ox} C_{2} \left( {V_{SS} + 2V_{th} } \right)^{2} } \\ { \leftarrow {\text{Variable}}\;{\text{part}} \to } \\ \end{array} }} $$
(32)

Similarly, after interchanging the connections at input terminals of CDBA from “p” to “n” the value of meminductance (ML) for incremental meminductor is obtained as

$$ M_{L} = \frac{{2C_{1} }}{{\begin{array}{*{20}c} {\left( {\mu_{n} C_{ox} } \right)^{2} \left( {V_{SS} + 2V_{th} } \right)^{2} } \\ { \leftarrow {\text{Fixed}}\;{\text{part}} \to } \\ \end{array} }} + \frac{{2C_{1} \varphi_{in} \left[ {\frac{{\mu_{n} C_{ox} \varphi_{in} }}{{2C_{2} }} - \sqrt 2 } \right]}}{{\begin{array}{*{20}c} {\mu_{n} C_{ox} C_{2} \left( {V_{SS} + 2V_{th} } \right)^{2} } \\ { \leftarrow {\text{Variable}}\;{\text{part}} \to } \\ \end{array} }} $$
(33)

It can be concluded from the Eqs. (32) and (33) that the first term of meminductance remains constant whereas the second term is variable due to its dependence on flux (ϕin). Both the terms of Eq. (32) are negative while both terms of Eq. (33) are positive and thereby represent the meminductances (ML) of decremental and incremental meminductor emulators, respectively.

The proposed floating decremental/incremental meminductor emulator using OTAs and CDBA is shown in figure 7. Connections of figure 7 are similar to the connections of figure 6 with only one difference in the applied voltages “Vin+” and “Vin−” at both the terminals (positive and negative) of OTAs, respectively. In the proposed emulator of figure 6, the negative terminal of OTA-1 is grounded while in figure 7 of the proposed floating meminductor emulator it is kept at voltage “Vin−”. Therefore, the meminductances (ML) derived in Eqs. (32) and (33) are equally valid for the proposed floating meminductor (ML) emulator of figure 7.

Figure 7
figure 7

Proposed floating meminductor emulaor

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5 Simulation results

Simulation results have been obtained for the proposed meminductor emulators by Mentor Graphics Eldo Simulation tool using

180 nm CMOS technology parameters. The voltage supply VDD = −VSS = 0.9 V. The biasing voltage (VB1) is set to -0.1V. The values of capacitors C1 and C2 are chosen as 20 pF and 40 pF, respectively. The values of current sources (IB1 and IB2) used in the design of CDBA are 20 µA.

5.1 Selection of aspect ratios (W/L) of MOSFETs for the design of OTA and CDBA on the basis of inversion coefficient

The operational transconductance amplifier (OTA) used in the design of meminductor emulator is shown in figure 8 with values of aspect ratios (W/L) and inversion coefficients (IC) for each MOSFET. The bias current (2IB) of differential pair MOSFETs of OTA is selected as 100 μA. The OTA shown in figure 8 is balanced and symmetrical and therefore bias current (IB) can be assumed equal in all branches i.e. 50 μA. The design steps of OTA are presented here on the basis of inversion coefficient (IC) [34]. The inversion coefficient (IC) is expressed as

$$ IC = \frac{{I_{D} }}{{I_{0} \left( \frac{W}{L} \right)}} $$
(34)

where ID is the drain current of MOSFET, I0 is the technology current that remains almost fixed (0.064103 μA for 0.18 μm technology) for a particular technology and W/L is the aspect ratio of the MOSFET. The range of inversion coefficients (IC) are represented in figure 9 for the MOSFETs operating in saturation regions with several trade-offs [34]. The aspect ratios (W/L) of each MOSFETs of OTA are appropriately selected such that the inversion coefficient (IC) of each MOSFET remains in the range of strong inversion. The lengths of MOSFETs are chosen large enough to avoid the several adverse effects that generally occur in strong inversion region.

Figure 8
figure 8

Circuit diagram of OTA with aspect ratios and inversion coefficient of MOSFETs.

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Figure 9
figure 9

The inversion coefficient for different regions and sub-regions of MOSFETs with corresponding performance trade-offs [34].

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The circuit diagram of CDBA with aspect ratios (W/L) and inversion coefficients (IC) of each MOSFET is represented in figure 10. It can be seen that aspect ratios and bias currents (IB) are chosen such that their inversion coefficients (IC) lie in the range of moderate or strong inversion for the MOS transistors of CDBA.

Figure 10
figure 10

Circuit diagram of CDBA with aspect ratios and inversion coefficient of MOSFET.

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The summary of aspect ratios of MOSFETs is shown in Table 1.

Table 1 MOSFET ratio of OTA and CDBA.
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5.2 Proposed grounded decremental/incremental meminductor emulator

The transient analysis of the proposed grounded decremental meminductor emulator has been obtained by applying an input sinusoidal signal of amplitude 100 mV and frequency 100 KHz as shown in figure 11. The pinched hysteresis loops (PHLs) between flux and current of the proposed grounded decremental meminductor emulators have also been obtained by applying a sinusoidal signal having amplitude of 100 mV for different frequencies lies in the range of 30 KHz to 2 MHz as shown in figures 12(a)–(g). The pinched hysteresis loops of the proposed grounded incremental meminductor emulators have also been shown for different frequencies lie in the range of 30 KHz to 2 MHz as shown in figures 13(a)–(g).

Figure 11
figure 11

Transient response of proposed grounded decremental meminductor emulator.

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Figure 12
figure 12

PHLs of proposed grounded decremental meminductor emulator for different frequencies (a) 30 kHz, (b) 50 kHz, (c) 100 kHz, (d) 500 kHz, (e) 800 kHz, (f) 1MHz and (g) 2 MHz

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Figure 13
figure 13

PHLs of the proposed grounded incremental meminductor emulator for different frequencies (a) 30 kHz, (b) 50 kHz, (c) 100 kHz, (d) 500 kHz, (e) 800 kHz, (f) 1MHz and (g) 2 MHz.

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5.3 Proposed floating decremental/incremental meminductor emulator

The transient analysis of the proposed floating meminductor emulator has been obtained by applying a sinusoidal voltage of amplitude 200 mV and frequency 100 KHz as shown in figure 14. The pinched hysteresis loop has also been obtained for the frequencies lie in the range of 30 KHz–2 MHz frequencies as shown in figure 15. The pinched hysteresis loops for floating incremental meminductor emulators are shown in figure 16.

Figure 14
figure 14

Transient analysis of the proposed floating meminductor emulator.

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Figure 15
figure 15

PHLs of the proposed floating decremental meminductor emulator for different frequencies (a) 30 kHz, (b) 50 kHz, (c) 100 kHz, (d) 500 kHz, (e) 800 kHz, (f) 1MHz and (g) 2 MHz.

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Figure 16
figure 16

PHLs of proposed floating incremental meminductor emulator for different frequencies (a) 30 kHz, (b) 50 kHz, (c) 100 kHz, (d) 500 kHz, (e) 800 kHz, (f) 1MHz and (g) 2 MHz

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5.4 Temperature analysis

The temperature analysis has been done for both proposed grounded and floating decremental meminductor emulators after applying an input sinusoidal signal of amplitude 100 mV and frequency of 50 KHz while the temperature is varied from −10 to 40°C. This analysis verifies that pinched hysteresis loops are not deformed even after variation in temperature as shown in figure 17 and thereby the proposed circuits are satisfactorily working for different temperatures.

Figure 17
figure 17

Temperature analysis of the proposed meminductor emulators (a) grounded and (b) floating.

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5.5 Monte Carlo analysis of proposed grounded and floating decremental/incremental meminductor emulators

The Monte Carlo analysis has been performed for the proposed meminductor emulators at a frequency of 50 KHz for the 200 runs to check the robustness of the proposed designs. The gaussian random variations have been given for the variation in threshold voltages, aspect ratios of MOSFETs and in device capacitances. The pinched hysteresis loops for proposed meminductor emulators have been shown in figure 18 and 19 that confirms that the pinched hysteresis loops cross at zero for various cycles and converse flawlessly.

Figure 18
figure 18

Monte Carlo analysis of the proposed grounded meminductor emulator (a) decremental and (b) incremental.

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Figure 19
figure 19

Monte Carlo analysis of proposed floating meminductor emulator (a) decremental and (b) incremental.

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5.6 Shifting of pinched point at higher frequencies

The shifting of pinched points along the X-axis is clearly observed at higher frequencies from figures 12, 13, 15 and 16. The shifting of pinched points can be avoided with proper scaling of values of capacitors with frequency. The pinched hysteresis loops obtained from the simulation results of the proposed meminductor emulators depend on the product of angular frequency and value of capacitor (ωC). The pinched point gets shifted from the origin when frequency is increased without scaling the values of capacitors. To maintain the pinched point, the values of capacitors need to be scaled properly with increase in frequency. The pinched hysteresis plots after varying the values of capacitors for different operating frequencies have now been shown in figure 20 to show the effect. It is observed from the simulation results that keeping the product of angular frequency and capacitor constant, the shifting of pinched points in the hysteresis loop at higher frequencies may be avoided.

Figure 20
figure 20

Pinched hysteresis curves for different values of capacitors (a) 30 kHz, (b) 50 kHz, (c) 100 kHz, (d) 500 kHz, (e) 800 kHz, (f) 1 MHz and (g) 2 MHz.

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5.7 Effect of changing the bias voltages and currents on the pinched hysteresis loops

The pinched hysteresis loops for different bias voltages and currents are presented in figures 21(a)–(b). It is observed from figures that the proposed meminductor emulator maintains the hysteresis loops after varying the supply voltages and bias currents. This verifies the robustness of the proposed meminductor emulator.

Figure 21
figure 21

Pinched hysteresis curves with (a) varying bias voltages and (b) varying bias currents.

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6 Comparison of the proposed meminductor emulators with other meminductor emulators reported in literature

The comparison of the proposed meminductor emulators with other meminductor emulators has been given in Table 2.

Table 2 Comparison of proposed meminductor emulators with existing meminductor emulators.
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The comparison has been done in terms of number of active/passive components, operating frequency range, power supply and type of realizations. The conclusion of Table 2 is as follows.

  1. (1)

    Most meminductor emulators reported in the literature are not electronically tunable but the proposed meminductor emulators are electronically tunable.

  2. (2)

    The meminductor emulators reported in [6, 7, 9, 12, 13, 15, 19,20,21, 24] employ mutator circuit or memristor emulator for the implementation of meminductor emulator. However, the proposed meminductor emulators are memristor-less.

  3. (3)

    In the meminductor emulators reported in [6, 7, 9,10,11,12, 15,16,17, 19,20,21, 24,25,26] use more number of active and passive components to realize meminductor emulator while the proposed meminductor emulator uses only two active and two passive component.

  4. (4)

    Analog multiplier has been used in the realization of meminductor emulators reported in [6, 11,12,13, 15, 16, 25, 26] whereas the proposed meminductor emulator has been designed without using a multiplier.

  5. (5)

    Almost all meminductor emulators reported in the literature use one or more resistors and capacitors as passive components; however, the proposed meminductor emulator is resistor-less and uses only two capacitors as passive components.

  6. (6)

    The operating frequency range of all meminductor emulators are very less in the Hz and kHz range but the proposed meminductor emulator works satisfactorily in MHz.

7 Application of the proposed meminductor emulator in adaptive learning circuit

To verify the performance of the proposed meminductor emulator, an adaptive learning circuit [35,36,37,38] has been realized as shown in figure 22. The proposed meminductor (ML) emulator circuit is connected in series with resistance (R) and capacitor (C). Mem-inductor remembers the past events and its performance is also dependent on the history of the circuit. To verify the property of remembrance, a piecewise linear (PWL) signal is applied to the input of the adaptive learning circuit realized in figure 22. The circuit first learns the pattern of PWL. It remembers the past input and tries to predict the pattern quickly. The same can be verified from the output (Vout) of figure 23 that it takes slightly more time to follow the first pulse but after learning the behavior of input pulse, it quickly follows the second and third pulses of the input. Fourth pulse is applied after some interval to verify the remembrance. It can also be verified that the circuit designed using meminductor is able to follow the fourth pulse that is applied after an irregular interval. The circuit behavior is analogous to amoeba’s learning (amoeba first learns and then acts on the basis of past events). To understand the analogy with amoeba, input voltage (Vin) can be considered as temperature that controls the amoeba’s motion. Output voltage (Vout) across the capacitor represents the locomotive speed of amoeba with respect to temperature variations. The variations in the locomotive speed (Vout) are according to environmental changes (Vin). It is clearly seen that if temperature (corresponds to Vin) slows down the voltage (Vout) corresponds to locomotive speed also falls down. The future temperature drops are predicted from the past occurrence drop which verifies the adaptive learning process steps of amoeba. The components values in the adaptive learning circuit are chosen as follows: R = 2 KΩ, C = 50 nF and the meminductor emulator component C1 = 20 pF and C2 = 40 pF.

Figure 22
figure 22

Adaptive learning circuit based on the proposed meminductor emulators.

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Figure 23
figure 23

Response of adaptive learning circuit.

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8 Conclusions

Grounded and floating memristor-less and resistor-less decremental/incremental meminductor emulators have been proposed using two OTAs, one current differencing buffered amplifier and two grounded capacitors. The performances of the proposed meminductor emulators are found to be satisfactory for a wide range of frequencies. Temperature analysis and Monte Carlo analysis also satisfy the robustness of the proposed emulators. The performance of the proposed emulators has also been compared with other meminductor emulators reported in the literature. An adaptive learning circuit has also been realized to check the worthiness of the proposed meminductor emulators.