Introduction

In recent years, AlGaN/GaN heterostructure-based power devices have attracted considerable attention due to the wide band gap and high critical field of GaN,1 its high electron mobility in the two-dimensional electron gas (2DEG) channel,2,3,4 and the low-cost fabrication of III-N epitaxy on silicon substrate.5 Therefore, AlGaN/GaN heterostructure field-effect transistors (HFETs) can operate at a high switching frequency (>1 MHz),6 to reduce the volume of energy storage devices such as inductors and capacitors,7,8 and miniaturize the power supply modules.9 AlGaN/GaN HFETs are already widely used in power supplies, electric vehicles, and fast chargers in consumer electronics.10,11,12 The P-GaN gate AlGaN/GaN HFET (PG-HFET) is a typical commercial GaN power device, which can realize enhanced-mode operation by a simple and controllable fabrication process.8 However, PG-HFETs often suffer from the concentration of the electric field (E-field) at the gate edge, which may cause a premature breakdown.13

Many recent research efforts have focused on improving the breakdown voltage (BV) of the PG-HFET using various approaches, including metal field plates,14,15 junction or P-type field plates,16 stripe array gates, and17 alternate-island drains.18 All these methods can smooth the E-field distribution along the channel and significantly improve the BV. However, these device structures often have a long drift region between the gate and the drain to withstand high voltages, resulting in relatively high on-resistance (Ron). Therefore, improving the on-state performance of the high-voltage PG-HFET is essential.

The double REduced SURface Field (RESURF) structure is a widely used technology in high-voltage lateral diffusion metal–oxide–semiconductor field-effect transistors (LDMOSFET).19 The double RESURF structure has a lateral N drift region that defines the Ron of the device and a vertical PNP structure which supports a space-charge depletion region enabling high breakdown voltage.20 Compared to the single RESURF structure with a vertical PN junction, the double RESURF structure with a more highly doped N-drift region shows lower on-resistance under the same breakdown voltage.

In this work, we propose a double RESURF P-GaN gate AlGaN/GaN HFET with a partial N-GaN (DR-HFET) channel to improve the BV and the Ron of the PG-HFETs. The partial N-GaN channel between the gate and the drain results in a remarkable reduction in the Ron by increasing the electron density in the channel layer. The P-top layer and the P-buffer layer modulate the distribution of the E-field along the N-type GaN channel to achieve a high breakdown voltage. After validation of the simulation models and parameters, the optimum DR-HFET achieves a BV of 1100 V and Ron of 5.5 Ω mm, while the PG-HFETs produce a BV of 600 V and Ron of 10.8 Ω mm under the same gate-to-drain distance of 6 μm. We then discuss the influence of the AlGaN/GaN quality on the performance of the DR-HFETs. When the quality of the AlGaN/GaN epitaxial layer is improved, the relative reduction of Ron decreases from 53% to 40%, and the relative increase in BFOM decreases from 6.1 times to 4.6 times. The simulation results indicate that the double RESURF structure may be less effective in the high-quality AlGaN/GaN epitaxial layer. Finally, we propose a series of fabrication steps for the DR-HFET, in which the fabrication of DR-HFETs may have more steps than that of PG-HFETs.

Device Structures, Simulation Models and Mechanism

Device Structures

The structures of the PG-HFET and the proposed DR-HFET are shown schematically in Fig. 1. The structure parameters of the PG-HFET are consistent with reported results.21 For vertical epitaxial layers, both structures are composed of a 2.6-μm-thick GaN buffer layer, a 300-nm GaN channel layer, and a 12.5-nm AlGaN barrier layer with 25% Al content. The gate stack is formed by an 80-nm-thick P-type GaN layer with a hole concentration of 1 × 1018 cm−3. The Si3N4 passivation layer with a thickness of 500 nm is located on the top of the devices.

Fig. 1
figure 1

Device structures of (a) PG-HFETs, (b) DR-HFETs.

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For the lateral structure parameters, both HFETs have a source and drain length (LC) of 1 μm. The gate length (LG) is set as 0.8 μm. The gate-to-source distance (LGS) and gate-to-drain distance (LGD) of the devices are defined as 0.75 and 6 μm, respectively. As shown in Fig. 1b, the proposed DR-HFETs have a P-AlGaN top layer, a partially doped N-GaN channel layer between the gate and the drain, and a P-type GaN buffer layer to form a double RESURF structure. All the structure parameters are given in Table I.

Table I Simulated device specifications
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Simulation Models and Validation

The technology computer-aided design (TCAD) simulation was conducted using the Shockley–Read–Hall (SRH) model to calculate the carrier generation and recombination, and the carrier in the simulated devices obey Fermi–Dirac statistics. The high field mobility and the polarization model of the III-N materials was adopted with default parameter values from the Silvaco ATLAS TCAD tool.22,23 Acceptor-like traps of 0.59 eV under the conduction band were added into the buffer layer of the PG-HFET with density of 1 × 1016 cm−3.24

The Selberherr impact ionization model was used to emulate the breakdown characteristics of the GaN-based electronic devices.25 The impact ionization coefficients for electrons (αn) and holes (αp) are based upon the following expressions.

$$ \alpha_{{\text{n}}} = a_{{\text{n}}} \exp \left[ { - \left( {\frac{{b_{{\text{n}}} }}{E}} \right)^{m} } \right], $$
(1)
$$ \alpha_{{\text{p}}} = a_{{\text{p}}} \exp \left[ { - \left( {\frac{{b_{{\text{p}}} }}{E}} \right)^{m} } \right], $$
(2)

where E is the electric field in the direction of current flow at a particular position in the structure, and an, ap, bn, bp, m are parameters. The parameters were set as an = ap = 1.1438 × 107 cm−1, bn = bp = 23.8933 MV/cm and m = 1.26

The Lombardi mobility model was conducted as the low field mobility model in the simulation.27 In the Lombardi mobility model, the electron mobility is limited by the surface acoustic phonon scattering mobility μac, doping-dependent bulk carrier mobility μb and interface roughness scattering μint. The total electron mobility μn was calculated using Matthiessen’s rule.

$$ \frac{1}{{\mu_{{\text{n}}} }} = \frac{1}{{\mu_{{{\text{ac}}}} }} + \frac{1}{{\mu_{{\text{b}}} }} + \frac{1}{{\mu_{{\text{int}}} }}, $$
(3)
$$ \mu_{{{\text{ac}}}} = \left( {B\frac{T}{{E_{ \bot } }} + C\frac{1}{{E_{ \bot }^{1/3} }}} \right)\frac{1}{T}, $$
(4)
$$ \mu_{{\text{b}}} = \mu_{0} + \frac{{\mu_{\max } - \mu_{0} }}{{1 + \left( {N/C_{{\text{r}}} } \right)^{\alpha 1} }}, $$
(5)
$$ \mu_{{\text{int}}} = \frac{\delta }{{E_{ \bot }^{2} }}, $$
(6)

where E⊥ is the transverse field, T is the temperature, μmax is the Hall mobility at room temperature, N is the impurity concentration of the semiconductor, and B, C, μ0, Cr, α1, δ are fitting parameters. The values of μ0, Cr and μmax are defined based upon other research results.28,29,30 We tuned the parameters of B, C, α1 and δ to fit the experimental results reported by Li et al.21. The parameters used in the Lombardi mobility model are listed in Table II.

Table II Parameters for μac, μb, and μint in the mobility model
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The validation of our simulation was conducted by comparison of the simulation curve and the experimental data for PG-HFETs reported by Li et al.21 The validation results are illustrated in Fig. 2. The PG-HFET has a threshold voltage VTH of 1.6 V, a linear area current Idlin of 9.3 mA/mm and a BV of 600 V. The method for calculating Ron is to divide the VDS by the Idlin current. During the transfer curves simulation, the VDS was set as 0.1 V, and the Ron was obtained as 10.8 Ω mm. These simulation results match the characteristics of the experimental results reported by Li et al.21 As shown in Fig. 2, the output (Fig. 2a), transfer (Fig. 2b), and off-state (Fig. 2c) characteristics of the PG-HFET are basically consistent with the experimental results.

Fig. 2
figure 2

Simulation validation by comparison of the experimental curves of (a) output (b) transfer (c) off-state characteristics.

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Device Mechanism

The electron density and band diagram at x = 4 μm for the PG-HFETs, the PG-HFETs with only N-GaN channels (NC-HFET) and the DR-HFETs are compared and discussed in Fig. 3 under thermal equilibrium conditions. As shown in Fig. 3a, the NC-HFET and DR-HFET have partial N-GaN channels with an electron concentration Nch of 8 × 1017 cm−3, which is placed between the gate and the drain; thus the channel electron density in the NC-HFET and DR-HFET become much higher than that of the PG-HFET. For the DR-HFET, the P-top layer induces a decrease in 2DEG density, and the P-buffer layer can extend the depletion region in the channel layer. Therefore, DR-HFETs may have a lower Ron than PG-HFET but a higher Ron than NC-HFET. In Fig. 3b, it is obvious that the DR-HFETs have the highest electron barrier in the buffer layer due to a concentration of 6.2 × 1016 cm−3 acceptors in the P-GaN buffer, and thus DR-HFETs may show low leakage current.

Fig. 3
figure 3

(a) Electron density and (b) band diagram of the PG-HFET, NC-HFET and DR-HFET with a Tch of 300 nm in thermal equilibrium.

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Figure 4 illustrates the results of our in-depth research on the relationship between the structural parameters of the N-GaN channel and Ron in the NC-HFETs. When the Nch and the Tch of the N-GaN channel increase, the Ron decreases monotonically. When Ron is lower than ~ 4 Ω mm, a larger change in Nch or Tch has a relatively smaller impact on the Ron, and it is inefficient to reduce Ron by increasing the Nch or Tch of the N-GaN channel. Therefore, the benefit threshold of Ron is obtained as 4 Ω mm, and we choose Tch = 400 nm, Nch = 8 × 1017 cm−3 as the optimum value of the N-GaN channel.

Fig. 4
figure 4

The Tch and Nch dependence of the Ron in the NC-HFET.

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In Fig. 4, the Ron of the PG-HFET can be expressed as

$$ R_{{{\text{on}}}} = R_{{\text{S}}} + R_{{\text{D}}} + R_{{{\text{SG}}}} + R_{{{\text{UG}}}} + R_{{{\text{GD}}}}, $$
(7)

where RS and RD are the resistance between the metal contacts and the 2DEG channel, RSG and RGD are the access region resistance, and RUG is the channel resistance under the gate. Although increasing Tch and Nch can reduce the RGD, Ron is limited to ~ 2.5 Ω mm, where the sum of RS, RD, RSG and RUG become the main part of the Ron in the NC-HFETs.

Results and Discussion

Device Characteristics and Optimization

The DC characteristics of the PG-HFETs, NC-HFETs and DR-HFETs are illustrated in Fig. 5. DR-HFETs and PG-HFETs have a Tch of 400 nm, a Nch of 8 × 1017 cm−3. According to the charge balance principle of the RESURF structure, the DR-HFETs are optimized and have a total charge density in P-top layer Qtp of 2.6 × 1013 cm−2 (Npt = 5.2 × 1017 cm−3, Tpt = 500 nm), and a total charge density in P-GaN buffer layer Qbuf of 1.6 × 1013 cm−2 (Nbuf = 6.2 × 1016 cm−3, Tbuf = 2.6 μm).

Fig. 5
figure 5

The DC characteristics of PG-HFETs, NC-HFETs and DR-HFETs: (a) output curves, (b) transfer curves.

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Facilitated by the high electron density in the N-GaN channel, the NC-HFET and DR-HFET show a higher saturation current Idsat and a lower Ron than that of PG-HFET. As shown in Fig. 5a, owing to the electron depletion caused by the P-top and P-buffer layer, a degradation of on-state performance can be observed in the DR-HFET. In Fig. 5b, the Ron is extracted by the transfer characteristic at VDS = 0.1 V. The Ron of the NC-HFET is achieved as ~ 4 Ω mm, which is the benefit threshold value mentioned in above section. Then, the DR-HFET have a Ron of 5.5 Ω mm, which is 50.9% that of PG-HFET, indicated that double RESURF structure can significantly reduce the Ron. As shown in Fig. 5b, the threshold voltage VTH of the PG-HFET and NC-HFET is 1.6 V with non-doped GaN buffers, while the VTH of the DR-HFET becomes 1.7 V due to the P-type doping in the buffer layer.

The off-state breakdown characteristics of PG-HFETs, NC-HFETs and DR-HFETs are compared at VGS = 0 V in Fig. 6. The BV is extracted when the reverse leakage current reaches 1 μA/mm. The on-state and off-state simulations have identical structural parameters. As shown in Fig. 6a, the DR-HFETs show a BV of 1100 V, while the PG-HFETs have a BV of 600 V. Compared to the PG-HFETs and NC-HFETs, the DR-HFETs display reverse leakage current of ~ 10−6 mA/mm at VDS = 600 V, which indicates that the P-GaN buffer can effectively suppress the leakage currents. The E-field distribution along the channel at y = 13 nm is shown in Fig. 6b. When breakdown occurs, all devices have the maximum E-field strength of ~ 3.4 MV/cm. It is clearly shown that the E-field distribution of the DR-HFET spread more uniformly than that of the PG-HFETs and the NC-HFETs; thus, the DR-HFETs have the highest BV of 1100 V among all three kinds of HFETs.

Fig. 6
figure 6

(a) The BV curves, (b) the E-field distribution along the channel of the PG-HFETs, NC-HFETs and DR-HFETs at the BV.

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The potential distributions of PG-HFET and the proposed DR-HFET at VDS = 600 V are shown in Fig. 7. For the PG-HFET in Fig. 7a, the potential contours are closely packed at the gate edge due to the incomplete depletion of the gate-to-drain access region, which suggests the crowding of the electric field lines at the gate edge. As shown in Fig. 7b, the potential distribution of the DR-HFETs is more uniform than that of the PG-HFETs. It can be observed that the potential contours are relatively concentrated at the gate edge and the P-top edge. Therefore, two electric field peaks at these edges can also be found in the E-field distribution of the DR-HFETs in Fig. 6b.

Fig. 7
figure 7

Potential distribution at VDS = 600 V: (a) PG-HFETs, (b) DR-HFETs.

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In Figs. 8 and 9, we optimize the structure parameters of the DR-HFETs. The optimization of hole concentration Np in the P-top layer is shown in Fig. 8a. It should be noted that the optimization of Np is in accordance with the charge balance principle. Once a value of Np is defined, the hole concentration of the P-buffer layer Nbuf can be expressed as

$$ N_{{{\text{buf}}}} = \frac{{N_{{{\text{ch}}}} \cdot T_{{{\text{ch}}}} - N_{{\text{p}}} \cdot T_{{{\text{pt}}}} }}{{T_{{{\text{buff}}}} }}, $$
(8)
Fig. 8
figure 8

(a) The Np dependence of the BV, Ron and BFOM with charge balance at Tpt = 500 nm, and (b) the E-field distribution at x = 6 μm with different Np.

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Fig. 9
figure 9

(a) The Lpt dependence of the BV, Ron and BFOM, and (b) the E-field distribution at y = 13 nm with different Lpt.

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where Nch = 8 × 1017 cm−3, Tch = 400 nm, and Tpt is the thickness of the P-top layer. The Tpt has no influence on Ron. When a thick P-top layer is grown, the Np can be smaller upon the same Qpt. When the value of Np is relatively small, the depletion effect of the P-top layer on the N-GaN channel is decreased, and the DR-HFET will show a low Ron. Therefore, the Tpt is set as 500 nm, which was the highest value in our previous work.16 The Tbuff is the thickness of the P-GaN buffer layer, which is defined as 2.6 μm in the compared experimental PG-HFETs.

When the charge balance principle is followed during the optimization, the proportion of Qpt to Qbuf has an optimum value of 1.625 (2.6:1.6). According to the double RESURF theory, the selection of the charge density in P-top and P-sub should maintain the full depletion in the N-drift region under the breakdown voltage. For a uniformly doped drift region, the charge in the P-top layer is usually half of that in the drift region.20 However, there is a 2DEG channel in the N-GaN drift region of the DR-HFET in our simulation, so the determination of Qtp should ensure the depletion of both the 2DEG channel and the half of the N-GaN drift region. The charge density in the 2DEG channel Q2DEG is calculated as ~ 1 × 1013 cm−2 in our simulation.16 Thus, the optimum value of Qpt should be the sum of Q2DEG and 1/2Qch, and is calculated as 2.6 × 1013 cm−2. The above results can also be confirmed in the vertical E-field distribution between y–y′ under the heterointerface at x = 6 μm in Fig. 7b. When Np = 3.6 or 6.8 × 1017 cm−3, high E-field strength can be observed only at the N-GaN/P-buffer interface or only at the AlGaN/GaN heterointerface. When the Np = 5.2 × 1017 cm−3, two E-field peaks can be found, at both the N-GaN/P-buffer interface and AlGaN/GaN heterointerface; thus the DR-HFET with Np = 5.2 × 1017 cm−3 shows a relatively uniform distribution of the E-field in the vertical direction.

The Lpt dependence of the BV, Ron and BFOM is shown in Fig. 9a. When the Lpt increases from 1 μm to 5.8 μm, the value of the BV, Ron and BFOM increase monotonically. The reason for the increase in BV can be found in Fig. 9b. When the Lpt increases, the depletion region under the P-top also extends several microns in the lateral direction, so the E-field along the channel can spread more uniformly, thus improving the BV. Therefore, the optimum Lpt is obtained as 5.8 μm in our simulation.

In comparison with other experimental P-GaN gate AlGaN/GaN HFETs in the literature (Fig. 10),14,15,17,18,21,31,32,33,34,35 our device shows a high BV of 1100 V with a remarkably low Ron,sp of 0.53 mΩ cm2, leading to a BFOM of 2.3 GW/cm2, which suggests a good balance between the off-state blocking capability and on-state performance.

Fig. 10
figure 10

Comparison plots of BV versus Ron,sp for the P-GaN gate HFET.

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The Influence of the AlGaN/GaN Quality

Epitaxial growth methods and fabrication process parameters may influence the quality of the AlGaN/GaN heterostructure. Typical growth methods for AlGaN/GaN include molecular-beam epitaxy (MBE) and metal–organic vapor-phase epitaxy (MOVPE), and the low field mobility is most affected by different growth methods.36 According to experimental results, the electron mobility may vary from 2000 cm2/(V s) to 500 cm2/(V s) under different growth conditions.

In our simulation, we use the Lombardi model to calculate the mobility under low electric field conditions. As described in the Lombardi model, the electron mobility is limited by surface acoustic phonon scattering, doping-dependent scattering and interface roughness scattering, while surface acoustic phonon scattering and interface roughness scattering are related to the quality of the AlGaN/GaN heterostructure.36 Therefore, we tune the parameters of B, C and δ in the Lombardi model to simulate the impact of the AlGaN/GaN material quality. Otherwise, we make no changes to the μmax, μ0, Cr or α1 values in the doping-dependent scattering part of the Lombardi model during the low field mobility simulation. Finally, the low field electron mobility μn varies from 500 cm2/(V s) to 2000 cm2/(V s) when we tune the parameters in the simulation.

Figure 11a shows the relationships between the Ron and the Nch and Tch of the NC-HFETs with varied μn. The μn in the previous simulation results is 700 cm2/(V s). When the growth quality of the AlGaN/GaN is improved, the μn will increase while the Ron of PG-HFET will decrease. When the mobility is higher, the Ron of the PG-HFET is lower, and thus the impact of the Nch and the Tch on the Ron is decreased. When μn = 2000 cm2/(V s), the Ron of the PG-HFET is 14.2 Ω mm, and when μn = 500 cm2/(V s), the Ron of the PG-HFET is 3.5 Ω mm. After considering the benefit threshold of Ron, by increasing the channel doping concentration, the Ron of the NC-HFET with μn = 500 cm2/(V s) can be reduced by 8.4 Ω mm, while for the NC-HFET with μn = 2000 cm2/(V s), the Ron can be reduced from 3.5 Ω mm to 1.5 Ω mm. When Tch = 400 nm, the optimum Nch is around ~ 8 × 1017 cm−3, while the Ron for each NC-HFET with different μn reaches the benefit threshold. Therefore, when the quality of the material is improved, the effects of the Ron reduction by increasing Nch or Tch become weak.

Fig. 11
figure 11

(a) The relationships between the Ron and the Nch and Tch of the NC-HFETs with varied electron mobility μn, and (b) the dependence of PG-HFETs and transfer curves, the relative variation of the Ron and the BFOM on the μn.

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As shown in Fig. 11b, when the μn increases to 2000 cm2/(V s), the Idlin of the DR-HFET reaches 47.6 mA/mm, while the Ron of the devices is as low as 2.1 Ω mm. The reduction in Ron with the double RESURF structure is 1.4 Ω mm, which is the lowest Ron improvement among the emulated DR-HFETs.

The graph inset in Fig. 11b shows the dependence of the relative increase in the Ron and BFOM on the μn. It should be noted that the relationship between the BV and the material quality is unclear. If the GaN buffer is of poor quality, the buffer leakage current may increase, causing a premature breakdown.37 Otherwise, in our simulation case, we add acceptor traps into the GaN buffer of the PG-HFETs, and we use P-GaN as a buffer layer in the DR-HFETs. The P-GaN buffer or acceptor trap-doped buffer shows low leakage current, and avoids premature breakdown.38,39 Thus, in our simulation case, the BV of the PG-HFETs remains 600 V, while the BV of the DR-HFETs remains 1100 V. When the μn increases from 500 cm2/(V s) to 2000 cm2/(V s), the relative reduction of the Ron decreases from 53% to 40%, while the relative increase in the BFOM decreases from 6.1 times to 4.6 times. Therefore, the enhancement of forward characteristics and BFOM of the DR-HFETs would gradually weaken when the quality of the AlGaN/GaN is improved.

Key Fabrication Steps

Figure 12 shows the main fabrication steps for the DR-HFET. After growth of the P-GaN buffer/GaN channel epitaxy by metal–organic chemical vapor deposition (MOCVD) (Fig. 12a), the Si-doped GaN channel, the AlGaN barrier and the P-GaN are regrown on the dielectric patterned wafer after selective etching of the GaN channel (Fig. 12b). Then, mesa isolation is conducted to define the active region of the devices (Fig. 12c). The P-GaN gate region is formatted after selective etching of the P-GaN layer (Fig. 12d). Then, a patterned dielectric is deposited after a surface treatment, and the patterned dielectric is used to perform selective area growth of P-AlGaN (Fig. 12e). Finally, a passivation layer is deposited and patterned after the formation of metal contacts (Fig. 12f).

Fig. 12
figure 12

Schematic for the fabrication steps of the DR-HFET: (a) the growth of P-GaN buffer and GaN channel layer, (b) the regrowth of N-GaN, AlGaN barrier and P-GaN layer, (c) the definition of the active region, (d) etching P-GaN gate region, (e) the regrowth of P-AlGaN, (f) metallization and passivation.

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Conclusion

A method for improving on-state performance utilizing double RESURF technology is presented for a P-GaN gate GaN HFET by TCAD simulation. With the simulation validation and the optimization of the Qch, Qpt and Qbuf in the double RESURF structure, a BV of 1100 V and BFOM of 2.3 GW/cm2 can be achieved, which indicates a good balance between off-state blocking capability and on-state performance.