Introduction

Motivation

Through the increasing advancement of technology, the requirement for smaller and more powerful tools has increased for a smarter and simpler life. According to an observation by Gordon Moore in 1966, every 2 years, the number of transistors in an IC (integrated circuit) doubles, which is significant in accelerating the scaling trend of transistors. The scaling trend of MOS was driven by this need for more integrated and efficient circuits. The channel length of MOS is reduced to shrink MOS into smaller units, resulting in decreased power per switching event and improvement in density. Still, it also causes undesirable changes in system properties such as various short-channel effects such as drain-induced barrier lowering and punch through, surface scattering, velocity saturation, impact ionization, and hot electron effect.1

Over the last five decades, CMOS technology scaling has driven the electronics industry to achieve more features and has provided a dense and fast integration.2 In almost every system, the need for more performance and integration has accelerated scaling trends. Therefore, today’s transistors occupy less than 1% space and are 20 times faster than the transistor developed five decades ago.3 The power density and overall power consumption of the chips have also increased along with this. Similarly, the various parameters of the VLSI design such as gate dielectric constant, supply voltage, device leakage current have significantly been modified to achieve the desired performance of the integrated circuits. CMOS became the leading technology for integrated circuits because it can be scaled down to offer higher performance and smaller dimensions.

As per Moore’s law, the downscaling of channel length is accompanied by a shrink in oxide thickness, introducing a hindrance for further scaling. The voltage supply, and transistor dimensions need to be scaled down linearly to accommodate dense integration of transistors.4 Reduced transistor sizes can be defined by the basic electromagnetism equations, which causes a decrease in capacitance, resulting in increased thermal noise (defined by Nyquist). As a result, the probability of bit-flipping is increased, which decreases the overall reliability. According to Dennard scaling rules,1 scaling down device dimensions reduces capacitance values and lowers overall power consumption. However, according to the scaling laws, the supply voltage VDD could not be scaled at the same pace considering the delay, showing itself as a constraint in achieving high-speed, low-power devices.5 This is because carriers in the source and drain regions of the MOSFET are controlled by Boltzmann statistics which restrict the rate of increase in drain current with respect to gate-source voltage to 60 mV/decade and, therefore, prevent further lowering of VDD and overall power consumption.

Background

For a conventional MOSFET, the drain current (ID) of the device is assumed to be negligible if the gate-to-source voltage is lower than the threshold voltage (VGS < VT). When VGS < VT, the drain current decreases exponentially, resulting in OFF-state current or sub-threshold current. The slope of sub-threshold current can be presented as \(\mathrm{d}({\mathrm{V}}_{\mathrm{G}})/\mathrm{ dlog}({\mathrm{I}}_{\mathrm{D}})\) where VG and ID are gate voltage and drain current, respectively. Analytically, sub-threshold swing (SS) is represented as

$$ {\text{SS}} = \frac{{d\left( {V_{G} } \right)}}{{{\text{dlog}}\left( {I_{D} } \right)}} = \left( {\frac{{{\text{KT}}}}{q}\ln 10} \right)\left( {1 + \frac{{C_{D} }}{{C_{{{\text{OX}}}} }}} \right) $$
(1)

where CD is the channel depletion capacitance. At room temperature, SS is defined as

$$ {\text{SS}} = \left( {60 \times 10^{ - 3} } \right)\left( {1 + \frac{{C_{D} }}{{C_{{{\text{OX}}}} }}} \right) $$
(2)

Theoretically, if CD<<Cox, SS will be 60 mV/decade;1 however, SS must be steeper to attain high performance. However, the smaller the ratio of the currents at VGS = VT and VGS= 0 or the ION/IOFF, the greater the leakage current. Consequently, the current ratio must be as high as possible for a high-performance chip, and the sub-threshold slope must be steeper, which can be a solution for the situation. Different transport mechanisms can be implemented to solve this problem, such as impact ionization, tunneling, and positive feedback, essentially by amplifying the gate voltage. Also, different types of doping and structure lower the effect of random dopant fluctuation.6 Recently, transistors with novel transport and switching mechanisms such as nano-electromechanical FET (NEMFET), resistive gate FET,7,8,9 impact ionization of metal oxide semiconductor (I-MOS),10,11 FET tunnelling 12,13 and negative capacitance FET (NCFET) are being investigated extensively to achieve SS below the Boltzmann limit. Since MOS is engineered to be ON at VT, the immense value of sub-threshold current results in device performance reliability issues.

Nevertheless, if the supply voltage is not scaled the same as the thickness of the oxide, its electric field will increase. This inconsistency in supply voltage scaling results in the gradual degradation of the oxide layer and dielectric breakdown.14 As a result, the gate oxide layer thickness cannot be scaled down significantly for an extended period of reliable operation. A severe constraint in resistive FET is hysteresis behavior. Further, the device will be in an ON-state for the reverse sweep until a reset operation is performed at VG<0.

In NEMFET, an abrupt SS is achieved, but operation speed and reliability are limited due to the mechanical movement of the gate. I-MOS have very quick switching, but still it is unlikely for practical applications due to the following two reasons. First, there is a very high breakdown voltage and drain voltage. In addition, hot-carrier degradation of oxides becomes a severe issue due to a high lateral electric field. Furthermore, a complicated fabrication process and low reliability limit the practical application of TFET and I-MOS devices. Among the devices mentioned above, NCFET has attracted much interest because it can achieve steep SS by a voltage amplification mechanism without losing the drive current shown in Fig. 1. High ON-state current along with the suppressed OFF-state current and low power dissipation are its additional advantages. Compared with other sub-60 mV/decade devices, NCFETs possess a simple structure, more compatible fabrication techniques, and excellent working performance such as a steep sub-threshold swing (SS), high ON/OFF ratio, and adjustable hysteresis. Because of the above-listed reasons, the NCFET is a good remedy for the problem faced by TFET, NEMFET, I-MOS, and resistive gate FET.

Fig. 1
figure 1

Steep slope of MOSFET and NCFET.

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In this review article, we have discussed the physics of various NCFET types of devices and observed how doping could lead to significant changes in their properties. Also, we have elaborated on how structural modification can result in efficiency enhancement. After making all the studies, we have summarized the results of different structures in a table. In addition, outcomes based on the various related reports, negative capacitance (NC) devices are categorized according to constraints such as devices for low sub-threshold slope, high ON current, negligible hysteresis, and improved SS, application-specific devices. Considering the above parameters, the MOSFET can be replaced by a promising substitute in terms of NCFET for ultra-low power, high speed, and cost-effective circuits. In addition, NCFET has yielded better results in several applications such as high-gain inverters, ultra-low power devices, internet of things (IoT), memories, biomedical devices, radio frequency (RF) sensing, analog circuits, and filters.

This article is structured as follows: "Working Principle of NCFET" elaborates on the working principle of NCFET and the physics of ferroelectric FET. "Different NC Devices" explores the systematic analysis of different NCFET devices. "Comparison of Fe-FET and NCFET" discusses the comparison of Fe-FET and NCFET, followed by a summarized comparison table. Finally, "Conclusion" lists the challenges in the practical implementation of NCFET and the conclusion of the article.

Working Principle of NCFET

Datta and Salahuddin15 proposed a new idea of using a ferroelectric as an oxide material which makes Cox < 0 and can result in a SS < 60mV/decade. Capacitance is the inverse of the double derivative of energy with charge. The negative capacitance mechanism of NCFET is depicted in Fig. 2. Ferroelectric polarization points upward when biasing is zero and inverts when the gate voltage exceeds coercive field (Ec), as presented in Fig. 2a and b. The curvature around charge (Q)=0 in the energy landscape of a ferroelectric is the opposite of an ordinary capacitor, i.e., an inverted parabola, as shown in Fig. 2c, and provides a negative capacitance. It depicts that a slight change in gate voltage causes a significant difference in the surface potential. However, obtaining the negative capacitance mainly relies upon the capability for driving ferroelectric material away from local minimum to non-equilibrium state.

Fig. 2
figure 2

Working operation of NCFET (a) Polarization under zero bias (b) Polarization when Vg is greater than coercive voltage (VC) (c) Energy landscape of ferroelectric under no bias (d) Energy state after inversion of polarization.

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Figure 2c and d shows the energy landscape variation before and after inversion of polarization. In the non-equilibrium state, the capacitance is negative, but the stage does not offer stability. The stability can be achieved by following any of the two steps in the CMOS gate stack: (1) providing a direct link between the ferroelectric and dielectric layer or (2) a ferroelectric-metal-dielectric connection.

In several studies,16,17,18 it has been shown that the second approach results in a sudden amplification of the MOSFET’s internal voltage (Vint) by the negative capacitance of the ferroelectric capacitor (CFE<0) as can be observed in Fig. 4c. The total capacitance increases with negative CFE, and the negative capacitance effect greatly amplifies Vint. Moreover, the introduction of series capacitance enhances the stability and the channel potential (ψs) on an internal node to adjust above the applied voltage.19 The NCFET structures depicted in Fig. 4a and b are exactly similar to MOSFET, except an additional thin layer of ferroelectric material. The two primary structures of NCFET are metal-ferroelectric-insulator-semiconductor (MFIS) and metal-ferroelectric-metal-insulator-semiconductor (MFMIS). MFIS has an insulator layer that adds an advantage to ferroelectric materials such as barium titanate and lead zirconate titanate to be directly incorporated in the gate stack because of their imperfect crystal matching with germanium and silicon substrates. The MFMIS has an internal metal layer sandwiched between the insulator and ferroelectric, maintaining ferroelectric polarization uniformly along the channel because the potential difference between the top electrode and inner metal is uniform.

Recently, many research papers 20,21,22 have reported steep switching characteristics of NCFETs by integrating silicon and zirconium doped ferroelectric layer and replacing the transistor channel with the carbon nanotube. In a ferroelectric MOS capacitor, the polarization charge density and channel charge density must match to find the operating point. Thus, NCFET static operating point is figured out through the cross-point of polarization-electric field (P-E) curve and load line of channel charge shown in Fig. 3. If the curve has a single cross point in the NC region (the P-E curve has a negative slope), the ferroelectric MOS transistor acts as NCFET. The different structures and circuit models are shown in Fig. 4.

Fig. 3
figure 3

Schematic of polarization-electric field and channel load line.

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Fig. 4
figure 4

Ferroelectric-based structure of NCFET: (a) MFIS, (b) MFMIS, (c) Circuit model of NCFET, and (d) Equivalent capacitance of substrate.

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Kim et al. reported in23 that the hysteresis in NCFETs occurs by the leakage current, which flows into the ferroelectric film through the dielectric layer, develops a ferroelectric depolarization field and causes charge traps. However, ferroelectric capacitor hysteresis can be avoided by modifying ferroelectric layer thickness. Here, static operation points of reference materials parameters are optimized. These materials have thickness dependence on the ψs–Vg characteristics of the NCFET MOS capacitor with positive ferroelectric voltage. In the thickness range of 3-5 nm, ψs is amplified without hysteresis. This amplification is an inspiring outcome because the ferroelectric’s thickness is only a few nanometers. In addition, only Vg of 0.2 V is required to amplify ψs (channel potential) that allows low supply voltage operation. It should be noted that the point of static operation will not be set appropriately for too high thickness, and the ψs-Vg curve will show a hysteresis effect.24 Notwithstanding hysteresis, NCFET has excellent potential for operation under the SS limit. For negative capacitance,

$$ \frac{{d\left( {V_{g} } \right)}}{{d\left( {\Psi s } \right)}} = \left( {1 + \frac{{C_{S} }}{{C_{{{\text{OX}}}} }}} \right) $$
(3)

which may be less than 1 if the COX is negative.6 In the case of negative capacitance, COX is negative, which can cause SS to cross the theoretical limit of MOSFET less than 60mV/decade. The advantage of this process is that it enables the use of existing fabrication flow by only the inclusion of an oxide layer leading to a negative capacitance effect. The typical structure, circuit model, and equivalent capacitance of the substrate of the NCFET device are shown in Fig. 4.

A negative capacitance field-effect transistor (NCFET) introduces a thin ferroelectric material (FE) layer to an existing MOSFET gate oxide, as shown in Fig. 4a and b. The addition of ferroelectric material leads to a surface potential variation even for the slight change in the VG. The key to negative capacitance is that it compensates the positive device capacitance such that the derived gate capacitance (CG) can be written as,

$$ {\text{C}}_{{\text{G}}} = {\mkern 1mu} \left( {{\text{C}}_{{{\text{FE}}^{{ - 1}} }} + {\text{C}}_{{{\text{MOS}}^{{ - 1}} }} } \right)^{{ - 1}}$$
(4)

results in sub-60mv/decade as understood from Fig. 4c and d. Fig. 4c and d are the capacitor equivalent model of NCFET, which represents the ferroelectric MOS capacitor as a series combination of channel capacitance and ferroelectric capacitance.

In an NCFET structure, the underlying MOSFET acts as a positive capacitance (CMOS) (Fig. 4c), which can stabilize the ferroelectric in the NC state if the total gate capacitance (Eq. 4) is positive. This condition states that |CFe| must be greater than CMOS to realize a stable NC state of the ferroelectric in NCFET. In addition, both the |CFe| and CMOS can be affected by the applied voltages. When the above condition is violated for any combination of gate voltage (VG) and drain voltage (VD), NCFETs become unstable, resulting in hysteresis in the electrical characteristics. To avoid such violation, the thickness of ferroelectric should be constrained because |CFe| varies proportionally with the ferroelectric thickness (TFe). Additionally, |CFe| also depends on the coercive field (Ec) and the ferroelectric’s remnant polarization (Pr) values. The ferroelectric with a high remnant polarization (Pr) and low coercive field (Ec) leads to an increase in the value of |CFe|. This implies that the condition of no hysteresis (|CFe| > CMOS) is always met across the operating voltage range. In addition, a low Tfe, high Pr, and low Ec reduces capacitance matching between CFe and CMOS. The FE oxide interface has an internal voltage greater than VG, such that the SS can be reduced below the 60 mV/decade (Boltzmann maximum limit) at 300K. As a result, as opposed to the classical transistor, we can have a larger current in the device for a smaller gate voltage.

Physics of Ferroelectric FET

The ability of certain dielectrics to have a spontaneous polarization that can be reversed by an applied electric field (E) is termed ferroelectricity. A ferroelectric is an insulating device with two or more distinct stable states. It has distinct non-zero electrical polarisation without an electrical field called “spontaneous” polarization. For ferroelectric devices, the switching probability between these states in the presence of an applied electrical field (E) is greater than the coercive field that adjusts the relative energy of the states by coupling to the field to the polarization (P). Joseph Valasek discovered this property in the course of Rochelle salt studies in 1921.25 Since then, there has been extensive study of materials that exhibit ferroelectric properties. Such materials show reversible and spontaneous polarization even when there is no external electric field. Electric polarization in ferroelectric materials occurs spontaneously due to phase transition at a critical temperature known as Curie temperature, Tc, without any external electric field. The crystal undergoes a phase transition from the ordered phase to the disordered phase at and below Curie temperature. Above the Curie temperature, materials are polarized under the electric field by the change in transition. Hence, the ferroelectric materials polarize spontaneously below the Curie temperature.

One of the critical characteristics of ferroelectric material is hysteresis. In hysteresis, all dipoles are pointed in specific directions, and these regions are known as domains. In the absence of an electric field, the net polarization is equal to zero due to random orientations of domains. However, dipole moments align themselves along the electric field by rotation under the influence of an applied electric field, thus forming a region with a net dipole moment oriented in a single direction. With the removal of the electric field, these created domains do not disappear. These irreversible processes of polarization result in hysteresis in material characteristics, as illustrated in Fig. 5. P-E hysteresis is not a sufficient condition for a ferroelectric material. Trapping phenomenon or leakage currents,26 surface polarization can also result in hysteresis loop detection.

Fig. 5
figure 5

Variation of polarization with electric field.

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It can be observed that small displacements in weak electrical fields are reversible. Furthermore, remnant polarization (Pr) refers to the polarization value when an electric field is zero. The strength of the electric field required to bring the polarization back to zero is known as the coercive field (EC). The threshold electrical field must be higher than the coercive field to alter the state of a ferroelectric device. If the electric field is applied in the same direction as the previous applied electric field, there will be no switching, and the charge will remain the same. The minimum electric field must be larger than the coercive field (Ec) for changing the state of the ferroelectric device. Unlike ferroelectrics, where the dielectric permittivity decreases with the electric field, the dielectric properties of antiferroelectric (AFE) materials can be improved at a high field due to the electric field-induced transition from an antiferroelectric state to a ferroelectric one. AFE materials exhibit low coercive fields and dielectric losses (at low field), as well as a high saturated polarization.

Until now, many researchers have focused on ferroelectric materials such as strontium bismuth tantalite (SBT) and lead zirconate titanate (PZT)27,28 because of their dielectric, ferroelectric properties, leakage current characteristics, and long polarization retention. However, these materials show unstable ferroelectric behavior at thin film morphology, and they are also incompatible with standard IC processing technology. Hence, the discovery of hafnium oxide (HfO2)-based dielectrics yields the potential to overcome these limitations. HfO2 is preferred due to its high dielectric constant (~20), large band gap (~5 eV), large conduction band offset (1.5eV), and thermal stability. Ferroelectricity is observed in thin HfO2 film without generating a large leakage current because of its wide band gap. Several studies show that controlling crystalline phases of HfO2 thin film can lead to ferroelectricity in HfO2, making it an attractive element. In addition, as a gate dielectric, this material is compatible with current IC technology. Dopants such as yttrium,29,30 silicon,31,32,33,34,35 and aluminum36 have been used to cause ferroelectricity in doped HfO2. Silicon-doped hafnium dioxide (Si: HfO2) exhibit favorable results with a stronger coercive field (1 MV/cm versus 50 kV/cm for PZT/SBT) and a low dielectric constant (~30 versus 200-300 for PZT/SBT)33 and is successfully incorporated into Fe-FET devices.26

Different NC Devices

The property of ferroelectricity was first observed in the 1920s, but the negative capacitance theory in ferroelectric material is more recent. McKee et al. suggested that incremental change in capacitance beyond classical limits could generate novel super capacitance structures.37 The significant developments of NCFET structures are shown below in Fig. 6 and further discussed in the upcoming section.

Fig. 6
figure 6

Major developments of NCFET, highlighting different structures, channel doping, and ferroelectric material.

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Devices for Low Sub-threshold Slope

The NCFET became a promising candidate to achieve SS less than 60 mV/decade at room temperature. Many researchers tried to lower the Boltzmann limit by proposing structural and materials modification. Initially, in 2008 Salahuddin et al. reported that the SS could be below the fundamental limit by using ferroelectric material as a gate insulator in MOSFET.15 Later, Khan and his research group explained the impact of negative capacitance in the nanoscale ferroelectric dielectric heterostructure in 2011.38 They used a ferroelectric bi-layer Pb(Zr0.2Ti0.8)O3 and a dielectric material SrTiO3. In,39 hysteretic switching together with a sub-kT/q steep slope (13 mV/decade at 300K) in MOSFET with PbZr0.52Ti0.48O3 is experimentally demonstrated as a FE gate insulator, integrated as a buffer interlayer on a silicon (si) channel with a non-perovskite high-k dielectric (HfO2). The abrupt transition is independent of the bias drain. In addition, sub-kT/q switching is noticed for the first time due to FE negative capacitance in the strong inversion (Id = 100 μA/μm) instead of low currents. Steep switching in strong inversion gives a significant consistency point with the assumptions of the Landau–Devonshire approach and the Landau–Khalatnikov equation.40,41,42,43,44,45,46 An experimental investigation of the negative capacitance FinFET device revealed that the length of source/drain (Lext) extension affects the hysteresis window. It was observed that an increase in Lext decreases hystersis. The same device exhibited a 0.48 V hysteresis window with an ON/OFF current ratio of approximately 107 by controlling Lext. Additionally, a sub-20 mV/decade SSavg expected to counter the Boltzmann limit was experimentally verified versus a FinFET baseline with an SSavg of approximately 105 mV/decade.47

Various ferroelectric materials such as BFO, SBT, and PZT exhibit compatibility with CMOS process technology; for example, the ferroelectric layer thickness should be less than 10 nm to be accepted in the current CMOS gate stack. Thus, a new sub-10 nm thick FE material compatible with CMOS, such as doped Hf-based FE material, can be incorporated in CMOS design. In,48 a sub-10 nm thick HfZrO capacitor-based NC FinFET exhibited a steep switching feature compared to baseline FinFET. The NC FinFET’s minimum SS was ~36 mV/decade at room temperature, which implies that the internal voltage is amplified due to the NC effect of the Hf-based ferroelectric layer. Rahman et al. reported the inclusion of Si-doped HfO2 as ferroelectric material in NCFET to achieve a lower SS of 30 mV/decade, which was much lower than the regular MOSFET device.49 Similarly, the use of multi-layer ferroelectric material achieved an excellent matching for the entire operating gate voltage range. The degree of improvement depends on the capacitance between the FE layer (CFE) and the underlying MOS transistor (CMOS). The technique of using multi-layer ferroelectric proposed in50 provides better SS and leads to a lower power supply (VDD) than the single-layer NCFET.

In 2013, Yeung with his colleagues proposed a new concept of incorporating an ultrathin body (UTB) structure in NCFET to suppress the short channel effects, thus significantly reducing the power loss.51 Moreover, using a 1 nm Si body as an example, they demonstrated that NCFET possesses no hysteresis in ultra-thin body configuration. This non-hysteretic NCFET can achieve ION=250 A/μm, IOFF=10 pA/μm at 0.3 V VDD and 21 mV/decade swing from Id of 10 pA to 10 μA per micron without considering mobility enhancement by strain. A 1.8 nm Zr-doped HfO2 gate oxide layer was deposited upon the FDSOI wafer, and this device exhibited hysteresis-free operation.52 Compared with a crystalline HfO2 gate oxide-based device, the Zr-doped HfO2 device showed a 10X reduction in the OFF current (IOFF) and 20 mV/decade steeper SS. On the other hand, this NCFET provided a more significant ON current at constant VDD, at matched IOFF.

Alternative Channel Material for Lowering SS

Recently, some functional 1D and 2D materials have been introduced in the channel of various NCFET-based devices. These materials possess some specific features, which dominate the performance of these devices. Some of the important details of different materials have been discussed below and their comparison is represented in tabular form (Table I). An exciting category of these materials is transition metal dichalcogenides (TMDCs) which are two-dimensional van der Waals materials. Their general chemical formula is MX2, in which M is a transition metal (such as molybdenum (Mo) or tungsten (W)) and X is a chalcogen (such as selenium (Se), sulphur (S), or tellurium (Te)). The metal layer is sandwiched between two chalcogenide layers in bulk TMDCs, and each layer has a thickness of three atoms. A carbon nanotube (CNT) is a one-dimensional (1D) material with high electrical conductivity and small scattering cross section. The nanotube conducts primarily on its surface, where all the chemical bonds are saturated and stable. Additionally, there are no dangling bonds to form interface states. As a result, the interface between the gate dielectric and the nanotube channel does not require careful passivation. CNT have high mobility of approximately 80,000 cm2/Vs, which stipulates that they are superior for high-speed electronics. Beta gallium oxide (β-Ga2O3) is a promising alternative for n-type channel material because of its large electrical breakdown voltage of ∼8 MVcm−1, ultra-wide band gap of 4.6−4.9 eV, high electron mobility of ∼100 cm2/Vs, and lattice compatibility with other wide band gap semiconductors (ZnO, SiC). All of these properties establish that β-Ga2O3 can be used for various electronic applications such as high-power applications, high-frequency devices, and optoelectronics. Table I presents the comparison of different channel materials.

Table I Comparison of different types of channel materials
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Many experiments were done for designing NCFET channels with Group III–V semiconductors but did not succeed in achieving hysteresis-free and sub-60 mV/dec SS53 simultaneously. Dong et al.54 proposed an NCFET model with monolayer MoS2 (molybdenum disulfide) as channel material. They demonstrated a simulation model explaining the effects of DIBL (drain-induced barrier lowering) and negative-output differential conductance (NDC) for a scaled-down NC-MOSFET. In addition, the inclusion of an ultrathin metallic layer with a monolayer channel significantly improves DIBL and NDC with a SS of 53.9 mV/decade. Similarly, low dimensional materials such as carbon nanotubes22 and WSe2 (tungsten diselenide)55 are used as the channel in NCFET.

A comparative study on SS of the UTB NCFET using Ge and Si as channel materials was performed.56 The results showed that a high permittivity germanium channel is more appropriate due to its high Cch (capacitance of the channel depletion). The Ge channel provides a better sub-threshold gate capacitance due to its higher permittivity leading to higher channel capacitance, Cch (εch/Tch). Furthermore, drain coupling (CDIBL) increases as the channel permittivity increases. Thus, germanium on insulator NCFET(GeOI) is better than Si-based NCFET because of its higher CCH and CDIBL (drain coupling). Further, GeOI NCFETs can also achieve lower SS than the Si counterpart. Later, a steep-slope β-Ga2O3 (beta gallium oxide) NCFET was demonstrated in the dielectric stack at the gate with ferroelectric material hafnium zirconium oxide (HZO) with hysteresis less than 0.1 V.57 Additionally, a minimum SS value of 34.3 mV/decade at reverse VG (gate voltage) sweep and 53.1 mV/decade at forward VG sweep at VDS = 0.5V is obtained. The enhancement-mode operation with a VT (threshold voltage) of 0.4 V is achieved by adjusting the β-Ga2O3 membrane thickness. A 2D transition metal dichalcogenide (such as MoS2) is a viable alternative channel material that provides sub-nanometer thickness and a more stabilized channel capacitance. This produces steep switches (slope) over a wide current range when coupled with the NC effect. In,58 2D NCFETs are demonstrated utilizing MoS2 and hafnium zirconium oxide (HfZrO2 or HZO) as channel and FE materials, respectively. These materials are compatible with CMOS technology which achieves repeatable and sustained sub-60 mV/decade switching, thus making it a promising candidate for scalable and low voltage transistors. Up to that point, the only demonstration of a 2D channel NCFET was done by using polymeric ferroelectric materials, which resulted in unstable and incompatible CMOS but improved low-voltage switching.59

Devices for High ON Current

In 2011, Khan et al. suggested anti-ferroelectric (AFE) mode,60 which achieved a sub-60 mV/decade SS and better current ratio. In this AFE mode, lines of ions in the crystal are spontaneously polarized, but with neighboring lines polarized in antiparallel directions. In simple cubic lattices, the antiferroelectric state is more stable than the ferroelectric state. Hu et al.61 simulated the first negative capacitance FinFET, resulting in Vdd of 0.2V, 0.6mA/μm ON current, and 100pA/μm of leakage current. Later, Jang et al. reported that the ferroelectric HfO2 -based NCFET with gate-all-around (GAA) nanowire channel design has five times and two times larger ION/IOFF ratio than classical nanowire MOSFET and DG NCFET, respectively.62 Another device, negative capacitance independent multi-gate FinFET (NC-IMG-FinFET), achieved SS of 42 mV/decade, larger ON current, and smaller OFF current by addition of 11 nm thick FE film at 300K. The leakage current can be controlled, and a significant high ON current can be obtained by increasing the thickness of FE material within a specific range.63 However, increasing FE material thickness increases the equivalent input capacitance of the device. Thereafter, the negative capacitance carbon nanotube FETs (NC-CNFETs) were proposed, combining the advantages of carbon nanotube channels and NC effects.22 The device achieves 20% less SS and 100% more ON current when compared to baseline CNFETs. In,64 the influence of the coercive field, remnant polarization, and parasitic capacitance on NC-FinFET performance was investigated. A suitable value of Pr is recommended to attain high ON current than baseline. Another experiment was carried out using CIPS flake and MoS2 2D van der Waals heterostructure, which improves current ON/OFF ratio and suited resistive RAM.65 CIPS is copper indium thiophosphate (CuInP2S6), which has van der Waals (vdW) layered structure with switchable polarization down to ~4 nm, low leakage current, and robust ferroelectricity at 300K. The CuInP2S6 is a 2D ferroelectric insulator incorporated on the top of the MoS2 channel allowing for a 2D/2D semiconductor/insulator interface with no dangling bonds. The MoS2/CIPS 2D vdW heterostructure ferroelectric FETs exhibit a counter-clockwise hysteresis loop in transfer characteristics, clearly showing their ferroelectric properties. Additionally, it decreases the interface trap density and reduces interface issues. Furthermore, the back-gate bias of the MoS2 transistors can modulate its stable nonvolatile memory attribute due to the tuning of capacitance matching between ferroelectric CuInP2S6 and MoS2 channel, which consequently improves the ON/OFF current ratio.

Devices with Negligible Hysteresis and Improved SS

In 2012, Yeung et al. obtained sub-30 mV/decade SS in non-hysteretic NCFET by adopting body profile engineering. In this method, using a thin channel layer on a highly doped bottom layer improves the performance of SS by increasing the negative capacitance-voltage amplifying effect. This model achieves SS of 28.3 mV/decade over six orders of magnitude with IOFF=10pA/μm, ION=0.3mA/μm at VDD=0.3V for a gate length of 100 nm without strain mobility enhancement. However, the inclusion of a semiconductor layer on the conductor (TTSOC) enhances the device’s performance by mobility enhancement or shorter gate length.6 In,66 antiferroelectric HZO is used, resulting in zero hysteresis and an average SS of 50 mV/dec because of less remnant polarization and coercive field. Furthermore, an experimental analysis of HZO with epi-Ge/Si channel is hysteresis-free, switching at less than 0.2 V and SS of 42 mV/dec in forward sweep and 28 mV/dec in reverse sweep.67 In 2017, aluminum-doped hafnium dioxide (HAO) was proposed as ferroelectric material.68 It provides SS of 40 mV/decade and 39 mV/decade for the forward and reverse sweep, respectively, together with an almost hysteresis-free performance at room temperature and low temperature. The HAO-based FET shows a similar steep SS value and is also hysteresis-free as compared to ultra-thin FE-HZO. Among the other 2017 works, Lee et al.69 demonstrated the FE-HZO (ferroelectric HfZrOx) NCFET along with high-temperature annealing (free of hysteresis), and Nourbakhsh et al.70 presented NC MoS2 FET incorporating ferroelectric Al-doped HfO2. Later, the analysis of hysteresis-free short-channel NCFETs was performed by associating quantum-mechanical calculations and the Landau–Khalatnikov equation which accounts for negative differential resistance (NDR) in the output characteristics.71 Because of the strong gate controllability, since CG (gate capacitance) increases with TFE (ferroelectric thickness), both SS and DIBL decrease. When SS has an upper bound of 60 mV/decade, abnormal behavior emerges in NCFETs, such as DIBR (drain induced barrier rising) and NDR. Although both n-type and p-type NCFETs are hysteresis-free, hysteresis behavior is observed in an inverter due to NDR. In conventional MOSFETs, the load lines have a single cross point for one input voltage, but in the case of NCFETs with NDR, two or more cross points are observed. This induces the hysteresis behaviour in voltage transfer characteristics of NCFET inverters. The hysteresis loop can be modified by adjusting TFE. As the TFE of NCFETs become thicker, the hysteresis loop becomes more apparent due to stronger NDR.

In 2018, methods for obtaining sub-kT/q non-hysteretic operation mode in NCFET for a wide band of VG were investigated by employing capacitance matching.72 In an unprecedented move, a unique approach for matching arbitrary MOSFETs with different ferroelectric (FE) materials was tossed. The NC germanium (Ge) pFETs introduce NDR with the different thicknesses of HfZrOx (HZO) was reported in.73 For non-hysteretic devices, NDR is pronounced with an increased TFE (thickness of ferroelectric film) and VGS (gate voltage), leading to an improved matching between CFE and CMOS. For the hysteretic NC transistors, NDR can be achieved only at a lower VGS because at a higher VGS, |CFE| can be smaller than CMOS, which increases the negative coupling factor.

Application-Specific Devices

The invention of BaTiO3 (barium titanate) led to the development of ferroelectric oxide as a capacitor for industrial applications.74 Afterward, the FE materials were used in the memories and switching devices for various applications. The use of the NC approach in electronic circuits has much lower power dissipation. Additionally, Yeung et al. reported the implementation of non-hysteretic NCFET to realize ultra-low power devices in.6 Currently, various researchers are concentrating on developing more energy-efficient NC devices. The article22 surveys energy-efficient electronic devices merging the advantages of NC effects and carbon nanotube channels for future generations. Capacitance enhancements, which were experimentally demonstrated in,38 can be advantageous for ultra-dense DRAM applications. In 2014, for the first time, an NCFET-based pNCFET was fabricated.75 Subsequently, pNCFET were fabricated on SOI MOSFET with PZT and STO (strontium titanate) deposition, and SS of almost 100 mV/decade was observed as the device was fabricated with very low gate leakage. However, it was not further tested because the gate contact pad was damaged when different temperature-dependent I-V measurements were attempted. NC-FinFET61 was suitable for high-speed, low-power servers to ultra-low power IoT devices. The hysteresis behavior of the NCFET inverter71 makes it a promising candidate for noise filters. Additionally, NCFET inverters with hysteresis behavior such as the Schmitt trigger can be used as a noise filter that advances the application area.

In 2017, Li et al. designed a non-volatile NCFET D-flip flop (DFF) which retained its state during power outages.76 They also fabricated an NCFET which produces hysteresis edges below 10 mV/decade upon seven orders in magnitude between the two IDS (drain-source current) states at VG=0. Additionally, the device is energy efficient and has an ultra-low energy-delay overhead (less than 2.1%) in normal operations and can be used in IoT and power gating applications. Finally, β-Ga2O3 NCFETs prove to be a demanding nFET candidate for upcoming wideband gap CMOS logic applications.57 The NCFET concept helps us to enable arbitrary tailoring of the energy landscape77,78 and realize Landau switches.

In 2019, for the first time, researchers79 investigated the outcomes of ferroelectric thickness in an undoped hafnium oxide-based NCFET. They developed a resistive load inverter which shows that increasing the ferroelectric thickness within a range enhances the noise margin and lowers the power dissipation. A charge plasma-based dopingless ring NCFET was designed and analyzed in,80 which provides SS of 20 mV/dec and high ON current. It has a wide range of applications such as biomedical, RF sensing, analog circuits, and space.

Modifications in Other Attributes of NCFET

The preceding sections discussed the improvement of SS, ON current, and hysteresis of NCFET. However, there are still some other attributes of NCFET which also dominate the performance of the device. Thus, in the light of these attributes, Khan and his colleagues reported a method for measuring NC (negative capacitance) directly in an isolated ferroelectric capacitor.81 This was a significant achievement because the calculation of negative capacitance in practice was a problem until that time. They also introduced two fundamental concepts called the characteristic negative capacitance transients and the dynamic hysteresis loop in negative capacitance. In 2016, Khandelwal et al. presented an NC FinFET model and extracted various performance parameter values. Nevertheless, the model did not include the effects of trap charges.82 Subsequently, a spice-compatible model was published for NC FinFETs device, but it did not have the implications of ferroelectric parameters on device characteristics.83 In their subsequent work, they proposed an enhanced model for NC FinFET in 2017, in which they included the effects of trap charges.84 However, in 2016, Khan also published a report on a change in charge balance when the ferroelectric material is leaky. In addition, the model includes the non-ideal ferroelectric leakage phenomenon.85 A ferroelectric capacitor with a parallel resistor is used for modeling the leakage, which offers the additional path to screening charges that degrade the performance. The solution to the above problem is the proper selection of work functions. It also reduces the leakage by modeling leakage as a resistance (I = V/R). The basic methodology for modeling NCFET includes an additional insulating layer which is controlled by the Landau–Khalatnikov equation written as,

$$ {\text{V}}_{{{\text{FE}}}} = { 2}\alpha {\text{Q }} + { 4}\beta {\text{Q}}^{{3}} + { 6 }\gamma {\text{Q}}^{{5}} $$
(5)

Khan also theoretically studied about leakage with the explanation of ferroelectric dynamics by Landau–Khalatnikov in the presence of a sandwiched metallic layer between the ferroelectric and dielectric material. In 2016, 18 nm and 27 nm thick (gadolinium) Gd:HfO2 capacitors were presented in series with an external resistor. This provided negative capacitance measurement directly in the polycrystalline HfO2 -based thin film.86 Different key parameters reported for a couple of NCFET structures are plotted and compared in Fig. 7. This is an effort to highlight the improved device performance by modifying ferroelectric thickness, gate length, and 2D materials in the channel.

Fig. 7
figure 7

Radar chart of the different figures of merit (FOMs) for different devices.

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Comparison of Fe-FET and NCFET

Fe-FET has hysteretic V-I properties, but NCFET does not; thus, Fe-FET has a broader application area in memory devices. For an NCFET, the gate’s overall capacitance is positive, implying that the negative capacitance state is stable in the ferroelectric insulator for a single state as per the quasi-static NC model. However, for the Fe-FET, the total capacitance of the gate is negative, so that the transistor transfer characteristics between two states result in hysteresis. The first experimental articles discussed the problem of steep-switching associated with Si Fe-FETs and “negative capacitance” using a thick polymer P(VDF-TrFE) as a ferroelectric insulator.16,87,88 Another ferroelectric material PZT-based Fe-FET is modeled, and its advantage of decreasing the delay in a ring oscillator by 97% is illustrated.89 Since 2014, several reports have been published on quasi-static or stabilized hysteresis-free Si NCFETs with SS of sub-60 mV/decade at room temperature. Also, researchers have investigated the performance of HZO as a ferroelectric gate insulator that provides a significant performance improvement. Following the above works, Si NCFETs were investigated with different gate stacks and structures falling into either Fe-FET (unstabilized NCFET)47,90,91,92,93,94 or steep-slope hysteresis-free NCFET20,68,95,96,97,98,99 with a minimum SS of sub-40 mV/decade at room temperature. This article includes all critical aspects of NCFETs, their physics, different channel engineering, and various low-power applications and their performances. In addition, the comparison of the figure of merit parameters of NCFET is presented in the following Table II.

Table II Comparison of different types of NCFET based on various characteristics
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Conclusion

The search for devices with faster switching speed than the conventional MOSFET has become a ubiquitous research motivation in the semiconductor industry. We have reviewed state-of-art technologies of NCFET for future low-power electronic devices. The paper discusses the development of various negative capacitance field-effect transistors from their initial stages until recent modifications. The incorporation of negative capacitance effect at gate provides sub-60 mV/decade SS which minimizes threshold voltage and thus power consumption. Moreover, it results in an additional barrier at the drain due to a decrease in internal gate voltage at higher drain voltage. At lower gate voltages and higher ferroelectric thickness, NDR behavior can be noticed in drain characteristics of NCFET. NCFETs also have lower SS and DIBL, which suppress short channel effects.

The discovery of ferroelectric properties of doped hafnium oxide in NCFET provides compatibility with CMOS structure and prevents the issue of limited scaling in conventional ferroelectric devices. As the technology scales below the 5 nm node, the critical device dimensions are extremely small, and the issue of incorporating thick FE layers into a gate stack turns out to be a challenging task. In addition, the incorporation of extremely thin 2D materials in the channel suppresses the short-channel effects. These two findings played a vital role in terms of scaling as well as enhancing the device characteristics. NCFET has brought significant changes to the semiconductor industry, and the design ecosystem is progressing with device new features.

NCFETs with SS<60 mV/decade, high ION / IOFF, and adjustable hysteresis can reduce supply voltage and power dissipation, thus making them a viable choice for low-power applications. However, NCFET devices suffer from several issues such as difficulty in integration, heavy metal contamination of the manufacturing line, and the presence of thick traditional ferroelectric material. As a result, conventional ferroelectric materials such as barium titanate and lead zirconate titanate are incompatible with modern CMOS technology. Hence, many research efforts are required to improve the performance of NCFET through channel engineering, exploring different structural engineering, ferroelectric materials, and optimizing materials parameters which may enable the rapid commercialization of NCFET-based devices in the near future.