Introduction

RF MEMS switches have great potential to replace the existing counterparts such as PIN diodes and coaxial switches. These switches have no leakage current in the OFF state and offer high isolation.1,2,3,4,5,6 At present, PIN diodes, CMOS, and GaAs MESFET-based SPST switches are used in transceiver systems.7,8 MEMS technology-based SPST RF switches can be a better alternative to the existing switches used in transceivers.9,10,11,12,13

MEMS switches consist of both suspended mechanical (cantilevers, bridge, etc.) and electrical parts. The suspended structures are the critical elements of RF MEMS switches. A sacrificial layer is used to fabricate these mechanical hanging structures. Metals (copper, nickle, etc.), silicon dioxide (SiO2), and silicon nitride (Si3N4) are broadly used as the sacrificial layer material.14,15,16,17,18,19

Copper, nickel, and other metallic materials as a sacrificial layer have selectivity challenges during the release of the hanging structures.20,21,22 Dielectric materials such as silicon dioxide (SiO2) and silicon nitride (Si3N4) required high deposition temperature and selective etching process during removal of the sacrificial layer.23,24,25,26 Hence, metallic and dielectric materials are not compatible with most MEMS devices. The photoresist-based sacrificial material is another good alternative for MEMS devices. It can be deposited easily by spin coating and has a low processing temperature. The photoresist-based sacrificial layer is either removed by dry etching (plasma etching) or wet etching (Piranha solution).17,18,23,27

Based on gap and device, a photoresist for the sacrificial layer is chosen. For thin photoresists such as S1800, S1300, or AZ1505, recipes are optimized and the layer is easily removed with acetone.17,18,28 However, optimization of thick photoresists suchh as HiPR 6517 is required. The standard patterning process involves the vertical placement of wafers during baking. The same process for thick photoresists leads to non-uniform thickness across the wafer. Researchers have published literature on sacrificial layer thickness, profile, and edge coverage optimization.18 However, the effect of the non-uniform thickness of the sacrificial layer on the device yield is least explored. In this paper, HiPR 6517 is selected as the sacrificial layer material and optimized to achieve uniform thickness across the wafer for a better yield. The pull-in voltage, mechanical resonance frequency, insertion loss, and isolation of the fabricated SPST RF MEMS switch are measured.

HiPR Thickness Optimization

An RF MEMS switch is an essential building block of most RF MEMS devices such as phase shifters, varactors, T-matrixes, and tunable filters. Hence, in this paper, the sacrificial layer is optimized for an RF MEMS switch to cover most RF devices.

In the RF MEMS switches, the pull-in voltage depends upon the gap between the actuation electrode and the suspended bridge. A large gap leads to a larger pull-in voltage, and a small gap leads to a lower pull-in voltage. But small gap introduces the capacitive loss and degrades the switch's RF performance. The bridge's gap is optimized such that the pull-in voltage of the switch should be minimal without degrading the switch's RF performance.

The HiPR 6517 photoresist is optimized for use as a sacrificial layer of the RF MEMS switch. Spin coating is used for the deposition of the film. The spin-coating time and acceleration are fixed to 60 s and 1000 rpm, respectively. The ambient temperature of the spin coating room is fixed at 18°C. The HiPR is spin-coated at different RPMs to achieve the desired thickness. The approximate spin-coated thickness (T) of the photoresist is given by the following Eq. 1:29

$$ T = \frac{{KC^{\beta } \eta^{\gamma } }}{{\omega^{\alpha } }} $$
(1)

where K—overall calibration constant, C—polymer concentration, η—intrinsic viscosity, and ω is the spin-coating speed (rpm). α, β, and γ are the exponential constants.

The spin-coated wafers are placed vertically in the specially designed boat, as shown in Fig. 1. The wafer’s vertical placement is preferred as it occupies less space to accommodate the multiple wafers and ease of handling. We have taken five samples in a single run. All the wafers are spin-coated one by one, which takes around 6-7 mins. During this duration, wafers are kept at 18°C in the vertical position. After that, wafers are placed in an oven for pre-baking at 90°C for 25 min.

Fig. 1
figure 1

The vertical placement of the wafer.

Full size image

The thickness of the spin-coated HiPR 6517 layer is measured using an optical surface profiler. The advantage of an optical surface profiler is that it does not require any step height in the photoresist for thickness measurement. The thickness measured after the pre-baked HiPR 6517 photoresists at different coating speeds is shown in Fig. 2. The required thickness of the HiPR 6517 sacrificial layer for the RF MEMS switch is achieved at 3000 rpm.

Fig. 2
figure 2

RPM versus thickness variation of HiPR 6517 photoresist.

Full size image

Fabrication of the RF MEMS Switch

The capacitive SPST RF MEMS switch is fabricated using surface micromachining technology with the help of a recipe optimized for the sacrificial layer described in “HiPR Thickness Optimization” section. The design and stress-related concerns of the switch are addressed in the earlier publication.30 The complete fabrication process of the capacitive SPST switch is illustrated in Fig. 3. It comprises five levels: lithography, oxidation, diffusion, metallization, and etching stages.

Fig. 3
figure 3

(a-l) Fabrication process flow of the RF MEMS Switch.

Full size image

The selection of substrate plays a vital role in the RF performance of the switch. Hence, to achieve better RF performance, a highly resistive (> 4000 Ω cm) silicon wafer of 280-µm thickness is chosen as a substrate material (Fig. 3a). The switch's fabrication procedure starts with the standard microelectronics fabrication cleaning procedure to remove the wafer's contamination. A 1-µm-thick silicon dioxide layer is thermally grown over silicon for surface passivation (Fig. 3b), and a 0.4-µm-thick polysilicon layer is deposited over the silicon oxide layer by using low-pressure chemical vapor deposition (LPCVD) to define the actuation electrodes and bumps (Fig. 3c, d). Subsequently, the underpass area of the transmission line of 200-nm-thick gold (Au) is defined by using lift-off (Fig. 3e). A 0.1-µm-thick silicon dioxide layer is deposited using plasma enhanced chemical vapor deposition (PECVD). This silicon dioxide layer prevents the electrical shorting between the actuation electrode and bridge in a downstate position (Fig. 3f). A 0.1-µm-thick Cr/Au floating metal layer is patterned using a lift-off process (Fig. 3g). After that, a 2-µm-thick sacrificial layer of HiPR 6517 photoresist is spin-coated and patterned to provide initial support to the bridge structure (Fig. 3h). Further, lithography of AZ 9260 is done for mold formation (Fig. 5i). A 2-µm-thick gold bridge and CPW lines are patterned using a LIGA-like process as shown in Fig. 3j. Then, an AZ 9260 mold is removed in the acetone, as shown in Fig. (Fig. 3k).

The HiPR 6517 sacrificial layer is detached from underneath the bridge using wet etching. Piranha solution in a 3:1 ratio is used to eradicate the sacrificial layer. The RF MEMS switch's bridge structure is finally released with a critical point dryer (CPD), as shown in Fig. 3l. The optical image of the released wafer is shown in Fig. 4.

Fig. 4
figure 4

Top view of the released wafer after vertical placement.

Full size image

The devices located at the bottom side are damaged in the released wafer, as shown in Fig. 4. Hence, the yield of the switches degrades. The reason for this damage is the non-uniformity in the sacrificial layer. The HiPR recipe is optimized to make it uniform across the wafer and improve the yield.

Photoresist Uniformity Optimization

The thickness uniformity of the spin-coated sacrificial layer plays a significant role in switch fabrication. The spin-coater leveling and cleaning of the substrate are done to achieve a uniform thickness profile of HiPR 6517. Further, the photoresist's thickness is measured over the 25 points on a 2-inch diameter substrate after pre-bakinng. The 2-D contour map is plotted for the visualization of the thickness uniformity. The points where the thickness has been measured are also marked in the contour maps. The contour map of the wafer is shown in Fig. 5.

Fig. 5
figure 5

Thickness profiling of the vertically placed wafer.

Full size image

From Fig. 5, it is observed that the thickness at the bottom of the wafer is high. The value of the minimum measured thickness of the HiPR 6517 sacrificial layer at the top side of the wafer is 2.1446 µm, and the thickness measured at the bottom side of the wafer is 2.3355 µm. The total thickness variation (TTV) of the photoresist is 0.1939 µm. The non-uniformity in the vertically placed wafer is due to the slow drying process of the HiPR photoresist at low temperature (at 18° C). At this temperature, the drying process of the photoresist is slow, and it starts to reflow. Hence, due to gravity, the photoresist accumulates at the lower side of the wafer, which leads to higher TTV.

Because of the greater thickness in the lower side of the wafer, the photoresist could not be resolved entirely, and some traces of the photoresists are left, which results in poor adhesion to subsequent layers. Hence, the structures are lifted off from that region during the final release, as shown in Fig. 4.

The best way to resolve this challenge is to place the wafers in a horizontal position after the photoresist coating for uniform thickness, as shown in Fig. 6.

Fig. 6
figure 6

Horizontal placement of the wafer.

Full size image

The HiPR 6517 is spin-coated with the same optimized recipe. However, the wafers are placed horizontally instead of vertically. The thickness of the photoresist is measured over the 25 points to plot the counter map, as shown in Fig. 7. The measured thickness ranges from 2.1569 µm to 2.1901 µm, and the TTV of the spin-coated HiPR 6517 layer is 0.0332 µm.

Fig. 7
figure 7

Thickness profiling of the horizontally placed wafer.

Full size image

The TTV of the horizontally placed wafer is five times less than the TTV of the vertically placed wafer. Hence, no residues remain after the HiPR 6517 developing process of the horizontally placed wafer. Thus, the wafer is released without damaging the devices, as shown in Fig. 8. The SEM micrograph of the final released capacitive SPST RF MEMS switch is shown in Fig. 9.

Fig. 8
figure 8

Top view of the released wafer after horizontal placement.

Full size image
Fig. 9
figure 9

SEM image of the fabricated capacitive SPST RF MEMS Switch.

Full size image

Result and Discussion

The SEM image of the fabricated and released capacitive SPST RF MEMS switch is shown in Fig. 9. RF measurement and mechanical analysis of the switch are performed. A laser Doppler vibrometer (LDV) is used to measure the resonance frequency of the released bridge. The first resonating mode of the beam is at 12.33 kHz, shown in Fig. 10. A C-V analysis is carried out to measure the pull-in voltage of the switch by using an impedance analyzer, and a hysteresis curve is plotted for the switch, as shown in Fig. 11. The switch actuates at 13 V, and the hold-on voltage is 7 V. The RF parameters of the switch are measured by using a vector network analyser (VNA), and results are presented in Fig. 12. The switch's isolation at 24.5 GHz is about − 35 dB, and insertion loss is better than − 1 dB.

Fig. 10
figure 10

LDV measurement of the capacitive SPST RF MEMS switch.

Full size image
Fig. 11
figure 11

Pull-in voltage measurement of the capacitive SPST RF MEMS switch.

Full size image
Fig. 12
figure 12

RF measurement of the capacitive SPST RF MEMS switch.

Full size image

The characteristics of the switch for both vertically and horizontally placed wafers are almost similar. However, the yield of the devices is increased in the horizontally placed wafer compared to vertical placement.

Conclusion

In this work, low-temperature photoresist HiPR 6517 is optimized as a sacrificial layer rather than process incompatible metallic and high-temperature dielectric materials for fabricating MEMS devices. In the standard vertical placement of wafers, the thick photoresist reflows and results in non-uniformity across the wafer. The bottom side of the wafer has a greater thickness compared to the top, which damages the devices located at the bottom side of the wafer. To overcome this issue, the wafers are placed horizontally to achieve uniform thickness. The TTV of the vertically placed wafer is 0.1939 µm, while the TTV of the horizontally placed wafer is 0.0332 µm. So, the uniformity of the horizontally placed wafer increased more than 500%. Hence, the yield of the devices is also increased using horizontal placement. The fabricated switch using the optimized recipe of low-temperature thick photoresist shows excellent characteristics. The measured actuation voltage of the switch is 13 V, and the mechanical resonant frequency is 12.32 kHz. The fabricated switch offers isolation and insertion loss better than − 35dB and − 1 dB at 24.5 GHz, respectively.