1 Introduction

The advantages of the wavelet transform over conventional transforms were recognized by Daubechies [1]. The wavelet transformation has become a standard technique in audio signal processing and image compression since Mallat [2] proposed the multiresolution representation of signals based on wavelet decomposition. Two-dimensional (2-D) discrete wavelet transform (DWT) has been adopted in the well-known JPEG 2000 still image compression standard [3].

According to JPEG 2000 standard, source image or its partitions are decomposed into different decomposition levels using a wavelet transform. These decomposition levels contain a number of subbands, which consist of coefficients that describe the horizontal and vertical spatial frequency characteristics of the original image or its partitions. To perform the forward DWT, JPEG 2000 standard utilizes a one-dimensional (1-D) subband decomposition of a 1-D set of samples into low-pass coefficients and high-pass coefficients. The choice of filters is an important issue, since it has been shown by Caglar et al. [4] and by Egger and Li [5, 6] that filters represent an important factor which has the influence on the performance of the decomposition for compression purposes. The default reversible transformation, according to JPEG 2000 standard, is implemented by means of Le Gall’s 5-tap/3-tap filter [7].

The standard supports two filtering modes: a convolution-based mode and a lifting-based mode. Convolution-based filters perform a series of multiplications and additions between low-pass and high-pass filter coefficients and extended 2-D pixels forming a window matrix in case of non-orthogonal filters, or separate horizontal and vertical processing, in case of orthogonal filters. Lifting-based filtering consists of a sequence of alternative updating of pixels with odd indexes with weighted sum of pixels with even indexes and updating of pixels with even indexes with weighted sum of pixels with odd indexes.

DWT implemented by convolution requires a high number of arithmetic computations and an extensive usage of logic and memory resources, which is not desirable for high-speed and low-power image processing applications. Filter circuits for efficient hardware implementation of DWT, which are mainly convolution-based, are proposed by Parhi and Nishitani [8], Wu and Chen [9], Cheng and Parhi [10], Usha and Chilambuchelvan [11] and Ghantous and Bayoumi [12].

Lifting-based DWT filters have many advantages compared to convolution-based filters, such as simpler design, less required logic and memory resources, lower computational complexity and lower power consumption. The lifting scheme also allows “in-place” computation of DWT as it can be seen in many existing implementations. Various efficient hardware implementations of lifting schemes have been developed.

A direct mapped filter design was implemented by Liu et al. [13, 14]. However, for 5/3 filter and a single read port memory, the odd and even samples are read serially in alternate clock cycles and buffered, which slows down the overall pipelined filter design by 50%. Liu et al.’s [13, 14] design was further improved by folding the last two pipeline stages into the first two stages by Lian et al. [15]. For 5/3 filter, no folded computing is necessary since there is only one stage for lifting-based operations. The generalized filter design proposed by Andra et al. [16] is an example of a highly programmable design that can support a large set of filters, including 5/3 filter. Although some conventional lifting-based filter designs require fewer arithmetic operations, they sometimes have long critical paths. Solving this issue by pipelining would result in a significant increase in the number of registers. However, Huang et al.’s [17] flipping design solved timing accumulation problem in an efficient way. Multiply-and-accumulate-based programmable filter design has been proposed by Chang et al. [18]. Unlike the most of traditional DWT filter designs which compute the next level of decomposition upon completion of the previous level of decomposition, Liao et al.’s [19] recursive DWT filter design is able to process multiple levels of decomposition simultaneously. Liao et al. [20] presented a dual-scan filter design for DWT which processes two independent data streams together using shared functional blocks in an interleaved fashion. A filter-independent DSP-type parallel design, which can be programmed to support a wide range of filters, including 5/3 filter, has been proposed by Martina et al. [21]. Recently, Meher et al. [22] presented an optimized adder-based formulation for low-area and low-power implementation of 1-D DWT using 5/3 filters.

As it has been shown by Acharya and Chakrabarti [23], the folded design [15] is the simplest while the DSP-based design [21] is the most complex in terms of hardware complexity. Designs [13, 16–20, 22] have comparable hardware complexity and differ mostly in the number of registers and adders. The control complexity of the filter design [13] is very simple, unlike the control complexity of the designs [20, 21]. Other mentioned designs have the moderate control complexity. In terms of timing performance, the filter designs [13, 15–18] have the highest throughput. Design [19] has fewer cycles but its clock period is higher, while filter design [17] has the lowest computation delay. All designs except [19] compute all the outputs of one level of decomposition before starting computations of the next level, while only design [19] interleaves the computations of the higher levels with those of the first level. That is the reason why memory requirements for [19] are lower than for the others.

Among mentioned lifting-based DWT filter designs, in terms of complexity of basic building blocks (1-D 5/3 filter blocks), those proposed in [13–16, 22] have the simplest realizations, which leads to important savings in logic and memory resources. Designs presented in [17–21] have greater hardware complexity, but also greater flexibility including the support for a wide range of different types of filters.

Several 2-D DWT hardware architectures have recently been proposed. A straightforward implementation of the 2-D DWT (direct architecture), as well as the implementation which employs two systolic array filters and two parallel filters (systolic-parallel architecture), has been suggested by Vishwanath et al. [24]. Chrysafis and Ortega [25] proposed the line-based architecture for 2-D DWT with reduced use of memory resources. Chang et al.’s [18] filter design is also employed in the appropriate programmable 2-D DWT architecture. Wu and Chen [9] used their convolution-based filter design and developed a line-based architecture for the 2-D DWT in which they employed polyphase decomposition technique and the coefficient folding technique in order to increase the hardware utilization and to decrease the total computing time. Andra et al. [16] utilized their generalized filter design and developed block-based implementation of four-processor architecture for 2-D DWT which is highly programmable, but which requires a large embedded memory. Liao et al. [19] proposed the lifting-based 2-D DWT recursive architecture (RA) which can process multiple levels of decomposition simultaneously and the 2-D DWT dual-scan architecture (DSA) [20] which uses an interleaving scheme for multilevel decomposition with reduced size of memory and decreased number of memory accesses. A hybrid of level-by-level and line-based 2-D DWT architecture in which the image is scanned into the row processor in a raster format was proposed by Barua et al. [26]. Pipelined architecture (PA), efficient for high-speed and/or low-power applications, has been developed by Xiong et al. [27]. Xiong et al. [28] have also proposed fast 2-D DWT architecture (FA) mainly composed of two horizontal filter modules and one vertical filter module, which employs parallel and pipeline techniques, and high-speed 2-D DWT architecture (HA) which exploits parallelism among four subband transforms. The block-based design of 2-D DWT architecture which eliminates the requirement of frame buffer, but which uses larger on-chip memory and has significant overhead due to its input interface units, was presented by Mohanty and Meher [29]. Parallel multilevel lifting-based 2-D DWT architecture with a single processing unit which calculates both predict and update values was proposed by Aziz and Pham [30]. Hsia et al. [31] have designed memory efficient 2-D DWT architecture, which exploits mixed row-wise and column-wise signal flow. For computing 2-D DWT, Darji et al. [32] presented high-performance folded multilevel architecture (FMA) and pipelined multilevel architecture (PMA) with dual-pixel scanning method with higher operational frequency, lower latency and lower power consumption in comparison with other existing DWT architectures with the same specifications. In the same paper, hardware efficient recursive multilevel architecture (RMA) is also described. Highly efficient lifting-based 2-D DWT architecture based on the parallel and folding scheme processing was proposed by Hsia et al. [33, 34].

In terms of memory requirements, 2-D DWT architectures [18, 19, 25, 27, 29, 30], PMA [32,33,34] require lower memory capacity compared to the other architectures and do not require off-chip memory at all. Computing time for 2-D DWT architectures [9, 16, 20, 25–28, 32–34] is lower than for the other mentioned architectures. The lowest output latency is present in systolic-parallel architecture [24] and architectures [28, 29, 31, 32], while output latency of other architectures is several times higher, but still comparable with mentioned ones. In terms of hardware utilization efficiency, the best performances (efficiency close to or approximately equal to 1) are present in architectures [9, 16, 26, 28], FMA [32,33,34], while other mentioned architectures have efficiency lower than 1.

This paper is structured as follows. Section 2 describes the design of the novel 1-D DWT 5/3 filter. Section 3 presents comparison with other state-of-the-art 1-D filter designs. Analysis, synthesis and fitting results obtained in implementation process for our and state-of-the-art 1-D filter designs are described and compared in Sect. 4. In Sect. 5, 2-D DWT 5/3 architecture, which exploits 1-D filter design from Sect. 2, is proposed. Complexity and performance comparisons with other 2-D DWT 5/3 architectures are described in Sect. 6. Finally, a brief conclusion is stated in Sect. 7.

Some initial research, on which this paper is based on, has been presented in [35, 36].

2 Design of the 1-D novel forward DWT 5/3 filter

Many of state-of-the-art 1-D forward DWTs provide low-pass filtering with transfer function H0(z) and downsampling by two, in the upper branch in Fig. 1, as well as high-pass filtering with transfer function H1(z) followed by downsampling by two, in the lower branch in Fig. 1. Since these filters are followed by decimators which discard samples, final coefficients y′0[n] comprise every second sample from the array of low-pass filtered coefficients y0[n] and coefficients y′1[n] comprise every second sample from the array of high-pass filtered coefficients y1[n]. This actually means that each second time slot used by low-pass H0(z) or high-pass H1(z) filter for the generation of coefficients has been wasted, together with logic and memory resources.

Fig. 1
figure 1

State-of-the-art 1-D forward DWT

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The approach disclosed in this paper is based on the idea that logic and memory resources of 1-D forward DWT 5/3 filter, which are wasted in state-of-the-art approach from Fig. 1, must be used for generating the coefficients which will not be rejected. That means, no coefficients generated by the filter may be discarded, despite the decimation process.

Namely, unlike the state-of-the-art DWTs from Fig. 1 which pass further every even coefficient generated by H0(z), while discarding every odd coefficient generated by H0(z) and pass further every even coefficient generated by H1(z), while discarding every odd coefficient generated by H1(z), our filter uses both even time slots and odd time slots for generating and further passing the transformation coefficients (Fig. 2).

Fig. 2
figure 2

Using time slots which are wasted in state-of-the-art solutions

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In this concept, even time slots are used for generating low-pass coefficients, while odd time slots are used for generating high-pass coefficients. Therefore, the filter utilizes logic and memory resources which have been wasted in state-of-the-art designs from Fig. 1.

Additional savings of memory resources in the filter, compared to state-of-the-art DWTs from Fig. 1, are obtained by using the same memory blocks (or registers) for the process of generating low-pass and high-pass coefficients, which is feasible since low-pass and high-pass coefficients are generated in different time slots. However, since the transfer function of the low-pass filter is different from the transfer function of the high-pass filter, our approach requires non-stationary topology for the forward DWT 5/3 filter. The first filter configuration should be applied in even time slots (when low-pass coefficients are generated), and the second filter configuration should be applied in odd time slots (when high-pass coefficients are generated). The configuration change will be accomplished using the switches. The same memory blocks (or registers) are reused for generating both low-pass and high-pass coefficients due to feed-forward and feedback paths.

Schematic block diagram of the novel forward DWT 5/3 filter is shown in Fig. 3. Each unit delay (a block with z−1 operator) is implemented using the appropriate register.

Fig. 3
figure 3

Schematic block diagram of the novel forward DWT 5/3 filter

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Control signal c controls four switches responsible for providing non-stationary filter topology. Time diagram of control signal c is shown in Fig. 4.

Fig. 4
figure 4

Time diagram of control signal c in presented filter

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Whenever the control signal c is at low level (c = 0), for every input sample x[n] with even index n = 2k, two upper switches are opened while two lower switches are closed.

Whenever the control signal c is at high level (c = 1), for every input sample x[n] with odd index n = 2k + 1, two upper switches are closed while two lower switches are opened.

The set of equations which describes signals inside the filter in time instances from n = 0 to n = 4 is presented in Table 1.

Table 1 Equations for signals inside the filter in time instances from n = 0 to n = 4
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Based on the equations for time instance n = 4, y[n] can be expressed as:

$$\begin{aligned} y[n] &= x[n - 2] + p \cdot s \cdot x[n - 2] + s \cdot x[n - 3] \\ & \quad + q \cdot s \cdot x[n - 4] + r \cdot x[n - 1] \\ & \quad + r \cdot q \cdot x[n - 2] + r \cdot p \cdot x[n] \\ \end{aligned}$$
(1)

which finally leads to:

$$\begin{aligned} y[n] &= p \cdot r \cdot x[n] + r \cdot x[n - 1] \\ & \quad + (1 + p \cdot s + q \cdot r) \cdot x[n - 2] \\ & \quad + s \cdot x[n - 3] + q \cdot s \cdot x[n - 4] \\ \end{aligned}$$
(2)

From now on, this computation is repeated on every subsequent cycle.

For every even index n, y[n] satisfies Eq. (2), which has the same form as Eq. (3) describing H0(z) in JPEG 2000 standard.

$$\begin{aligned} y_{0} [n] &= - \frac{1}{8}x[n] + \frac{1}{4}x[n - 1] + \frac{3}{4}x[n - 2] \\ & \quad + \frac{1}{4}x[n - 3] - \frac{1}{8}x[n - 4] \end{aligned}$$
(3)

Equations (2) and (3) become identical if p, q, r and s satisfy conditions (4):

$$\begin{aligned} 1 + p \cdot s + q \cdot r &= \frac{6}{8}, \\ p \cdot r &= - \frac{1}{8}, \\ q \cdot s &= - \frac{1}{8}, \\ r = s &= \frac{1}{4}, \\ p = q &= - \frac{1}{2} \\ \end{aligned}$$
(4)

For every odd index n, y[n] satisfies Eq. (5), which has the same form as Eq. (6) describing H1(z) in JPEG 2000 standard.

$$y[n] = p \cdot x[n - 1] + x[n - 2] + q \cdot x[n - 3]$$
(5)
$$y_{1} [n] = - \frac{1}{2}x[n - 1] + x[n - 2] - \frac{1}{2}x[n - 3]$$
(6)

Equations (5) and (6) become identical if p and q satisfy condition (7), which is in line with the condition (4):

$$p = q = - \frac{1}{2}$$
(7)

Finally, by adding the values from expressions (4) and (7) to the product operators shown in Fig. 3, our filter obtains its final form. This filter generates low-pass filtered coefficients y[n] for even index n and high-pass filtered coefficients y[n] for odd index n.

The input samples x[n] are low-pass filtered within time slots with even indexes n = 2k without any need for downsampling by two, in order to produce output samples y0[n], which actually represent the output samples y[n] with even indexes n = 2k (8).

$$\begin{aligned} y_{0} [n] &= - \frac{1}{8}x[n] + \frac{1}{4}x[n - 1] + \frac{3}{4}x[n - 2]\\ & \quad + \frac{1}{4}x[n - 3] - \frac{1}{8}x[n - 4] \end{aligned}$$
(8)

The input samples x[n] are high-pass filtered within time slots with odd indexes n = 2k + 1 without any need for downsampling by two, in order to produce output samples y1[n], which actually represent the output samples y[n] with odd indexes n = 2k + 1 (9).

$$y_{1} [n] = - \frac{1}{2}x[n - 1] + x[n - 2] - \frac{1}{2}x[n - 3]$$
(9)

The transfer function of the filter is fully appropriate to the Le Gall’s 5-tap/3-tap filter [7] which is used as default filter for reversible transformation in JPEG 2000 standard.

Multipliers in our filter can be made as permanently shifted hardware connections between output and input bit lines, thus removing any necessity for hardware multipliers.

In order to keep the number of wavelet coefficients the same as the number of input data samples, symmetric extension of input samples at image boundaries, which is well-known solution, can be used.

3 Comparison with other 1-D forward DWT 5/3 filter designs

In order to illustrate the advantages of described filter (Fig. 3), its design is compared with state-of-the-art convolution-based forward DWT 5/3 filter design [8–12, 25] (shown in Fig. 5) and with the most efficient among the state-of-the-art lifting-based forward DWT 5/3 filter designs [13–16, 26, 27, 33] (shown in Fig. 6) in terms of hardware complexity. Also, some other 1-D DWT 5/3 filter designs, such as [22, 28, 30] are included in comparison (these designs are not presented in figures since they have greater complexity than designs shown in Figs. 3, 5, 6). The design proposed in [16] is a bit more complex than it is shown in Fig. 6, but it can be reduced to the form in Fig. 6 after removing pipeline registers. Comparison with designs proposed in [17–21] is not presented, since these designs have greater hardware complexity, as a price paid for greater flexibility including the support for a wide range of different types of filters, as it has been shown in [23]. Also, comparison with some other 1-D DWT 5/3 filter designs, which are used as basic building blocks in 2-D DWT architectures described in Sect. 1, is not presented since those filter designs have greater hardware complexity as a compromise made in order to achieve greater flexibility of 2-D DWT architecture.

Fig. 5
figure 5

State-of-the-art convolution-based 5/3 filter design: low-pass filter (a) and high-pass filter (b)

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Fig. 6
figure 6

State-of-the-art lifting-based 5/3 filter design

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Actual implementation of the proposed filter from Fig. 3 is shown in Fig. 7. Four switches in the proposed filter design are implemented using 3 multiplexers in total. The part of the circuit which contains the upper left switch is implemented using the left multiplexer, the part of the circuit which contains the lower right switch is implemented using the right multiplexer, and finally, the part of the circuit which contains the lower left switch and the upper right switch is implemented using the multiplexer in the middle, since these switches are connected to the same node.

Fig. 7
figure 7

Implementation of the novel forward DWT 5/3 filter

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Table 2 provides the list of used hardware components and estimated critical path delay (where TA and TMUX represent the delay time of the adder and multiplexer, respectively) for aforementioned filter designs. It can be seen that the proposed filter requires the lowest memory size. State-of-the-art lifting-based 5/3 filter design (shown in Fig. 6) requires two input data samples x0[n] and x1[n] at the filter input at the same clock cycle, and generates, after processing delay, two resulted data samples y0[n] and y1[n] at the filter output at the same clock cycle. However, if input data samples are being received serially in alternate clock cycles, additional logic circuit at the filter input is necessary in order to ensure proper rearrangement (i.e., timing adjustments) of input samples, so that lifting-based 5/3 filter design could process them properly. Also, if output data samples have to be generated serially in alternate clock cycles, additional logic circuit at the filter output is necessary in order to ensure that. Similarly, state-of-the-art convolution-based 5/3 filter design (shown in Fig. 5) requires additional logic circuit at the filter output, in case when output data samples have to be generated serially in alternate clock cycles. The proposed filter design does not require any additional logic for input data splitting when the odd and even input samples are being received serially in alternate clock cycles, nor any additional logic for output data combining when the odd and even output coefficients have to be generated serially in alternate clock cycles.

Table 2 Used hardware components for 1-D forward DWT 5/3 filters
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It also can be seen that the convolution-based design and the proposed filter design have the shortest estimated critical path delays, compared to other designs, while the lifting-based design has the longest estimated critical path delay.

4 Experimental results for 1-D forward DWT 5/3 filter designs

In order to carry out functional verification, presented filter has been simulated with 24-bit two’s complement fixed point number format, with 12 integer bits and 12 fractional bits using Altera Quartus II software. This data format has been chosen since it ensures correct representation of generated coefficients for at least 4 levels of decomposition. Simulation results confirmed the perfect match between our filter and Le Gall’s 5/3 filter in terms of generated output coefficients.

The presented filter design, the state-of-the-art convolution-based filter design, the state-of-the-art lifting-based filter design, as well as some other recently published 5/3 filter designs, have been implemented for 24-bit data samples usage in Altera FPGA EP4CE115F29I8L chip. The analysis, synthesis and fitting results obtained in the implementation process using Altera Quartus II 10.0 software are represented in Table 3. The second column contains data for state-of-the-art convolution-based forward DWT 5/3 filter design [8–12, 25], the third column contains data for the most efficient state-of-the-art lifting-based forward DWT 5/3 filter design [13–16, 26, 27, 33] without any additional logic for input data splitting nor for output data combining, while the fourth column contains data for the most efficient state-of-the-art lifting-based forward DWT 5/3 filter design [13–16, 26, 27, 33] with additional logic for input data splitting and output data combining. The fifth, sixth and seventh column contain the results for 5/3 filter designs from [22, 28, 30], respectively. Finally, the eighth column represents the results for the filter design described in this paper.

Table 3 Synthesis results of 1-D forward DWT 5/3 filters in Altera FPGA EP4CE115F29I8L
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Fitting results clearly show that in terms of used registers, the presented filter is 71% simpler than convolution-based 5/3 filter design, 33% simpler than lifting-based 5/3 filter design without splitting and combining parts, and 50% simpler than lifting-based design with splitting and combining parts. The proposed filter design utilizes 50% less memory resources than recently published filter designs from [22, 30].

In terms of used logic elements, the presented filter is 37% simpler than convolution-based 5/3 filter design, 28% simpler than 5/3 filter design from [22], while has the same complexity as lifting-based 5/3 filter design without splitting and combining parts (although the theoretical estimations from Table 2 show that the proposed design has slightly higher complexity than the lifting-based design in terms of total number of adders and multiplexers, the proposed design is more suitable for optimizations made by the compiler during compilation process which leads to the same number of utilized logic elements, since the compiler merges the multiplexers with neighboring adders and makes the optimized combinational logic circuits). However, in cases when additional logic for input data splitting and for output data combining is needed, described design is 17% simpler than lifting-based design in terms of used logic elements.

Maximum operating frequency is 7% higher for presented filter in comparison with convolution-based 5/3 filter, and between 70 and 77% higher in comparison with lifting-based 5/3 filter (depending on whether lifting-based design has additional parts for data splitting/combining or not). Presented filter design has 44% higher maximum operating frequency than recently published filter design from [22]. The convolution-based 5/3 filter design and the presented filter design have the shortest critical path delay, filter design from [22] has 35% longer critical path delay, while lifting-based design with splitting and combining parts has 60% longer critical path delay and lifting-based design without splitting and combining parts has 65% longer critical path delay. Although the estimated critical path delay for the proposed design is slightly longer than for the convolution-based design, since the compiler merges the multiplexers with neighboring adders and makes the optimized combinational logic circuits for the proposed design, these two designs have the same resulting critical path delay.

The proposed filter design allows 8% higher throughput than convolution-based design, 70% higher throughput than lifting-based design with splitting and combining parts and 44% higher throughput than recently published filter design from [22]. However, due to ability to generate two output samples at the same clock cycle, the lifting-based design without splitting and combining parts allows the highest throughput (13% higher than the proposed filter design).

Also, described filter design has the lowest total power dissipation, compared with other designs.

5 The proposed 2-D DWT 5/3 architecture

The overall structure of the proposed 2-D DWT 5/3 architecture with J = 7 decomposition levels, which exploits 1-D DWT filter design presented in Sect. 2, is shown in Fig. 8. Seven levels of decomposition have been chosen since that number of levels ensures the excellent compression quality for high-definition (HD) resolution images (1920 × 1080 pixels).

Fig. 8
figure 8

Proposed 2-D DWT 5/3 architecture

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Input data samples p[m, n] are received by “HF Input Register Level 1” and then horizontally filtered by “Horizontal Filter Level 1” line by line. All horizontal filters are implemented as 1-D DWT filters described in Sect. 2. As a result, coefficients yA[m, n] are generated:

$$y_{A} [m,n] = \left\{ {\begin{array}{*{20}l} {y_{H}^{(1)} [m,k],} \hfill & {{\text{for}}\;n = 2k} \hfill \\ {y_{L}^{(1)} [m,k],} \hfill & {{\text{for}}\;n = 2k + 1} \hfill \\ \end{array} } \right.$$
(10)

where y (1) H [m, k] represent high-pass horizontally filtered coefficients at level 1, and y (1) L [m, k] represent low-pass horizontally filtered coefficients at level 1. Since 1-D DWT filter from Sect. 2 generates high-pass coefficient as first valid coefficient, in notation in Eq. (10) yA[m, 0] represents the high-pass coefficient.

Coefficients yA[m, n] are then vertically filtered by “Vertical Filter A,” producing coefficients zA[m, n]:

$$z_{A} [m,n] = \left\{ {\begin{array}{*{20}l} {z_{LH}^{(1)} [m,k],} \hfill & {{\text{for}}\;m = 2l\;{\text{and}}\;n = 2k} \hfill \\ {z_{LL}^{(1)} [m,k],} \hfill & {{\text{for}}\;m = 2l\;{\text{and}}\;n = 2k + 1} \hfill \\ {z_{HH}^{(1)} [m,k],} \hfill & {{\text{for}}\;m = 2l + 1\;{\text{and}}\;n = 2k} \hfill \\ {z_{HL}^{(1)} [m,k],} \hfill & {{\text{for}}\;m = 2l + 1\;{\text{and}}\;n = 2k + 1} \hfill \\ \end{array} } \right.$$
(11)

Resulting coefficients at level 1: z (1) LH [m, n], z (1) LL [m, n], z (1) HH [m, n] and z (1) HL [m, n] belong to level 1 subbands LH, LL, HH and HL, respectively.

Coefficients z (1) LL [m, n] are received one by one by “HF Input Register Level 2,” then horizontally filtered by “Horizontal Filter Level 2” and routed through a multiplexer, generating coefficients yB[m, n]:

$$y_{B} [m,n] = \left\{ \begin{array}{l} y_{H}^{(j)} [m,k],\quad {\text{for}}\;n = 2k \hfill \\ y_{L}^{(j)} [m,k],\quad {\text{for}}\;n = 2k + 1 \hfill \\ \end{array} \right.$$
(12)

where y ( j) H [m, k] represent high-pass horizontally filtered coefficients at level j (j = 2, 3, …, 7), and y ( j) L [m, k] represent low-pass horizontally filtered coefficients at level j (j = 2, 3, …, 7).

Coefficients yB[m, n] are then vertically filtered by “Vertical Filter B,” producing coefficients zB[m, n]:

$$z_{B} [m,n] = \left\{ {\begin{array}{*{20}l} {z_{LH}^{(j)} [m,k],} \hfill & {{\text{for}}\;m = 2l\;{\text{and}}\;n = 2k} \hfill \\ {z_{LL}^{(j)} [m,k],} \hfill & {{\text{for}}\;m = 2l\;{\text{and}}\;n = 2k + 1} \hfill \\ {z_{HH}^{(j)} [m,k],} \hfill & {{\text{for}}\;m = 2l + 1\;{\text{and}}\;n = 2k} \hfill \\ {z_{HL}^{(j)} [m,k],} \hfill & {{\text{for}}\;m = 2l + 1\;{\text{and}}\;n = 2k + 1} \hfill \\ \end{array} } \right.$$
(13)

Resulting coefficients at level j: z ( j) LH [m, n], z ( j) LL [m, n], z ( j) HH [m, n] and z ( j) HL [m, n] belong to level j (j = 2, 3, …, 7) subbands LH, LL, HH and HL, respectively.

Coefficients z ( j) LL [m, n] are received one by one by “HF Input Register Level j,” then horizontally filtered by “Horizontal Filter Level j” (j = 3, …, 7) and multiplexed with other coefficients generated by horizontal filters from other levels 2–7, producing coefficients yB[m, n].

The time diagram which describes the dynamics of 2-D filtering at the beginning of even lines (starting from 0) is presented in Fig. 9. The time diagram shows the lines in first three levels of decomposition in case when lines at each presented level are even lines (since only in even lines coefficients from LL subbands are generated, and only these coefficients are further filtered at the next decomposition level).

Fig. 9
figure 9

Time diagram of 2-D DWT at the beginning of even lines

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The process of horizontal filtering of the line starts as soon as the first pixel (i.e., input data sample) in line is received by 2-D DWT system (in time instance n = 0 as denoted in Fig. 9). The first valid coefficient produced by horizontal filter at level 1, the high-pass coefficient y (1) H [m(1), 0], appears in time instance n = 3. It is followed by the first valid low-pass coefficient y (1) L [m(1), 0] in the next time slot. The third valid coefficient produced by horizontal filter at level 1 is the high-pass coefficient (y (1) H [m(1), 1]). It is followed by the low-pass coefficient y (1) L [m(1), 1] in the next time slot. The other horizontally filtered coefficients are produced in subsequent cycles.

As soon as horizontally filtered coefficient at level 1 is produced, it is being vertically filtered at the same level in the next time slot. Every even (starting from 0) both horizontally and vertically filtered coefficient in the line belongs to the subband LH (z (1) LH [m(1), n(1)]), while every odd both horizontally and vertically filtered coefficient in the line belongs to the subband LL (z (1) LL [m(1), n(1)]).

The process of horizontal filtering of the line at level 2 starts as soon as the first coefficient from subband LL from level 1 (z (1) LL [m(1), 0]) is received by “Horizontal Filter Level 2.” The first valid coefficient produced by that filter, the high-pass coefficient y (2) H [m(2), 0], appears in time instance n = 10. It is followed by the first valid low-pass coefficient y (2) L [m(2), 0] in time slot n = 12. The third valid coefficient produced by horizontal filter at level 2 is the high-pass coefficient (y (2) H [m(2), 1]) in time slot n = 14, followed by the low-pass coefficient y (2) L [m(2), 1] in time slot n = 16. The other horizontally filtered coefficients at level 2 are produced in every second cycle.

As soon as horizontally filtered coefficient at level 2 is produced, it is being vertically filtered at the same level in the next time slot. Every even (starting from 0) both horizontally and vertically filtered coefficient in the line belongs to the subband LH (z (2) LH [m(2), n(2)]), while every odd both horizontally and vertically filtered coefficient in the line belongs to the subband LL (z (2) LL [m(2), n(2)]).

The horizontal filtering of the line at level 3 starts once the first coefficient from subband LL from level 2 (z (2) LL [m(2), 0]) is received by “Horizontal Filter Level 3.” The first valid coefficient produced by that filter, the high-pass coefficient y (3) H [m(3), 0], appears in time instance n = 23. It is followed by the first valid low-pass coefficient y (3) L [m(3), 0] in time slot n = 27. The third valid coefficient produced by horizontal filter at level 3 is the high-pass coefficient (y (3) H [m(3), 1]) in time slot n = 31, followed by the low-pass coefficient y (3) L [m(3), 1] in time slot n = 35. The other horizontally filtered coefficients at level 3 are produced in every fourth time slot. Although these horizontally filtered coefficients could be generated one time slot earlier (i.e., in time instances n = 22, n = 26, n = 30 and n = 34), this scenario is avoided in order to utilize the same vertical filter for all coefficients at levels from 2 to 7, which is possible due to the appropriate interleaving of time slots generating vertically filtered coefficients.

As soon as horizontally filtered coefficient at level 3 is produced, it is being vertically filtered at the same level in the next time slot. Every even both horizontally and vertically filtered coefficient in the line belongs to the subband LH (z (3) LH [m(3), n(3)]). Every odd both horizontally and vertically filtered coefficient in the line belongs to the subband LL (z (3) LL [m(3), n(3)]).

The described pattern of 2-D filtering at the beginning of even lines continues at all other levels (j = 4, 5, 6 and 7), which has not been shown in simplified Fig. 9. The horizontal filtering of the line at the level starts once the first coefficient from the subband LL from previous level is received by the horizontal filter at current level. As soon as horizontally filtered coefficient at current level is produced, it is being vertically filtered at the same level in the next time slot. Coefficients at level 4 are generated on every eighth time slot. Coefficients at level 5 are generated on every sixteenth time slot. Coefficients at level 6 are generated on every thirty-second time slot, etc.

Starting time instance for the generation of the first coefficient at each level is chosen on the manner which allows appropriate interleaving of time slots when vertically filtered coefficients are generated. This approach allows using one vertical filter for level 1 (“Vertical Filter A”), and another vertical filter for all other decomposition levels (“Vertical Filter B”), since any overlapping of time slots when “Vertical Filter B” is used has been avoided.

The time diagram which illustrates the dynamics of 2-D filtering at the end of even lines of HD resolution images, for lines whose beginning is shown in Fig. 9, is presented in Fig. 10. For level 1 of decomposition, the pattern of filtering is the same as at the beginning of the line. For all other levels of decomposition, the pattern of filtering is the same as at the beginning of the line until the time slot when the last coefficient from LL subband at previous level is generated. After that time slot, all remaining coefficients at current level of decomposition are generated at successive time slots.

Fig. 10
figure 10

Time diagram of 2-D DWT at the end of even lines

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The time diagram which describes the dynamics of 2-D filtering at the beginning of odd lines (starting from 0) is presented in Fig. 11.

Fig. 11
figure 11

Time diagram of 2-D DWT at the beginning of odd lines

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The pattern of filtering is almost the same as in case of filtering at the beginning of even lines. Only two differences can be noticed. First, every even (starting from 0) both horizontally and vertically filtered coefficient in the line belongs to the subband HH (z (1) HH [m(1), n(1)]), while every odd both horizontally and vertically filtered coefficient in the line belongs to the subband HL (z (1) HL [m(1), n(1)]). Second, the first level of decomposition is always the only level of decomposition, since neither the coefficients from HH subband nor the coefficients from HL subband are further filtered at the next decomposition level.

The time diagram which illustrates the dynamics of 2-D filtering at the end of odd lines of HD resolution images, for lines whose beginning is shown in Fig. 11, is presented in Fig. 12. The pattern of filtering is the same as at the beginning of the line. Also, the first level of decomposition is always the only level of decomposition, since neither the coefficients from HH subband nor the coefficients from HL subband are further filtered at the next decomposition level.

Fig. 12
figure 12

Time diagram of 2-D DWT at the end of odd lines

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The illustration of the beginning of line-wise filtering in the proposed 2-D DWT architecture is shown in Fig. 13.

Fig. 13
figure 13

Beginning of line-wise filtering

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After horizontal filtering of line 0 of input image, “Vertical Filter A” generates “temp result 1,” which represents the set of zeros, while simultaneously calculates internal intermediate results later used for generation of valid resulting coefficients at level 1.

After horizontal filtering of line 1 of input image, “Vertical Filter A” generates “temp result 2,” which represents the set of zeros, while simultaneously calculates internal intermediate results later used for generation of valid resulting coefficients at level 1. After horizontal filtering of line 2 of input image, “Vertical Filter A” generates the first line of valid resulting coefficients at level 1.

That line contains coefficients alternately from subbands LH and LL, i.e., notation “z (1) LH [0, n(1)], z (1) LL [0, n(1)]” from Fig. 13 represents the following sequence of coefficients: z (1) LH [0, 0], z (1) LL [0, 0], z (1) LH [0, 1], z (1) LL [0, 1], z (1) LH [0, 2], z (1) LL [0, 2], etc. After horizontal filtering of line 3 of input image, “Vertical Filter A” generates the second line of valid resulting coefficients at level 1. That line contains coefficients alternately from subbands HH and HL, i.e., notation “z (1) HH [1, n(1)], z (1) HL [1, n(1)]” from Fig. 13 represents the following sequence of coefficients: z (1) HH [1, 0], z (1) HL [1, 0], z (1) HH [1, 1], z (1) HL [1, 1], z (1) HH [1, 2], z (1) HL [1, 2], etc. This pattern continues for all remaining lines at level 1, i.e., alternately lines with resulting coefficients from subbands LH and LL and lines with resulting coefficients from subbands HH and HL are generated.

The pattern of line-wise filtering at all other levels is almost the same as for level 1. Only two differences can be noticed: (1) filtering of particular line at current level is performed after valid LL coefficients from corresponding line from previous level are generated, which means that filtering of successive lines at current level is interleaved with every second line of generated coefficients from previous level; (2) after horizontal filtering, the vertical filtering is performed by “Vertical Filter B.”

The illustration of the end of line-wise filtering for HD resolution images in the proposed 2-D DWT architecture is shown in Fig. 14. For level 1 of decomposition, the pattern of filtering is the same as at the beginning of the line-wise filtering. For all other levels of decomposition, the pattern of filtering is the same as at the beginning of the line-wise filtering until the line where the last coefficients from LL subband at previous level are generated. Starting with that line, all remaining lines at current level of decomposition are generated successively one after another without empty time slots between successive lines.

Fig. 14
figure 14

End of line-wise filtering

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The detailed structure of “Vertical Filter A” and “Vertical Filter B” from Fig. 8 is shown in Fig. 15.

Fig. 15
figure 15

Detailed structure of vertical filter

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Equation (14) describe relations between input and output signals for “Zero Line Block”:

$$\begin{aligned} T0[m,n] &= y[m,n] \\ T1[m,n] &= 0 \\ z[m,n] &= 0 \\ \end{aligned}$$
(14)

This block receives the input line 0 as input signal y[m, n]. At the output z[m, n], this block generates “temp result 1” which represents the set of zeros.

Equation (15) describe dependences between input and output signals for “First Line Block”:

$$\begin{aligned} T0[m,n] &= y[m,n] - \frac{1}{2}IT0[m,n] \\ &= y[m,n] - \frac{1}{2}T0[m - 1,n] \\ &= y[m,n] - \frac{1}{2}y[m - 1,n] \\ T1[m,n] &= IT0[m,n] = T0[m - 1,n] = y[m - 1,n] \\ z[m,n] &= IT1[m,n] = T1[m - 1,n] = 0 \\ \end{aligned}$$
(15)

This block receives the input line 1 as input signal y[m, n]. At the output z[m, n], this block generates “temp result 2” which also represents the set of zeros.

Equation (16) describe relations between input and output signals for “Second Line Block,” which receives input signal y[m, n]via the input line 2. The output signal z[m, n] of this block is described with the equation which corresponds to the special form of low-pass Le Gall’s 5/3 filter used for vertical filtering near image boundaries, instead of symmetric extension of input pixels at image boundaries, which is well-known solution. This output signal z[m, n] actually represents the line 0 of valid resulting coefficients generated by vertical filter.

$$\begin{aligned} T0[m,n] &= y[m,n] \\ T1[m,n] &= IT0[m,n] - \frac{1}{2}y[m,n] \\ &= T0[m - 1,n] - \frac{1}{2}y[m,n] \\ &= - \frac{1}{2}y[m,n] + y[m - 1,n] - \frac{1}{2}y[m - 2,n] \\ z[m,n] &= IT1[m,n] + \frac{1}{2}IT0[m,n] - \frac{1}{4}y[m,n] \\ &= T1[m - 1,n] + \frac{1}{2}T0[m - 1,n] - \frac{1}{4}y[m,n] \\ &= - \frac{1}{4}y[m,n] + \frac{1}{2}y[m - 1,n] + \frac{3}{4}y[m - 2,n] \\ \end{aligned}$$
(16)

Equation (17) describe relations between input and output signals for “Odd Line Block,” which receives input signal y[m, n] via any odd input line, except the input line 1 and the last input line. The output signal z[m, n] of this block is described with the equation which corresponds to the high-pass Le Gall’s 5/3 filter. This output signal z[m, n] actually represents any odd line (starting from 0) of valid resulting coefficients except odd lines among last three lines.

$$\begin{aligned} T0[m,n] &= y[m,n] - \frac{1}{2}IT0[m,n] \\ &= y[m,n] - \frac{1}{2}T0[m - 1,n] \\ &= y[m,n] - \frac{1}{2}y[m - 1,n] \\ T1[m,n] &= IT0[m,n] + \frac{1}{4}IT1[m,n] \\ &= T0[m - 1,n] + \frac{1}{4}T1[m - 1,n] \\ &= \frac{7}{8}y[m - 1,n] + \frac{1}{4}y[m - 2,n] - \frac{1}{8}y[m - 3,n] \\ z[m,n] &= IT1[m,n] = T1[m - 1,n] \\ &= - \frac{1}{2}y[m - 1,n] + y[m - 2,n] - \frac{1}{2}y[m - 3,n] \\ \end{aligned}$$
(17)

Equation (18) describe relations between input and output signals for “Even Line Block,” which receives input signal y[m, n] via any even input line, except the input line 0 and input line 2. The output signal z[m, n] of this block is described with the equation which corresponds to the low-pass Le Gall’s 5/3 filter. This output signal z[m, n] actually represents any even line (starting from 0) of valid resulting coefficients except the line 0 and except the even line among last three lines.

$$\begin{aligned} T0[m,n] &= y[m,n] \\ T1[m,n] &= IT0[m,n] - \frac{1}{2}y[m,n] \\ &= T0[m - 1,n] - \frac{1}{2}y[m,n] \\ &= - \frac{1}{2}y[m,n] + y[m - 1,n] - \frac{1}{2}y[m - 2,n] \\ z[m,n] &= IT1[m,n] + \frac{1}{4}IT0[m,n] - \frac{1}{8}y[m,n] \\ &= T1[m - 1,n] + \frac{1}{4}T0[m - 1,n] - \frac{1}{8}y[m,n] \\ &= - \frac{1}{8}y[m,n] + \frac{1}{4}y[m - 1,n] + \frac{3}{4}y[m - 2,n] \\ & \quad + \frac{1}{4}y[m - 3,n] - \frac{1}{8}y[m - 4,n] \\ \end{aligned}$$
(18)

Description of remaining three blocks is given in case when total number of lines within the image is even.

Equation (19) describe relations between input and output signals for “Last Line Block,” which receives input signal y[m, n] via the last input line. The output signal z[m, n] of this block is described with the equation which corresponds to the high-pass Le Gall’s 5/3 filter.

$$\begin{aligned} T0[m,n] &= y[m,n] - IT0[m,n] \\ & = y[m,n] - T0[m - 1,n] \\ & = y[m,n] - y[m - 1,n] \\ T1[m,n] &= IT0[m,n] + \frac{1}{4}IT1[m,n] \\ &= T0[m - 1,n] + \frac{1}{4}T1[m - 1,n] \\ &= \frac{7}{8}y[m - 1,n] + \frac{1}{4}y[m - 2,n] - \frac{1}{8}y[m - 3,n] \\ z[m,n] &= IT1[m,n] = T1[m - 1,n] \\ &= - \frac{1}{2}y[m - 1,n] + y[m - 2,n] - \frac{1}{2}y[m - 3,n] \\ \end{aligned}$$
(19)

Equation (20) describe relations between input and output signals for “Last Plus 1 Line Block,” which is responsible for vertical filtering of the remaining intermediate results IT0[m, n] and IT1[m, n]. The output signal z[m, n] of this block is described with the equation which corresponds to the special form of low-pass Le Gall’s 5/3 filter used for vertical filtering near image boundaries, instead of symmetric extension of input pixels at image boundaries.

$$\begin{aligned} T0[m,n] &= y[m,n] \\ T1[m,n] &= IT0[m,n] = T0[m - 1,n] \\ &= y[m - 1,n] - y[m - 2,n] \\ z[m,n] &= IT1[m,n] + \frac{1}{4}IT0[m,n] \\ &= T1[m - 1,n] + \frac{1}{4}T0[m - 1,n] \\ &= \frac{1}{4}y[m - 1,n] + \frac{5}{8}y[m - 2,n] \\ & \quad + \frac{1}{4}y[m - 3,n] - \frac{1}{8}y[m - 4,n] \\ \end{aligned}$$
(20)

Finally, Eq. (21) describe relations between input and output signals for “Last Plus 2 Line Block,” which is responsible for vertical filtering of the remaining intermediate results IT1[m, n]. The output signal z[m, n] of this block is described with equation which corresponds to the special form of high-pass Le Gall’s 5/3 filter used for vertical filtering near image boundaries, instead of symmetric extension of input pixels at image boundaries. This output signal z[m, n] actually represents the last line of valid resulting coefficients generated by vertical filter.

$$\begin{aligned} T0[m,n] &= y[m,n] \\ T1[m,n] &= IT0[m,n] = T0[m - 1,n] = y[m - 1,n] \\ z[m,n] &= IT1[m,n] = T1[m - 1,n] \\ &= y[m - 2,n] - y[m - 3,n] \\ \end{aligned}$$
(21)

All these equations are derived with respect to the fact that intermediate results T0[m, n] and T1[m, n] are stored in on-chip memory which produces the dependences:

$$\begin{aligned} IT0[m,n] &= T0[m - 1,n] \\ IT1[m,n] &= T1[m - 1,n] \\ \end{aligned}$$
(22)

On-chip memory is shown in Fig. 16. For successful 2-D DWT filtering and decomposition of N × N image, two lines of intermediate results have to be stored in on-chip memory at each level. “On-chip memory A” is used for storing the intermediate results from level 1 of decomposition and it contains one buffer with capacity of 2N coefficients. “On-chip memory B” is used for storing the intermediate results from other levels of decomposition and it contains six buffers (in case of J = 7 levels of decomposition) with capacity halved at every succeeding level, starting from capacity of N coefficients at level 2. All these buffers represent FIFO memory.

Fig. 16
figure 16

On-chip memory

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6 Complexity and performance comparisons of various 2-D DWT 5/3 architectures

For J levels of decomposition of N × N image, the proposed 2-D DWT 5/3 architecture utilizes J FIFO buffers for storing the intermediate results T0[m, n] and T1[m, n], where the capacity of FIFO buffer for level 1 is 2N coefficients. The capacity of FIFO buffer for every succeeding level is half of the capacity of FIFO buffer for the preceding level. Also, each level of decomposition requires one input register for horizontal filter and horizontal filter itself, which contains 2 registers (delay elements). Therefore, the total on-chip memory used by the proposed 2-D DWT architecture can be calculated as follows:

$$\begin{aligned} & 2N + N + \frac{N}{2} + \frac{N}{4} + \cdots + \frac{N}{{2^{J - 2} }} + 3J + 2 \\ & \quad = 4N\left( {1 - 2^{ - J} } \right) + 3J + 2 \\ \end{aligned}$$
(23)

The proposed 2-D DWT architecture does not require off-chip memory at all. Since for all real image processing applications is J << N, the total used memory is approximately 4N(1 − 2−J).

Based on time diagrams shown in Figs. 9 and 10 it can be concluded that computing time per line is N + 4J clock cycles. Based on line-wise diagrams shown in Figs. 13 and 14, the total number of time slots for line processing can be calculated as N + J + 1. Therefore, the total computing time for the proposed 2-D DWT architecture is:

$$\left( {N + 4J} \right) \cdot \left( {N + J + 1} \right) \approx N^{2}$$
(24)

Based on Figs. 9 and 13, the output latency for the proposed architecture can be calculated as:

$$2N + 4 \approx 2N$$
(25)

Hardware utilization efficiency HUE(PA) of a parallel architecture (PA) can be defined as:

$${\text{HUE}}({\text{PA}}) = \frac{{\sum\nolimits_{i = 1}^{M} {A_{i} \times {\text{HUE}}(A_{i} )} }}{{\sum\nolimits_{i = 1}^{M} {A_{i} } }}$$
(26)

where Ai denotes the ith computing unit, HUE(Ai) denotes the hardware utilization efficiency of computing unit Ai and M denotes the total number of computing units. The proposed 2-D DWT 5/3 architecture represents the parallel architecture which consists of two computing units: A1 (which comprises the part of the proposed architecture responsible for filtering and decomposition of level 1) and A2 (which comprises the part of the proposed architecture responsible for filtering and decomposition of all other levels j, where j > 1).

Hardware utilization efficiency HUE(Ai) of the ith computing unit Ai can be defined as the ratio of the actual computation time to the total processing (computing) time, with time expressed in numbers of clock cycles. The actual computation time in case of the proposed architecture is equal to the number of data samples to be processed in computing unit Ai.

Therefore, the hardware utilization efficiency of computing unit A1 can be expressed as:

$${\text{HUE}}(A_{1} ) = \frac{N \cdot N}{(N + 4) \cdot (N + 2)} \approx 1$$
(27)

The hardware utilization efficiency of computing unit A2 can be expressed as:

$$\begin{aligned} {\text{HUE}}(A_{2} ) &= \frac{{\frac{1}{3}N^{2} \left( {1 - 4^{ - J + 1} } \right)}}{(N + 4J - 5) \cdot (N + J - 1)} \\ &\approx \frac{1}{3}\left( {1 - 4^{ - J + 1} } \right) \\ \end{aligned}$$
(28)

Finally, the hardware utilization efficiency for the proposed 2-D DWT 5/3 architecture can be calculated as follows:

$$\begin{aligned} {\text{HUE}}({\text{PA}}) &= \frac{{1 \cdot 1 + 1 \cdot \frac{1}{3}\left( {1 - 4^{ - J + 1} } \right)}}{1 + 1} \\ &= \frac{2}{3}\left( {1 - 4^{ - J} } \right) \\ \end{aligned}$$
(29)

Therefore, for performing only one level of decomposition, the hardware utilization efficiency of the proposed 2-D DWT 5/3 architecture is approximately equal to 1. However, for performing J (J > 1) levels of decomposition, the hardware utilization efficiency reduces to approximately 0.66, as can be calculated from Eq. (29).

Both computing time and output latency are represented in number of clock cycles, while the capacity of total required memory is represented in number of coefficients.

The performance of the proposed 2-D DWT architecture and architectures reported in [9, 16, 18–20, 24–34] are compared in Table 4 in terms of required on-chip memory capacity, required off-chip memory capacity, computing time, output latency and hardware utilization efficiency, for J levels of decomposition of N × N image.

Table 4 Comparison of 2-D DWT 5/3 architectures
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It can be noticed that, compared to other architectures, the proposed architecture has medium computing time, medium output latency and comparable hardware utilization efficiency. Due to very high level of regularity which can be seen in time diagrams in Figs. 9, 10, 11, 12, 13 and 14, the proposed architecture has medium control complexity compared to other architectures. However, the proposed architecture has the lowest total used memory in comparison with all other published architectures. For J → ∞ levels of decomposition of N × N image, the proposed 2-D DWT 5/3 architecture requires the memory capacity of only 4N, which is 20% lower capacity than required capacity for the best previously published architecture.

In order to compare the synthesis results of the proposed 2-D DWT 5/3 architecture with the best available synthesis results of other 2-D DWT 5/3 architectures reported in the literature, the proposed 2-D DWT 5/3 architecture is implemented on Xilinx Virtex-4 XC4VFX100 and Virtex-5 XC5VLX110T FPGA target devices.

Synthesis results for 16-bit word length are presented in Table 5. Slice-delay product (SDP) is calculated based on Eq. (30):

$${\text{SDP}} = N_{\text{SL}} \cdot \frac{\text{CT}}{{f_{\text{MAX}} }}$$
(30)

where NSL denotes the number of used CLB slices, CT denotes the computing time represented in number of clock cycles and fMAX denotes the maximum operating frequency of 2-D DWT 5/3 architecture. It can be noticed that the proposed 2-D DWT 5/3 architecture requires the lowest number of CLB slices in comparison with architecture [30] and PMA [32]. The proposed architecture also requires comparable number of CLB slices with RMA [32], even though the proposed architecture is implemented for 512 × 512 image size and 5 levels of decomposition, while RMA from [32] is implemented for 256 × 256 image size and 3 levels of decomposition. Due to very high maximum operating frequency, PMA [32] has the lowest slice-delay product.

Table 5 FPGA synthesis results of 2-D DWT 5/3 architectures
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Memory usage (for 10-bit word length in order to make proper comparison with results available in [30]) is presented in Table 6. It can be seen that the proposed 2-D DWT 5/3 architecture requires the lowest memory size in comparison with architectures [16, 30, 37–39], even though the proposed architecture is implemented for 512 × 512 image size and 5 levels of decomposition, while architectures from [16, 37–39] are implemented for only 1 level of decomposition and some of them for smaller image size.

Table 6 Comparison of memory usage
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Finally, the FPGA post-synthesis power analysis at 100 MHz for image size 512 × 512, 16-bit word length and Virtex-5 XC5VLX110T FPGA target device (presented in Table 7) clearly shows that the proposed architecture has comparable dissipation with architecture [30] and PMA [32], even though the power dissipation for the proposed architecture is estimated for design with 5 levels of decomposition, while power dissipations for other architectures are estimated for designs with only 1 level of decomposition.

Table 7 FPGA post-synthesis power analysis at 100 MHz (for image size 512 × 512 and Virtex-5 XC5VLX110T FPGA chip)
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7 Conclusion

One-dimensional filter presented in this paper allows utilization of each time slot for the generation of output coefficients. Time slots with input samples with even indexes are used for the generation of low-pass output coefficients. Time slots with input samples with odd indexes are used for the generation of high-pass output coefficients. This approach saves memory resources, since the same memory blocks are used for both low-pass and high-pass coefficients generation. The same filter components are reused, thus reducing the used logic resources, allowing higher operating frequency, lower critical path delay and lower total power dissipation in comparison with other published designs. Two-dimensional DWT 5/3 architecture proposed in this paper, which exploits implemented 1-D filter design, represents memory efficient solution which requires lower storage capacity than any other previously published architecture. The proposed architecture does not require any off-chip memory.