1 Introduction

In preceding years, a continuous miniaturization of complementary metal oxide semiconductor (CMOS) technologies in nanometer scale is facing many reliability and degradation issues. Designer needs to pay more attention towards circuit design that are reliable and insensitive to the transistor parameter degradation. The resilient biasing technique aims to design reliable circuits that are capable of post process adjustment and insensitive to the transistor parameter degradation over long term stress effect [1, 2]. Random doping fluctuation is one of the most important fluctuation sources for threshold voltage. Due to random doping profile, the fluctuation of threshold voltage is expected to be larger [3]. Threshold voltage variation is inherent to the property of CMOS. The sensitivity of the threshold voltage variations in the critical dimensions is greater due to increasing shorter channel effects as the gate length is reduced using CMOS technology. The resilient or body bias technique dynamically changes the threshold voltage by varying voltage of the body terminal which depends upon the substrate materials as well as technology scaling. In the development of different device technologies or different semiconductor materials, much research has been investigated on threshold voltage variation. It is found that one of the most popular materials that is silicon (Si) for which variation in sensitivity of \(V_{T}\) is more as compared to other materials. Gallium Arsenide (GaAS) based MOS devices has advantages over silicon [4] based devices are of its high electron mobility, larger band gap, high critical field etc. which dominates towards the sensitivity of threshold variations. Additionally, gallium nitride (GaN) material also plays vital role as compared to Si and GaAs. But GaN material based parameters are more sensitive to external bias i.e. body potential which directly affects the threshold parameter of devices. A GaAs FET power switching performance with competing silicon devices (MOSFETs, FCTs, GTOs, and bipolar transistors) indicates that the GaAs FET will have better switching efficiency at all operating frequencies [5].

In [6], authors used adaptive gate biasing scheme to compensate the drain current in MOS circuits that is less sensitive to a threshold voltage and mobility degradation for radio frequency power amplifier design for reliability. In [7], authors from Intel argue that process variation is not an “insurmountable barrier” to Moore’s Law, but is simply another challenge to be overcome. Random doping fluctuation, oxide thickness variation and line edge roughness result in significant threshold voltage variation of CMOS transistors at the 45-nm technology node and below in [8–11]. In [12], adaptive substrate biasing scheme is used for low noise amplifier to improve process variability and circuit reliability. In [13], analysis and design of CMOS RF power amplifier using resilient biasing which reduces the impact of variability and reliability when subjected to threshold voltage shift and electron mobility degradation.

In this paper, optimization of the threshold voltage variation for RF CMOS power amplifier with two stages tunable body biasing is proposed. Analytical equations are derived for analysis using three materials with scaling in technology which reduce the threshold voltage shift in preceding stages. GaAs offered prominent threshold voltage variations as compared to Si and GaN. Moreover, this class AB topology achieves power added efficiency of 45 % with output power of 14.96 dBm during simulation. The design also achieves wide bandwidth at resonant frequency of 34 GHz within frequency band of operation. Section 2 describes the analysis of threshold voltage variations. The circuit implementation at design and fabricated level is discussed on Sect. 3. The results and discussion is in Sect. 4 and conclusion is followed in Sect. 5.

2 Analysis of Threshold Voltage Variation

This section describes the analysis of threshold voltage variation using different substrate materials with scale down in CMOS technology which reduces the impact of variability of \(V_{T}\). The tunable body biasing technique is already studied in [13]. It is observed that the threshold voltage \(V_{T}\) is the major circuit performance parameter for CMOS technology and its variability depends upon the substrate materials as well as technology scaling. The numerical analysis of \(V_{T}\) variation is discussed in next sub-sections A and B respectively.

2.1 Single Stage Class AB PA with Tunable Body Biasing

Figure 1 shows the conventional design of single stage body biasing class AB PA. In Liu and Yuan [13] have designed a resilient biasing technique for PA using silicon substrate with 65 nm PTM and achieved a more stable design in terms of sensitivity of threshold voltage variation \(\delta V_{T}\). During analysis, it is found that the level of reduction in \(V_{T}\) of MOSFET is related to the body effect coefficient γ and MOSFET structure coefficient β.

Fig. 1
figure 1

Conventional design of single stage body biasing class AB PA

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The β and γ depends upon the substrate material as well as technology scaling. Using this conception, three different materials Si, GaN and GaAs with two PTM of 65 and 45 nm are employed for the analysis of \(\delta V_{T}\). The calculated node voltage \(V_{BB}\) is given in Eq. (1) [13].

$${\text{V}}_{\text{BB}} = {\text{V}}_{\text{body}} + {\text{V}}_{{{\text{T}}2}} + \frac{{\sqrt {2\upbeta_{2} {\text{R}}_{1} \left( {{\text{V}}_{\text{DD}} - {\text{V}}_{\text{body}} - {\text{V}}_{{{\text{T}}2}} } \right) + 1 } - 1 }}{{\upbeta_{2} {\text{R}}_{1} }}$$
(1)

Here, \(V_{body}\) is voltage of MOSFET M2, \(V_{T2}^{ }\) is threshold voltage of M2 and \(\beta_{2}\) is MOSFET structure coefficient and its expression is (\(= \mu_{n} C_{ox} \frac{W}{L}\)). From this relation (1), it is noticed that the potential \(V_{{{\text{BB}} }}\) is a function of body bias \(V_{body}\) and threshold voltage \(V_{T2}^{ }\). Here, \(V_{body}\) is assumed to be constant and is lower than the supply voltage VDD. The parameter \(V_{T1}^{ }\) of MOSFET M1 due to body effect is given in Eq. (2).

$${\text{V}}_{{{\text{T}}1}} = {\text{V}}_{\text{TO}} +\upgamma\left( {\sqrt {2\emptyset_{\text{F}} - V_{\text{BB}} } - \sqrt {2\emptyset_{\text{F}} } } \right)$$
(2)

Here, \(V_{TO}\) is zero bias threshold voltage of M1, \(\gamma\) is the body coefficient of M1 whose expression (\(\gamma = \frac{{\sqrt {2q \in_{substrate} N_{substrate} } }}{{C_{ox} }}\)) and \(\emptyset_{F}\) is the Fermi Potential (\(= \left( {\frac{kT}{q}} \right){ \ln }\left( {\frac{{N_{substrate } }}{{n_{i} }}} \right)\)). Now, parameters of the chosen materials Si, GaN and GaAs are analyzed using γ expression. It is possible to reduce \(\delta V_{T1}\) if designer chooses different substrate materials other than silicon where \(V_{T}^{ }\) is a critical parameter to be considered. The overall expression of \(\delta V_{T1}\) for single stage body bias PA is stated as in (3) [13].

$$\updelta{\text{V}}_{{{\text{T}}1}} \approx \frac{{{\partial }{\text{V}}_{{{\text{T}}1}} }}{{{\partial }{\text{V}}_{\text{TO}} }} \updelta{\text{V}}_{\text{TO}} + \frac{{{\partial }{\text{V}}_{{{\text{T}}1}} }}{{\partial {\text{V}}_{\text{BB}} }} \updelta{\text{V}}_{\text{BB}}$$
(3)

From (1), (2) and (3), it is concluded that the threshold voltage of M1 depends on the potential \(V_{{{\text{BB}} }}\) and \(V_{{{\text{BB}} }}\) depends on biasing \(V_{body}\). Therefore, \(V_{T1}\) of M1 can be reduced to a minimum value by choosing \(\gamma\) and varying \(V_{BB}\) accordingly. All parameters of \(\gamma\) are constant except for \(\in_{substrate}\) and \(C_{ox}\). The \(V_{BB}\) potential corresponding to M1 by tuning body voltages is further divided into \(V_{{{\text{BB}}1 }}\) and \(V_{{{\text{BB}}2 }}\) and as shown in (4) and (5) respectively.

$${\text{V}}_{{{\text{BB}}1 }} = {\text{V}}_{{{\text{body}}1}} + {\text{V}}_{{{\text{T}}2}}^{ } + \frac{{\sqrt {2\upbeta_{2} {\text{R}}_{1} \left( {{\text{V}}_{\text{DD}} - {\text{V}}_{{{\text{body}}1}} - {\text{V}}_{{{\text{T}}2}}^{ } } \right) + 1 } - 1 }}{{\upbeta_{2} {\text{R}}_{1} }}$$
(4)
$${\text{V}}_{{{\text{BB}}2 }} = {\text{V}}_{{{\text{body}}2}} + {\text{V}}_{{{\text{T}}2}}^{ } + \frac{{\sqrt {2\upbeta_{2} {\text{R}}_{1} \left( {{\text{V}}_{\text{DD}} - {\text{V}}_{{{\text{body}}2}} - {\text{V}}_{{{\text{T}}2}}^{ } } \right) + 1 } - 1 }}{{\upbeta_{2} {\text{R}}_{1} }}$$
(5)

where \(V_{body1}\) and \(V_{body2}\) represent the two different tuning body voltages. According to [13], \(\delta V_{T1}^{{\prime }}\) corresponding to two different body voltages is given as in (6).

$${\text{V}}_{{{\text{T}}1}}^{{\prime }} =\upgamma\left[ { \sqrt {2\emptyset_{\text{F}} - {\text{V}}_{{{\text{BB}}2}} } - \sqrt {2\emptyset_{\text{F}} - {\text{V}}_{{{\text{BB}}1}} } } \right]$$
(6)

A comparison of calculated threshold voltages with respect to tune body voltage is as shown in Figs. 2 and 3 respectively. From the graph, it can be seen that \(V_{T1}\) of M1 decreases linearly when \(V_{body}\) increases from −0.2 to 0.2 V. The amount of percentage change in \(\updelta{\text{V}}_{\text{T}} /{\text{V}}_{\text{T}}\) with respect to \(V_{body}\) is shown in Table 1. The table highlights the importance of the selection of materials as well as plays vital role by scaling in device length which improves the level of threshold voltage variation reduction. According to graphs, GaAs shows minimum variation of sensitivity in threshold voltage as compared to Silicon and GaN.

Fig. 2
figure 2

Sensitivity of threshold voltage versus body voltage

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Fig. 3
figure 3

Sensitivity of threshold voltage versus body voltage

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Table 1 Comparison of threshold voltage variation using three materials at 65 and 45 nm
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2.2 Proposed Two Stage PA with Tunable Biasing

The proposed schematic of two stage body biasing class AB PA is shown in Fig. 4. For optimization of threshold voltage variation, three substrate materials (Si, GaN and GaAs) with scaling in technology are proposed for this analysis. It is found that can be possible to further reduce \(\delta V_{T1}\) of M1 with the help of one or more stage when incorporated with single body biased PA circuit. The \(V_{BB1}^{\prime}\) and \(V_{BB2}^{\prime}\) potentials are generated by tuning \(V_{body}\) and \(V^{\prime}_{body}\) voltages as shown in Eqs. (7) and (8) respectively.

Fig. 4
figure 4

Proposed schematic of two stages body biasing class AB PA

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$$\begin{aligned} {\text{V}}_{{{\text{BB}}1 }}^{\prime}& = {\text{V}}_{{{\text{body}}1}} + \left[ {{\text{V}}_{\text{TO}}^{\prime} +\upgamma\left( {\sqrt {2\emptyset_{\text{F}} - \left( { {\text{V}}_{{{\text{body}}1}}^{\prime} + {\text{V}}_{{{\text{T}}3}} + \frac{{\sqrt {2\upbeta_{3} {\text{R}}_{2} \left( {{\text{V}}_{\text{DD}} - {\text{V}}_{{{\text{body}}1}}^{\prime} - {\text{V}}_{{{\text{T}}3}} } \right) + 1 } - 1 }}{{\upbeta_{3} {\text{R}}_{2} }}} \right)} - \sqrt {2\emptyset_{\text{F}} } } \right)} \right] \\ & \quad + \frac{{\sqrt {2\upbeta_{2} {\text{R}}_{1} \left( {{\text{V}}_{\text{DD}} - {\text{V}}_{{{\text{body}}1}} - {\text{V}}_{{{\text{T}}2}} } \right) + 1 } - 1 }}{{\upbeta_{2} {\text{R}}_{1} }} \\ \end{aligned}$$
(7)
$$\begin{aligned} {\text{V}}_{{{\text{BB}}2 }}^{\prime}& = {\text{V}}_{{{\text{body}}2}} + \left[ {{\text{V}}_{\text{TO}}^{\prime} +\upgamma\left( {\sqrt {2\emptyset_{\text{F}} - \left( { {\text{V}}_{{{\text{body}}2}}^{\prime} + {\text{V}}_{{{\text{T}}3}} + \frac{{\sqrt {2\upbeta_{3} {\text{R}}_{2} \left( {{\text{V}}_{\text{DD}} - {\text{V}}_{{{\text{body}}2}}^{\prime} - {\text{V}}_{{{\text{T}}3}} } \right) + 1 } - 1 }}{{\upbeta_{3} {\text{R}}_{2} }}} \right)} - \sqrt {2\emptyset_{\text{F}} } } \right)} \right] \\ & \quad + \frac{{\sqrt {2\upbeta_{2} {\text{R}}_{1} \left( {{\text{V}}_{\text{DD}} - {\text{V}}_{{{\text{body}}2}} - {\text{V}}_{{{\text{T}}2}} } \right) + 1 } - 1 }}{{\upbeta_{2} {\text{R}}_{1} }} \\ \end{aligned}$$
(8)

Here, \({\text{V}}_{{{\text{body}}1}}^{\prime}\) and \({\text{V}}_{{{\text{body}}2}}^{\prime}\) is obtained by tuning \({\text{V}}_{\text{body}}^{\prime}\) whereas \({\text{V}}_{{{\text{body}}1}}\) and \({\text{V}}_{{{\text{body}}2}}\) by tuning \({\text{V}}_{\text{body}}\). \({\text{V}}_{{{\text{T}}3}}\) is threshold voltage of M3 which is constant. Now, two values of threshold voltage \(V_{T2}\) for M2 would be generated as \(V_{T21}\) and \(V_{T22}\) by tuning the body bias of M3 (\(V_{body}^{\prime}\)) whose expressions are given in (9) and (10).

$${\text{V}}_{{{\text{T}}21}} = {\text{V}}_{{{\text{T}}2{\text{O}}}} +\upgamma\left( {\sqrt {2\emptyset_{\text{F}} - \left( {V_{BB1}^{\prime}} \right)} - \sqrt {2\emptyset_{\text{F}} } } \right)$$
(9)
$${\text{V}}_{{{\text{T}}22}} = {\text{V}}_{{{\text{T}}2{\text{O}}}} +\upgamma\left( {\sqrt {2\emptyset_{\text{F}} - \left( {V_{BB2}^{\prime}} \right)} - \sqrt {2\emptyset_{\text{F}} } } \right)$$
(10)

Here, \({\text{V}}_{{{\text{T}}2{\text{O}}}}\) is zero bias threshold voltage of M2. Now putting the values of \(V_{T21}\) and \(V_{T22}\) in place of \(V_{T2}\) in Eqs. (4) and (5) and evaluate according to Eq. (6), the values for \(\delta V_{T1}\) is obtained. A complete expression is shown below which could be complicated when substituting \({\text{V}^{\prime}}_{{{\text{BB}}1 }}\) and \({\text{V}^{\prime}}_{{{\text{BB}}2 }}\) as given in (7) and (8) respectively.

$$\varvec{ }\updelta{\text{V}}_{{{\text{T}}1}} =\upgamma \left[ {\sqrt {\left( {2 \emptyset_{\text{F}} - {\text{V}}_{{{\text{BB}}2}}^{\prime}} \right)} - \sqrt {\left( {2 \emptyset_{\text{F}} - {\text{V}}_{{{\text{BB}}1}}^{\prime}} \right)} } \right]$$
(11)

Plots of the normalized value of \(V_{T1}\) with respect to \(V_{body}\) are shown in Figs. 5 and 6 respectively. The percentage change in \(\updelta{\text{V}}_{\text{T}} /{\text{V}}_{\text{T}}\) with respect to \(V_{body}\) is shown in Table 2. Here, the tabular data indicates fact that a two stage resilience network provides further reduction in \(\updelta{\text{V}}_{\text{T1}} .\) Again, GaAs shows calculated variation of \(\updelta{\text{V}}_{\text{T1}}\) from 1.80 to −1.82 % at 65 nm while 1.59 to −1.61 % at 45 nm. The proposed network can gives better performance of MOSFET because it is well known that threshold voltage is must small as much as possible.

Fig. 5
figure 5

Variation of threshold voltage versus body biasing

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Fig. 6
figure 6

Variation of threshold voltage versus body biasing

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Table 2 Comparison of threshold voltage variation using three materials at 65 and 45 nm
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3 Circuit Design

Figure 7 shows a 34 GHz class AB PA topology which includes two stage body biasing circuit, input matching network and output matching network. In class AB PA, matching networks is composed of C1, C2, C3, L2 and L3 with bias voltages of VGG and VDD. The biasing voltages are chosen according to [13]. The RF source is taken as 50 Ω and gets maximum power transformation when impedance matching network between source and transistor input are employed. It is possible to achieve maximum output power, gain and power added efficiency (PAE) by improving the input matching. The optimal output value is achieved by tuning the output matching network using ADS load pull instrument. The 45-nm NMOS transistors are modeled by the PTM equivalent BSIM4 model card. As discussed in above section, \(V_{T}\) is the most significant parameter and affected by body biasing of the transistors. According to [13], tunable biasing technique controls the body potential of the MOSFET which is to adjust the threshold voltage and to achieve maximum output power and PAE. So, here also two stages of tunable body biasing improve \(V_{T}\) variation of CMOS PA and after simulation achieves more output power, higher gain and best PAE. The proposed schematic design of 34 GHz PA topology is simulated using harmonic balance (HB) simulator in advanced design system (ADS) tool. Table 3. Gives design specifications of proposed power amplifier and its values. Figure 8 presents the chip photograph of the 34 GHz CMOS PA with a chip size of 0.84 × 0.95 mm2. For fabrication silicon substrate is utilized. The simulation and measured results of this design are discussed in next section.

Fig. 7
figure 7

Proposed architecture of CMOS Class AB PA with matching network

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Table 3 Component values with dimensions of proposed power amplifier
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Fig. 8
figure 8

Chip photograph of 34 GHz Power Amplifier

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4 Results and Discussion

The above discussed 34 GHz class AB PA topology is simulated by ADS using PTM model of 45 nm CMOS process. In the input matching, parallel inductance L1 is 1 nH and series capacitances C1 and C2 are 64 fF and 1.23 pF respectively. At the output, capacitance C3 is 1 pF where inductance value L3 is 1.2 nH. As shown in Fig. 9, at 34 GHz, output power is 14.96 dBm while input power signal is 0 dBm. It is observed that if input power is <0 dBm and with the increase of input power, output power increases but output powers stop up to a saturation point, once the input power exceeds the 0 dBm. It is seen that in Fig. 10, the maximum power added efficiency (PAE) of this circuit achieves up to 44.8 %. The PA is measured via On-wafer probing with test capability of 35 nm plate. The measurement of fabricated chip could be possible for s-parameters only. As per the simulation and measurement results, return loss is obtained at the operating frequency of 34 GHz within frequency range of 33–35 GHz which is shown in Fig. 11. It is small enough to indicate the satisfactory input matching. The best gain of 16.9 dB is achieved with the help of two stages tunable biasing body design can see in Fig. 11. A dc power dissipation of approximately 11.3 mW under 1 V power supply is utilized for this design. Table 4. Show comparison in parameters of circuit design with previous reported paper.

Fig. 9
figure 9

Output power versus input power

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Fig. 10
figure 10

PAE versus input power

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Fig. 11
figure 11

Variation of return loss and forward gain versus frequency

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Table 4 Comparison of circuit design with previous reported paper
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5 Conclusion

In this paper, two stage tunable body biasing class AB PA using three substrate materials with scaling in technology optimizes the threshold voltage variation. A single stage adaptive body biasing class AB PA is compared with two stages and it is analytically proven that the threshold voltage variation in preceding stages can be diminished if body biasing design is tunabled. A two stage tunable body biasing class AB Power amplifier with matching networks is simulated in ADS and shows that at operating frequency of 34 GHz, output power is 14.96 dBm and PAE of 44.8 %. Performance standards are met for the PA circuit. Moreover, state of the art of this work achieves S11 of −23 dB with forward gain of 16.9 dB which relaxed 50 Ω matching constraints throughout in PA circuit.