1 Introduction

Metal–semiconductor devices are very interesting and promise for electronic applications [1,2,3,4,5]. These devices can be used as rectifiers, inverters, photodiode and photodetectors [6,7,8,9]. Changing properties of these devices can be accomplished by inserting some kind of metal oxide or insulator layers between the metal and semiconductor [10,11,12].

The ZnO can be inserted as a metal oxide layer between the Au metal and n-type Si semiconductor for controlling of properties of this metal and semiconductor device because the ZnO metal oxide layer has high direct band gap (3.37 eV) [13, 14]. Also, the ZnO layer can be obtained low cost and low temperature deposition technique [15]. The ZnO as a semiconductor can be used in lasers, solar cells, photodetectors and varistors [16,17,18,19]. To obtain a ZnO thin film layer, it can be used chemical vapor deposition [20], spray pyrolysis [21], sol gel [22] and atomic layer deposition techniques (ALD) [23]. Among them, ALD technique has more advantageous for obtaining uniform film and definite thickness control [24, 25].

The measurement temperature of the sample is very important parameter for metal–semiconductor devices because it can affect main properties of those kinds of devices, and these devices can be used at various temperature after understanding temperature dependent features [26, 27]. When it can be checked in the literature, it can be seen many investigations on temperature-dependent electrical properties of metal–semiconductor devices. For instance, Mtangi et al. [28] investigated temperature-dependent current–voltage (I–V) characteristics of Pd/ZnO Schottky barrier diodes in 60–300 K temperature range. They showed that ZnO has different conduction mechanism in different temperatures, and has stable ideality factor and barrier height in this temperature range. Yadav et al. [7] studied high temperature-dependent electrical properties of Pd/ZnO/n-Si/Ti/Al device. They obtained ZnO layer using sol–gel spin coating technique and concluded that the saturation current and barrier height increased with the temperature increment. Khare et al. [29] researched the temperature-dependent current–voltage (I–V) characteristics of ZnO/P3HT:PCBM junctions. ZnO layer were obtained atmospheric pressure spatial ALD and electrodeposition techniques. In this junctions barrier height decreased and ideality factor increased with increasing temperature. They emphasized that the samples need to be thermally annealed for higher photoresponse properties of the junctions in their study. These are three different studies, but there is no any investigations about the temperature-dependent I–V characteristics of Au/ZnO/n-Si devices in the literature. This is important for better understanding of ZnO role in the interface of the metal–semiconductor devices.

In this context, the aim of this study is to investigate the temperature-dependent I–V characteristics of the Au/ZnO/n-Si device for technological applications in the wide range temperatures from 100 to 380 K with 20 K steps.

2 Materials and methods

n-Type Si substrate, which has (100) orientation, was used for producing Au/ZnO/n-Si device. Firstly, Si wafer was cut into 1 cm2 pieces (square shape), and they were cleaned and etched with various solvents and acids (H2SO4:H2O2:H2O (5:1:1) for 1 min). Secondly, high purity gold was evaporated thermally back side of the Si wafers for ohmic contact, and then wafers were annealed in N2 atmosphere at 450 °C for 3 min. Thirdly, ZnO layer was deposited on front side of Si wafers for 10 nm ZnO layer with 1.45 Å growth rate at per cycle by ALD technique which had 5 × 10−3 Torr vacuum, 180 °C temperature and zinc acetate and water sources. Fourthly, Au metal was doped on the ZnO surface as metallic contacts using a mask with 1.0 mm diameter holes on the device. Shematic diagram of the device has been shown in Fig. 1. The ZnO film layer in the device was characterized with Bruker D8 Discover XRD. SEM images were obtained ZEISS Sigma 300. The I–V measurements of the device were obtained by using a homemade liquid nitrogen cryostat equipped with a temperature controller in darkness in the range of 100–380 K temperatures with 20 K steps at 500 kHz frequency.

Fig. 1
figure 1

Schematic diagram and image of Au/ZnO/n-Si device

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3 Result and discussion

XRD graph of ZnO thin film layer has been indicated in Fig. 2 from 20° to 80°. It can be seen two peaks in that figure: one of them and severe one is (201) peak, other and weak one is (002) peak. These peaks have implied that ZnO thin film layer was obtained successfully by the ALD technique. XRD peaks also referred to the hexagonal structure of the ZnO [30].

Fig. 2
figure 2

XRD graphs of ZnO layer obtained by ALD technique

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Surface and cross-section images of the device were taken to investigate surface morphology properties of the device using SEM. These images have been given in Fig. 3a, b for surface of the ZnO thin film and cross-section of the Au/ZnO/n-Si, respectively. Figure 3a has pointed out that ZnO thin film, which has smooth and homogenous surface, has been obtained successfully by ALD technique. Figure 3b has showed that device was composed also successfully on Si wafer. The surface morphology of the ZnO thin film has revealed that ALD technique is promising technique to deposit good films on a substrate [31, 32].

Fig. 3
figure 3

a Surface SEM image, b cross-section image of the Au/ZnO/n-Si

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The I–V characteristics of Au/ZnO/n-Si have indicated for changing temperature from 100 to 380 K for 20 K steps in Fig. 4 (inset figure shows 300 K I–V characteristics of the device). The device has good rectifying property at all temperatures, and this indicates that the temperature increase or decrease do not change rectifying properties of the device. This conclusion implied that this device can be used for wide temperature ranges [33, 34].

Fig. 4
figure 4

(online color) I–V characteristics of Au/ZnO/n-Si device at various temperature

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Barrier height and ideality factor were calculated by using thermionic emission theory. According to this theory, current (I) is given below equation:

$$I={I_0}{\text{exp}}\left( {\frac{{qV}}{{nkT}}} \right)\left[ {1 - {\text{exp}}\left( {\frac{{qV}}{{nkT}}} \right)} \right]$$
(1)

in here, \({I_0}\) (saturation current) is intercept value of the linear portion of lnI–V plot at V = 0, and is given

$${I_0}=A{A^*}{T^2}\exp \left( { - \frac{{q{\Phi _b}}}{{kT}}} \right)$$
(2)

In these equations, q is charge of the electron; n, k, T, are ideality factor of device, Boltzman’s constant and device temperature, respectively. A and A * are metallic contact area of the device and Richardson constant (A* = 112 A cm−2 K−2 for n-type Si), respectively. \({\Phi _b}\) is the barrier height at zero bias for device. If n and \({\Phi _b}\) is rearranged using Eqs. (1) and (2), they can be typed as follow:

$$n=\frac{q}{{kT}}\left( {\frac{{dV}}{{dlnI}}} \right)$$
(3)

and

$${\Phi _b}=\frac{{kT}}{q}\ln \left( {\frac{{{A^*}A{T^2}}}{{{I_0}}}} \right)~~$$
(4)

n and \({\Phi _b}\) values for all temperature have been listed in Table 1. When n values have decreased from 4.34 at 100 K to 2.40 at 380 K with increasing temperature, \({\Phi _b}\) values increased from 0.39 at 100 K to 0.91 eV at 380 K. These change in n and \({\Phi _b}\) values have been shown in Fig. 5 as a graph. All n values are bigger than one, and it implied that there is no pure thermionic emission (TE) in this device. This difference can be attributed to interface states or barrier inhomogeneity in the interface of the device [35, 36]. At the same time, increasing temperature has increased the saturation current values of the device. Saturation current values have also been listed in Table 1. This device can be used depending on temperature for different applications in technology [37].

Table 1 The some electrical parameters of Au/ZnO/n-Si device obtained I–V measurements
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Fig. 5
figure 5

(online color) Changing of barrier height and idealty factor of Au/ZnO/n-Si device at various temperature

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Figure 5 shows how barrier height and ideality factor changed with the changing temperature. While the barrier height values have increased with increasing temperature, the ideality factor values have decreased. These changes clearly have concluded that there is no pure TE current in the device [38]. The charge carriers have no enough energy to cross the high barrier height in the lower temperature, but current transport is provided by lower parts of barrier height [39]. If barrier height is not homogeous, this case usually happens, and this causes to increase in the barrier height and decrease in the ideality factors with increasing temperature [40,41,42].

To better understand currrent mechanism, the nkT versus kT plot of Au/ZnO/n-Si device has been plotted in Fig. 6. If a diode is ideal, pure thermionic emission happens, and its ideality factor values do not change with increasing temperature as can be seen in Fig. 6. In this device, nkT versus kT plot have showed almost parallel line to the ideal device but not exactly parallel. It means that associated with TE, other current transport mechanism such as thermionic fileld emission (TFE) has also effectiveness in this device [42]. In addition, this conclusion also have referred to barrier inhomogenity in the interface of the device [38].

Fig. 6
figure 6

(online color) The nkT versus kT plot of Au/ZnO/n-Si device

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The ln(I 0 /T 2) versus (kT)−1 or (nkT)−1 plots of Au/ZnO/n-Si device have been given in Fig. 7. The value of Richardson constant for n-type Si is 112 A/(cm K)−1, but here, Richardson constant values (can be seen on Fig. 7) are very small from the value of 112 A/(cm K)−1. This result showed that there is some barrier inhomogeneity in the interface [42].

Fig. 7
figure 7

(online color) The experimental Richardson plots of Au/ZnO/n-Si device

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The other way to determine the diode parameters, Cheung’s functions can be used for this case. Current expression with considering series resistance of device could be calculated below equation [43]:

$$I={I_0}{\text{exp}}\left( {\frac{{q(V - I{R_s}}}{{nkT}}} \right)$$
(5)

where, IR s voltage dropping which is reasoned by series resistance of the device. This series resistance can be calculated using following expression:

$$\frac{{dV}}{{d(\ln I)}}=I{R_s}+n\frac{{kT}}{q}$$
(6)
$$H\left( I \right)=V - n\left( {\frac{{kT}}{q}} \right)\ln \left( {\frac{I}{{A{A^*}{T^2}}}} \right)$$
(7)

where H(I) can be arranged as follow:

$$H\left( I \right)=I{R_s}+n{\Phi _b}$$
(8)

Equation (6) is a straight line equation, and if dV/d(lnI) versus I are plotted, this graph should be linear. According to the Cheung’s functions, using this linear plotting, R s and n values can be obtained slope and intercept of the plots, respectively. Also, expression (8) is again a straight line equation. If obtaining ideality factor is written in this equation to its place, same plotting way, barrier height and series resistance can be calculated. In this plotting, y-axis intercept is equal to \(n{\Phi _b}\) and slope of this plot also provides a different obtaining of R s which could be controlled the accuracy of Cheung’s approximation [43].

The dV/d(lnI) versus I and H(I) versus I plots of device for different temperatures have been shown in Figs. 8 and 9, respectively. Although there is some deviations in dV/d(lnI) versus I plots of the device, these plots are good agreement and almost periodic with the changing temperature. H(I) versus I plots have showed very good periodicity with changing temperature. The calculated n, \({\Phi _b}\) and R s values have been given in Table 1. While n values are increasing, \({\Phi _b}\) values almost stay constant for the changing temperature. The difference in n and \({\Phi _b}\) values obtained from TE current theory can be attributed that TE theory and Cheung’s functions obtained different regions of I–V measurements [44]. R s values which were obtained dV/d(lnI) versus I and H(I) versus I plots were not so different from each other. These results have corrected consistency of Chung’s functions. At the same time, R s values for two calculations have decreased with increasing temperature because of increasing number of carriers [45].

Fig. 8
figure 8

(online color) dv/dln(I) versus I plots of Au/ZnO/n-Si device with the changing temperature

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Fig. 9
figure 9

(online color) H(I)–I plots of Au/ZnO/n-Si device in the temperature range of 100–380 K

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As another method, Norde’s approximation can be used for calculating series resistance and barrier height of the device. Respect to this method, R s and \({\Phi _b}\) values are given as follow:

$$F\left( V \right)=\frac{V}{\gamma } - \frac{{kT}}{q}\ln \left( {\frac{{I(V)}}{{A{A^*}{T^2}}}} \right)$$
(9)

where \(\gamma\) is an integer (dimensionless) greater than n and I(V) is current which is acquired from the I–V curve. With aid of this equation, R s and \({\Phi _b}\) can be rearranged following relations:

$${\Phi _b}=F\left( {{V_0}} \right)+\left[ {\frac{{{V_0}}}{\gamma } - \frac{{kT}}{q}} \right]$$
(10)

here F(V 0) is the minimum point of F(V) and V 0 is the corresponding voltage and R s is with below equation

$${R_s}=\frac{{\gamma - n}}{I}~~~\frac{{kT}}{q}$$
(11)

The F(V) versus V plots of Au/ZnO/n-Si device have been shown in Fig. 10 for the changing temperature from 100 to 380 K. Calculated \({\Phi _b}\) and R s values were listed in Table 1. While \({\Phi _b}\) values were increased with increasing temperature, R s values decreased. This decrease can be attributed to increasing carriers in the device with increasing temperature [46]. There are also differences \({\Phi _b}\) and R s values between obtained Norde’s method, TE theory and Cheung’s method. These differences can be attributed to that while Cheung’s method is applied non-linear region (high voltage), Norde’s method is performed all forward bias lnI–V plots [47].

Fig. 10
figure 10

(online color) F(v)–V plots of Au/ZnO/n-Si device changing temperature from 100 to 380 K

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The lnI–V plot which has a non-linearity part at high forward bias voltages shows a continuous of the interface state density (N ss ) in balance with semiconductor. The N ss values for Au/ZnO/n-Si device with changing temperature were calculated from the forward bias I–V by considering efficient barrier height (Φ e ), ideality factor n(V) which is depend on the voltage and R s . The Φ e can be written as following equation [48]:

$${\Phi _e}={\Phi _b}+\left( {1 - 1/n(V)} \right)\left( {V - I{R_s}} \right)$$
(12)

Since the ideality factor of a diode become all time greater than one, it was suggested below formula by Card and Rhoderick [48].

$$n\left( V \right)=1+\frac{\delta }{{{\varepsilon _i}}}\left[ {\frac{{{\varepsilon _s}}}{{{W_d}}}+q{N_{ss}}\left( V \right)} \right]$$
(13)

where W d is depletion layer width and δ is the thickness of the insulator sheet at the interface. ε i and ε s are permittivity of interfacial layer and the semiconductor, respectively. Rearranges of Eq. (13), the N ss can be expressed as follow:

$${N_{ss}}(V)=\frac{1}{q}\left[ {\frac{{{\varepsilon _i}}}{\delta }\left( {n\left( V \right) - 1} \right) - \frac{{{\varepsilon _s}}}{{{W_d}}})} \right]$$
(14)

In addition, for n-type semiconductors, the energy of the N ss as regards the conductance band edge (E c ) at the semiconductor surface can be calculated as

$${E_c} - {E_{ss}}=q({\Phi _e} - \left( {V - I{R_s}} \right))$$
(15)

where the IR s term is the voltage drop on the device. The energy density distribution profile of N ss with R s , which was obtained from the forward-bias I–V measurements, has been indicated in Fig. 11 for the changing temperature. It can be seen from Fig. 11 that N ss values has been affected by changing temperatures. In addition, relatively higher N ss values can be ascribed to the very thin (10 nm) ZnO interface layer [49, 50]. These results have also advised that the N ss values should be considered as distinguishing parameters for determining properties of the device [51].

Fig. 11
figure 11

(online color) N ss versus E c —E ss plots of Au/ZnO/n-Si device changing temperature

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4 Conclusion

Au/ZnO/n-Si device was composed by ALD technique as a thin layer ZnO film at the interface, and device was characterized with XRD, SEM and temperature dependent I–V measurements. XRD measurements showed that ZnO thin film layer has (002) and (201) orientation peaks which are referred to hexagonal structure of the ZnO layer. SEM images of the device showed that ZnO layer has smooth surface and, Au/ZnO/n-Si device was obtained successfully. Ideality factor and barrier height values were calculated using TE theory for various temperatures. While n values decreased with increasing temperature, \({\Phi _b}\) values increased. These changings at n and \({\Phi _b}\) values confirmed that device was not ideal diode and charge transport mechanism was not just TE. Also, these parameters and R s values were calculated using Chung’s and Norde’s methods. The increasing temperature caused generally decreasing R s values. N ss versus (E c –E ss ) plots have shown that N ss values increased with increasing temperatures. These results have implied that this device can be used for diodes applications in the wide range temperatures.