1 Introduction

Polycrystalline silicon nanowires (poly-SiNWs) have attracted considerable attention in recent decades as an active element for the new generation of electronic devices, such as thin film transistors (TFT) [1,2,3] and biochemical sensors [4, 5], owing to their sensitivity to chemical and biological species. The electrical properties of poly-SiNWs and their realization technique have rendered these nanowires potentially promising candidates for overcoming several obstacles, such as the short-channel effects encountered in fin field-effect transistors (FinFETs) [6]. Different techniques have been implemented to realize poly-SiNWs [7, 8], and the top-down approach affords an important advantage due to its compatibility with the concept of miniaturization. Planar technology is commonly used in the very large-scale industrial applications to produce reliable and low-cost devices. More precisely, for low-temperature technologies, polycrystalline silicon is a widely used material.

Although the operation of devices based on poly-SiNWs has been demonstrated [1, 9, 10] and their performance has been encouraging, they are still being researched to better understand and identify the properties of poly-SiNWs for integration in commercial devices. Furthermore, the electrical properties of poly-SiNWs are closely linked to their production processes, their diameter [11], and their architecture. More precisely, their crystalline quality plays a decisive role in the device performance. Thus, poly-SiNWs with good crystalline quality will afford high-performance devices such as transistors with a high ION/IOFF ratio, reduced threshold voltage, and small subthreshold swing slope [12]. In contrast, a low or even highly disordered crystalline quality is advantageous for sensors owing to the interaction of the electrical defects on the surface with the surrounding chemical species [13].

The performance/crystalline quality duality of poly-SiNWs needs to be analyzed to understand and predict their behaviors. Since physical characterizations are a powerful tool for understanding the device properties, analytical and numerical studies have been performed to build models to explicitly determine the electrical properties. Several approaches have been employed to model the electrical performance of poly-SiNW-based devices with different architectures, including back gate, dual gate [14], and gate all around [15, 16], by analyzing the impact of the number and position of grain boundaries present in the nanowire structure. For poly-SiNWs with a high density of defects, adopting a model that is described by only grain boundaries is not convenient. Indeed, studies on the conduction mechanism [17] for poly-SiNWs with diameters less than 50 nm have shown that carrier transport occurs via variable-range hopping (VRH). This verifies the disordered nature for poly-SiNWs and rules out the model based on grains separated by grain boundaries.

In this study, we investigate the performance of TFTs based on poly-SiNWs with 30 nm diameters that were realized using the complementary metal–oxide–semiconductor (CMOS) spacer technique [7]. First, a model of the drain current was developed based on the Poisson’s equation. The charge of acceptor traps to the density of states (DOS) was represented by two exponentials describing the deep and band tail states. Thereafter, the impact of the DOS parameters is detailed and discussed to elucidate the performance of poly-SiNWs. Finally, the model was fitted with the experimental transfer characteristic data, justified in agreement with our study on the conduction mechanism and DOS measurements for TFTs based on poly-SiNWs in order to provide the DOS within the gap.

2 Device modeling

2.1 Surface potential model

Our previous study [17] on the electrical properties of poly-SiNWs obtained using the spacer method revealed that the conduction mechanism operates via VRH when the nanowire diameter is around 50 nm. This is explained by the high density of electric traps that are afforded by the disordered structure of the lower part of the un-doped poly-Si layer, from which these nanowires are obtained. Therefore, we can consider the DOS model [18] to express the distribution of these defects within the gap. The density of two exponential acceptor and donor tail states and two exponential deep acceptor and donor states can be expressed as follows:

$$\begin{array}{*{20}c} {g_{{{\text{TA}}}} \left( E \right) = N_{{{\text{TA}}}} \exp \left( {\frac{{E - E_{C} }}{{w_{{{\text{TA}}}} }}} \right)} \\ \end{array}$$
(1)
$$\begin{array}{*{20}c} {g_{{{\text{DA}}}} \left( E \right) = N_{{{\text{DA}}}} \exp \left( {\frac{{E - E_{C} }}{{w_{{{\text{DA}}}} }}} \right)} \\ \end{array}$$
(2)
$$\begin{array}{*{20}c} {g_{TD} \left( E \right) = N_{TD} \exp \left( {\frac{{E_{V} - E}}{{w_{TD} }}} \right)} \\ \end{array}$$
(3)
$$\begin{array}{*{20}c} {g_{{{\text{DD}}}} \left( E \right) = N_{{{\text{DD}}}} \exp \left( {\frac{{E_{V} - E}}{{w_{{{\text{DD}}}} }}} \right)} \\ \end{array}$$
(4)

Here, gTA(E) and gTD(E) are two exponential densities that correspond to the densities of the acceptor and donor states, respectively, in the tape tails. Additionally, gDA(E) and gDD(E) are two exponential densities corresponding to the densities of the deep acceptor and donor states, respectively. E is the trap energy, EC is the conduction band energy, and EV is the valence band energy. For tail distributions, DOS is described by the conduction and valence band edge intercept densities (NTA and NTD, respectively) and the characteristic decay energies (WTA and WTD, respectively). For deep distributions, DOS is described by the conduction and valence band edge intercept densities (NDA and NDD, respectively) and the characteristic decay energies (WDA and WDD, respectively).

Figure 1 shows the cross-section of the metal–insulator–semiconductor structure and the corresponding energy diagram. For simplicity, we only consider the free electrons and the charge of the acceptor traps. The one-dimensional Poisson equation is

$$\begin{array}{*{20}c} {\frac{{\partial^{2} \psi }}{{\partial x^{2} }} = \frac{q}{{\varepsilon_{si} }}\left( {n + n_{T} } \right)} \\ \end{array}$$
(5)
Fig. 1
figure 1

a Schematic of the considered metal–insulator–semiconductor structure. b Energy band diagram

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Here, n is the concentration of free electrons and nT is the density of ionized acceptor traps:

$$\begin{array}{*{20}c} {n = N_{0} \exp \left( {\frac{q\psi }{{{\text{kT}}}}} \right)} \\ \end{array}$$
(6)
$$\begin{array}{*{20}c} {n_{T} = n_{{{\text{tail}}}} + n_{{{\text{deep}}}} = \mathop \smallint \limits_{{E_{V} }}^{{E_{C} }} g_{{{\text{TA}}}} \left( E \right).f_{A} \left( E \right).{\text{d}}E + \mathop \smallint \limits_{{E_{V} }}^{{E_{C} }} g_{{{\text{DA}}}} \left( E \right).f_{A} \left( E \right).{\text{d}}E} \\ \end{array}$$
(7)

where \(N_{0} = N_{C} \exp \left( { - \frac{{E_{F0} }}{{{\text{kT}}}}} \right)\) is the electron concentration under equilibrium conditions, and NC is the effective DOS in the conduction band. fA(E) is the probability function of occupation of an acceptor trap by an electron:

$$\begin{array}{*{20}c} {f_{A} \left( E \right) = \frac{1}{{1 + \exp \left( {\frac{{E - E_{F0} }}{{{\text{kT}}}}} \right)}} = \left\{ {\begin{array}{*{20}c} {1;E < E_{F0} } \\ {\exp \left( {\frac{{E_{F0} - E}}{{{\text{kT}}}}} \right) ;E > E_{F0} } \\ \end{array} } \right.} \\ \end{array}$$
(8)

Here, EF0 denotes the Fermi level under equilibrium conditions. Based on the band gap diagram, the number of ionized acceptor traps at steady state is

$$\begin{array}{*{20}c} {n_{{{\text{tail}}}} \left( \psi \right) = \mathop \smallint \limits_{{E_{V} }}^{{E_{F0} + q\psi}} g_{TA} \left( E \right).{\text{d}}E + \mathop \smallint \limits_{{E_{F0} + q\psi}}^{{E_{C} }} g_{{{\text{TA}}}} \left( E \right).{\text{exp}}\left( {\frac{{E_{F0} - E}}{{{\text{kT}}}}} \right){\text{d}}E} \\ \end{array}$$
(9)
$$\begin{array}{*{20}c} {n_{{{\text{tail}}}} \left( \psi \right) = \alpha_{T} \left[ {A_{T} \exp \left( {\frac{q\psi }{{{\text{kT}}}}} \right) - B_{T} \exp \left( {\frac{q\psi }{{W_{{{\text{TA}}}} }}} \right)} \right] - C_{T} } \\ \end{array}$$
(10)
$$\begin{array}{*{20}c} {n_{{{\text{deep}}}} \left( \psi \right) = \mathop \smallint \limits_{{E_{V} }}^{{E_{F0} + q\psi}} g_{DA} \left( E \right).{\text{d}}E + \mathop \smallint \limits_{{E_{F0} + q\psi}}^{{E_{C} }} g_{{{\text{DA}}}} \left( E \right).\exp \left( {\frac{{E_{F0} - E}}{{{\text{kT}}}}} \right){\text{d}}E} \\ \end{array}$$
(11)
$$\begin{array}{*{20}c} {n_{{{\text{deep}}}} \left( \psi \right) = \alpha_{D} \left[ {A_{D} \exp \left( {\frac{q\psi }{{{\text{kT}}}}} \right) - B_{D} \exp \left( {\frac{q\psi }{{W_{{{\text{TA}}}} }}} \right)} \right] - C_{D} } \\ \end{array}$$
(12)

Here,

$$\begin{gathered} \alpha_{T} = \frac{{W_{{{\text{TA}}}} N_{{{\text{TA}}}} }}{{{\text{kT}} - W_{{{\text{TA}}}} }};\alpha_{D} = \frac{{W_{{{\text{DA}}}} N_{{{\text{DA}}}} }}{{{\text{kT}} - W_{{{\text{DA}}}} }};A_{T} = A_{D} = {\text{kT}}\exp \left( {\frac{{E_{F0} - E_{C} }}{{{\text{kT}}}}} \right);B_{T} = W_{{{\text{TA}}}} \exp \left( {\frac{{E_{F0} - E_{C} }}{{W_{{{\text{TA}}}} }}} \right) \hfill \\ ;B_{D} = W_{{{\text{DA}}}} \exp \left( {\frac{{E_{F0} - E_{C} }}{{W_{{{\text{DA}}}} }}} \right);C_{T} = W_{{{\text{TA}}}} N_{{{\text{TA}}}} \exp \left( { - \frac{{E_{C} }}{{{\text{kT}}}}} \right);C_{D} = W_{{{\text{DA}}}} N_{{{\text{DA}}}} \exp \left( { - \frac{{E_{C} }}{{{\text{kT}}}}} \right) \hfill \\ \end{gathered}$$

Using the property \(\partial \left( {\partial \psi /\partial x} \right)^{2} = 2\left( {\partial^{2} \psi /\partial x^{2} } \right)\partial \psi\), the electric field ξ along x is expressed according to (5) as

$$\begin{array}{*{20}c} {\partial \left( {\xi^{2} } \right) = \frac{2q}{{\varepsilon_{si} }}\left( {n + n_{T} } \right)\partial \psi } \\ \end{array}$$
(13)

Substituting (6), (10), and (12) in (13) and integrating from ψTsc(x = Tsc) to ψs(x = 0), the expression of the electric field at the SiO2/poly-SiNW interface (x = 0) is

$$\begin{array}{*{20}c} {\xi_{s} = \sqrt {\frac{2kT}{{\varepsilon_{{{\text{si}}}} }}\left| {\left( {N_{1} + N_{2} + N_{3} + N_{4} } \right)} \right|} } \\ \end{array}$$
(14)

Here,

$$N_{1} = \left( {N_{0} + \alpha_{T} A_{T} + \alpha_{D} A_{D} } \right)\left( {\exp \left( {\frac{{q\psi_{s} }}{{{\text{kT}}}}} \right) - \exp \left( {\frac{{q\psi_{{{\text{Tsc}}}} }}{{{\text{kT}}}}} \right)} \right)$$
$$N_{2} = - \frac{{W_{{{\text{TA}}}} }}{kT}\alpha_{T} B_{T} \left( {\exp \left( {\frac{{q\psi_{s} }}{{W_{{{\text{TA}}}} }}} \right) - \exp \left( {\frac{{q\psi_{{{\text{Tsc}}}} }}{{W_{{{\text{TA}}}} }}} \right)} \right)$$
$$N_{3} = - \frac{{W_{DA} }}{{{\text{kT}}}}\alpha_{D} B_{D} \left( {\exp \left( {\frac{{q\psi_{s} }}{{W_{{{\text{DA}}}} }}} \right) - \exp \left( {\frac{{q\psi_{{{\text{Tsc}}}} }}{{W_{{{\text{DA}}}} }}} \right)} \right)$$
$$N_{4} = - \left( {C_{T} + C_{D} } \right)\left( {\frac{{q\psi_{s} }}{{{\text{kT}}}} - \frac{{q\psi_{{{\text{Tsc}}}} }}{{{\text{kT}}}}} \right)$$

For a range of parameters WTA, WDA, NTA, and NDA, which we will discuss later, only the terms N2 and N3 subsist in the expression of ξs. Neglecting the potential ψTsc, the final expression of ξs becomes

$$\begin{array}{*{20}c} {\xi_{s} \approx \sqrt {\frac{{2{\text{kT}}}}{{\varepsilon_{si} }}\left( {N_{02} \exp \left( {\frac{{q\psi_{s} }}{{W_{{{\text{TA}}}} }}} \right) + N_{03} \exp \left( {\frac{{q\psi_{s} }}{{W_{{{\text{DA}}}} }}} \right)} \right)} } \\ \end{array}$$
(15)

Here,

$${N}_{02}=-\frac{{W}_{\mathrm{TA}}}{\mathrm{kT}}{\alpha }_{T}{B}_{T};{N}_{03}=-\frac{{W}_{DA}}{\mathrm{kT}}{\alpha }_{D}{B}_{D}$$

Considering the Vox potential in the insulator and using Gauss’s law at the SiO2/poly-SiNW interface, the gate voltage is

$$\begin{array}{*{20}c} {V_{{{\text{GS}}}} = V_{{{\text{ox}}}} + \psi_{s} + V_{{{\text{FB}}}} = \psi_{s} + V_{{{\text{FB}}}} + t_{{{\text{ox}}}} \frac{{\varepsilon_{{{\text{si}}}} }}{{\varepsilon_{{{\text{ox}}}} }}\xi_{s} } \\ \end{array}$$
(16)

where VFB is the flat band voltage defined by \(V_{{{\text{FB}}}} = q\chi - q\varphi_{m}\). Thus, ψs becomes

$$\begin{array}{*{20}c} {\psi_{s} = V_{{{\text{GS}}}} - V_{{{\text{FB}}}} - \frac{{\sqrt {2kT\varepsilon_{{{\text{si}}}} } }}{{C_{{{\text{ox}}}} }}\sqrt {N_{02} \exp \left( {\frac{{q\psi_{s} }}{{W_{{{\text{TA}}}} }}} \right) + N_{03} \exp \left( {\frac{{q\psi_{s} }}{{W_{{{\text{DA}}}} }}} \right)} } \\ \end{array}$$
(17)

Here, Cox is the oxide capacity per unit area. An analytical expression of ψs cannot be clearly obtained from (17). However, depending on the choice of the parameters N2 and N3, one of the two parameters dominates the expression of ξs. Then, ψs becomes

$$\begin{array}{*{20}c} {\psi_{s} = V_{{{\text{GS}}}} - V_{{{\text{FB}}}} - \frac{{\sqrt {\varepsilon_{{{\text{si}}}} 2{\text{kT}}} }}{{C_{{{\text{ox}}}} }}\sqrt {N_{02,3} } \exp \left( {\frac{{q\psi_{s} }}{{2W_{{T,{\text{DA}}}} }}} \right)} \\ \end{array}$$
(18)

Here,

$$\begin{array}{*{20}c} {N_{02,3} \exp \left( {\frac{{q\psi_{s} }}{{W_{{T,{\text{DA}}}} }}} \right) = N_{02} \exp \left( {\frac{{q\psi_{s} }}{{W_{{{\text{TA}}}} }}} \right) or N_{03} \exp \left( {\frac{{q\psi_{s} }}{{W_{{{\text{DA}}}} }}} \right)} \\ \end{array}$$
(19)

From (18), the numerical solution ψs for a given VGS value shows that the potential ψs <  < VGS when VGS > VFB, yielding the following final expression of ψs

$$\begin{array}{*{20}c} {q\psi_{s} = 2W_{{T,{\text{DA}}}} .\ln \left( {\frac{{V_{{{\text{GS}}}} - V_{{{\text{FB}}}} }}{{\frac{{\sqrt {\varepsilon_{{{\text{si}}}} 2{\text{kT}}} }}{{C_{{{\text{ox}}}} }}\sqrt {N_{02,3} } }}} \right)} \\ \end{array}$$
(20)

2.2 Drain current model

The free electron concentration, according to the charge sheet model, over the entire depth of the nanowire is as follows:

$$\begin{array}{*{20}c} {n_{{{\text{free}}}} = \mathop \smallint \limits_{0}^{{T_{sc} }} n\left( x \right).{\text{d}}x = \mathop \smallint \limits_{0}^{{T_{sc} }} \frac{n\left( x \right)}{{{\text{d}}\psi }}{\text{d}}\psi {\text{d}}x = \mathop \smallint \limits_{{\psi_{s} }}^{0} \frac{n\left( x \right)}{{\xi \left( x \right)}}{\text{d}}\psi } \\ \end{array}$$
(21)
$$\begin{array}{*{20}c} {n_{{{\text{free}}}} = \frac{{N_{0} }}{{\sqrt {\frac{{2{\text{kT}}}}{{\varepsilon_{{{\text{si}}}} }}N_{02,3} } }}\frac{{2W_{{T,{\text{DA}}}} .{\text{kT}}}}{{2W_{{T,{\text{DA}}}} - {\text{kT}}}}\left( {\frac{{V_{{{\text{GS}}}} - V_{{{\text{FB}}}} }}{{\frac{{\sqrt {\varepsilon_{{{\text{si}}}} 2{\text{kT}}} }}{{C_{{{\text{ox}}}} }}\sqrt {N_{02,3} } }}} \right)^{{\frac{{2W_{{T,{\text{DA}}}} }}{{{\text{kT}}}} - 1}} } \\ \end{array}$$
(22)

According to the MOSFET drain current [22], its expression is

$$\begin{array}{*{20}c} {I_{{{\text{DS}}}} = \frac{W}{L}q\mu_{0} n_{{{\text{free}}}} \mathop \smallint \limits_{{V_{S} }}^{{V_{D} }} {\text{d}}\psi \left( z \right)} \\ \end{array}$$
(23)

where W and L are the width and length of the channel, respectively, µ0 is the mobility of electrons, and ψ(z) is the potential along the channel. The drain current is

$$\begin{array}{*{20}c} {I_{{{\text{DS}}}} = \frac{W}{Z}\frac{{q\mu_{0} N_{0} }}{{\sqrt {\frac{{2{\text{kT}}}}{{\varepsilon_{{{\text{si}}}} }}N_{02,3} } }}\frac{{2W_{{T,{\text{DA}}}} .{\text{kT}}}}{{2W_{{T,{\text{DA}}}} - {\text{kT}}}}\left( {\frac{{V_{{{\text{GS}}}} - V_{{{\text{FB}}}} }}{{\frac{{\sqrt {\varepsilon_{{{\text{si}}}} 2{\text{kT}}} }}{{C_{{{\text{ox}}}} }}\sqrt {N_{02,3} } }}} \right)^{{\frac{{2W_{{T,{\text{DA}}}} }}{{{\text{kT}}}} - 1}} V_{{{\text{DS}}}} } \\ \end{array}$$
(24)

The subthreshold slope is

$$\begin{array}{*{20}c} {{\text{SS}} = \frac{{\ln \left( {10} \right)}}{{\frac{{\partial \ln \left( {I_{{{\text{DS}}}} } \right)}}{{\partial V_{{{\text{GS}}}} }}}} = \ln \left( {10} \right).\frac{{V_{{{\text{GS}}}} - V_{{{\text{FB}}}} }}{{\frac{{2W_{{T,{\text{DA}}}} }}{{{\text{kT}}}} - 1}}} \\ \end{array}$$
(25)

3 Results and discussion

To validate our model, a technology computer-aided design (TCAD) simulation was performed using Silvaco commercial software [19]. Figure 2 displays a three-dimensional (3D) view of the simulated device, and Table 1 summarizes the DOS parameters and the chosen dimensions, similar to the experimental device reported in Ref. [20]. Herein, we focus on the effect of DOS parameters (NTA, WTA, NDA, WDA) on the transfer characteristics. Thus, only one parameter is varied while the others are kept fixed. For reference, IDS(VGS) curves include transfer characteristics fitted with experimental data from Ref. [20].

Fig. 2
figure 2

3D TCAD architecture for the simulated device (not to scale)

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Table 1 Device dimensions and DOS parameters
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Figure 3 displays the transfer characteristics of the model in comparison to the simulation with NTA ranging from 1020 to 1022 cm−3 eV−1. The model and simulation results agree well, demonstrating the validity of our model. When NTA increases, the current above the threshold decreases and the threshold voltage and the subthreshold slope are very weakly affected. Based on (24), only the parameters of the band tail states affect the current, justifying the weak variation of the subthreshold slope according to (25). In contrast, the decrease in the drain current above the threshold is explained by the increase in N02 with NTA. The NTA effect studied in this context agrees with the simulations of Gao et al. [21], highlighting the band tail effect on the drain current when the gate voltage exceeds the threshold voltage. Additionally, from (18), \(\partial {\psi }_{s}/\partial {V}_{GS}\) exhibits a slope independent of NTA, leading to a less pronounced increase in the surface potential when the device operates above the threshold. However, the experimental characteristics exhibit a high threshold voltage and sub-threshold slope. Clearly, the consideration of NTA alone does not afford a DOS representation that brings the model closer to the experimental characteristics.

Fig. 3
figure 3

IDS (VGS) at VDS = 0.5 V for various NTA (WTA = 0.04 eV, NDA = 1018 cm−3 eV−1, WDA = 0.1 eV). Symbol: simulated; line: modeled

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Figure 4 shows the transfer characteristics for WTA varying from 0.04 to 0.08 eV while the other parameters are kept fixed. Obviously, the increase in WTA degrades the device performance as the threshold voltage and subthreshold slope increase and the current above the threshold decreases. Below the threshold, WTA significantly affects the subthreshold slope, which increases according to (25), and the drain current decreases with N02 above the threshold. Given the WTA range considered, only the band tail states describe the total density of the acceptor traps. Compared to NTA, the effect of WTA is clearly seen on the transfer characteristics as the dominant factor of the slopes below and above the threshold.

Fig. 4
figure 4

IDS (VGS) at VDS = 0.5 V for various WTA (NTA = 1021 cm−3 eV−1, NDA = 1018 cm−3 eV−1, WDA = 0.1 eV). Symbol: simulated; line: modeled

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Figure 5 shows the transfer characteristics for WDA varying from 0.3 to 1.1 eV, while the other parameters are kept fixed. In this case, the expression for the current depends on N2 and N3, and an explicit expression for the drain current cannot be formulated with these two quantities together. Indeed, as mentioned earlier, one of the two parameters subsists in the expression of the current. This fact is illustrated in Fig. 6, which displays the variation in N2 and N3 as a function of ψ, where the intersection potential ψi corresponds to N2(ψi) = N3(ψi) and is expressed by:

$$\begin{array}{*{20}c} {q\psi_{i} = \frac{{W_{{{\text{DA}}}} W_{{{\text{TA}}}} }}{{W_{{{\text{DA}}}} - W_{{{\text{TA}}}} }}\ln \left( {\frac{{W_{{{\text{DA}}}} \alpha_{D} B_{D} }}{{W_{{{\text{TA}}}} \alpha_{T} B_{T} }}} \right)} \\ \end{array}$$
(26)
Fig. 5
figure 5

IDS(VGS) at VDS = 0.5 V for various WDA (WTA = 0.04 eV, NTA = 1021 cm−3 eV−1, NDA = 1018 cm−3 eV−1). Symbol: simulated; line: modeled

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Fig. 6
figure 6

N2 and N3 versus ψ for various WDA (WTA = 0.04 eV, NTA = 1021 cm−3 eV−1, NDA = 1018 cm−3 eV−1)

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Thus, based on the value of ψi, we define two currents Ideep and Itail: Above ψi (region above the threshold), the drain current is described by Itail, which depends on N2; N2 is kept fixed in this case. Below ψi (below the threshold), the drain current is described by Ideep, which depends on N3. Figure 7 exhibits the Ideep current as a function of VGS for a limit value of 10−10 A. From the expression of Ideep, the transfer characteristics can be differentiated into two regions with a new threshold voltage and a new subthreshold slope depending on WDA. However, in the region below the threshold and for WDA ≥ 0.7 eV, Ideep is drastically weak to the point of being practically immeasurable. Thus, the current is only present above the threshold of Ideep, which appears in the subthreshold region of the device and whose slope varies very weakly with WDA. This explains the small variation in the slope under the device threshold with increasing WDA. The expression of the potential according to (18) shows that its value is negative even when VGS > VFB. For the region of the channel near the SiO2/poly-SiNW interface, the band diagram will exhibit high curvature of the conduction band that is manifested by a strong decrease in the concentration of free electrons. In other words, the region near the SiO2/poly-SiNW interface is deserted for a positive VGS. On the other hand, a negative surface potential will shift the probability of the occupation function fA(E) back toward energies below EF0, which will drastically reduce the probability that an acceptor trap will be ionized. Hence, the device performance degrades in the region below the threshold.

Fig. 7
figure 7

Ideep (VGS) at VDS = 0.5 V for various WDA values

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Figure 8 shows the transfer characteristics for NDA ranging from 1019 to 1021 cm−3 eV−1. Below an NDA value between 1020 and 1021 cm−3 eV−1, the drain current is described by Itail and Ideep, whose subthreshold slope does not vary with NDA (the part of the very weak currents is not shown in the figure). Above a certain value of NDA, only the deep states influence the drain current, whose decrease above the threshold is due to the increase of N03 with NDA. Figure 9 displays a fit of the model with the experimental data. Compared to the DOS distribution of polycrystalline silicon referenced in the literature [18], the DOS studied herein displays a high density of deep states. As is known, deep states are afforded by the dangling bonds present in disordered silicon, such as microcrystalline or amorphous silicon. Moreover, our previous study [17] clearly showed that the increase in deep states exhaustively explains the conduction mechanism via VRH for poly-SiNWs with small diameters and presents clear insight into their structure. Moreover, the DOS measurements of Le Borgne et al. [14] confirm our results, showing a high density of acceptor states for the TFT back gate based on poly-SiNWs realized by the spacer method.

Fig. 8
figure 8

IDS(VGS) at VDS = 0.5 V for various NDA (WTA = 0.04 eV, NTA = 1021 cm−3 eV−1, WDA = 0.1 eV). Symbol: simulated; line: modeled

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Fig. 9
figure 9

Transfer characteristics fitted with experimental data [20] for NTA = 1021 cm−3 eV−1; WTA = 0.06 eV; NDA = 2.1020 cm−3 eV−1; WDA = 0.1 eV

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In addition to the performance analysis of poly-SiNW TFTs exhibiting a high defect density, the analytical drain current model developed in this work has an interesting advantage. The explanation for all acceptor DOS parameters in the formulation of the model affords a good understanding of the impact of each parameter on the device behavior. Let us recall, among other things, the expression of the ionized acceptor trap density as a function of the potential, the involvement of each parameter, and its effect on operating below or above the threshold regions via the expressions of the densities N02 and N03.

In the case of FETs based on poly-SiNWs, the literature often mentions simulation studies [23,24,25] and shows similar effects of the variation in the DOS on the performance without presenting an analytical formulation. Hence, the importance of our model is that it can be adopted as a reference to develop other models intended for other devices, such as biochemical sensors based on poly-SiNWs whose operation is governed by the interaction of chemical species surrounding the defects present on the surface of the nanowires [26]. Note that although our model concerns the case of an architecture in which the gate modulates the channel on a single face, it can be extended to other architectures such as the double gate or the gate-all-around.

4 Conclusion

We investigated the performance of poly-SiNW TFTs fabricated using the spacer method by developing an analytical model of the drain current, explicitly showing the DOS parameters described by two exponentials. The impact of these parameters on the transfer characteristics demonstrated that the deep states significantly affect the subthreshold region while the tail states affect the region above the threshold. The fit of the model with the experimental data revealed a higher density of deep states than that for polysilicon, which provides extensive insight into the distribution of acceptor traps in the gap, agreeing well with our previous studies on the conduction mechanism and DOS measurement for poly-SiNWs. On the other hand, the explanation of the DOS parameters in the model of the drain current, in the particular case of TFTs based on poly-SiNWs, presents an interesting advantage for the analytical study of the performance of these devices. This supports the proposal of this model as a reference for the study and development of other models for other devices based on poly-SiNWs.