1 Introduction

The ongoing downscaling of semiconductor devices and the requirement to reduce the power consumption density of integrated circuits (ICs) have led to the proposition of many innovative technologies for “More Moore” and “More than Moore” electronics applications [1, 2]. Because the their low power dissipation, TFETs have thus attracted much attention recently and even become serious candidates for use in ultralow-power applications [3, 4]. The carrier injection mechanism in TFETs is based on band to band tunneling (BTBT), resulting in their low energy dissipation and the expectation of a significant reduction in the off-state current in such devices [5, 6]. Furthermore, the subthreshold slope of TFETs can be reduced below 60 mV/dec, which has been proved to be the theoretical limit for conventional metal–oxide–semiconductor field-effect transistors (MOSFETs) [7, 8]. Therefore, TFETs are very energy efficient and can be incorporated into circuits for operation at very low supply voltage targets [9,10,11,12]. However, TFET devices also suffer from low on-state current (ION) and ambipolar current conduction (Iamb) when used in circuits [12,13,14]. The low ION of TFETs is due to the BTBT carrier injection mechanism itself, according to which electrons tunnel from the valence band of the source region to the conduction band of the channel region, or from the valence band of the channel region to the conduction band of the drain region, with the band bending in the energy gap being controlled by the gate bias [15, 16]. The ambipolar conduction in TFETs occurs due to the large BTBT at the source–channel junction as well as the drain–channel junction at different polarities of the gate voltage applied to obtain the drive current. This can prevent the device from turning off completely. As a result, a TFET can show n-type behavior with electrons as the majority carriers as well as p-type behavior with holes as the majority carriers at the same drain voltage [15, 16].

Many ideas have been proposed in literature to boost the drive current of TFETs, including approaches based on the insertion of source pocket (SP) doping [17,18,19], tunneling-area engineering using high-k dielectrics [6, 20, 21], double-gate (DG) architectures [22], gate-to-source overlap [23], gate-to-drain underlap [24], dual-material gates [25], and the use of strained silicon [26]. Meanwhile, the problem of ambipolar conduction can be addressed by adopting various techniques such as a gate–drain underlap [23, 27], Gaussian or nonuniform drain doping [6, 28], work-function engineering of the gate electrodes [29], and spacer and gate material engineering [30, 31].

Several supplementary structures are analyzed stepwise herein to study how the use of a heterogeneous gate dielectric, an HfO2 insulator on the drain side of the gate, and a silicon source stack on the source side can both enhance the drive current and reduce the ambipolar current conduction in comparison with the conventional DG-TFET. Furthermore, the transconductance (gm), gate–drain capacitance (Cgd), gate–source capacitance (Cgs), subthreshold slope (S), and ION/IOFF ratio are also analyzed for the studied structures with a fixed channel length of 50 nm.

The remainder of this manuscript is organized as follows: In Sect. II, the proposed device structures and simulation models are discussed. Section III addresses the electrical characteristics of the devices under study. Finally, the principal findings and conclusions of this paper are presented in Sect. IV.

2 The device structures and simulation parameters

Figure 1 shows a schematic cross-sectional view of the five devices under study. Structure (I) is a conventional DG-TFET with a SiO2 gate dielectric. Structure (II) is similar to the conventional DG-TFET but with an HfO2 gate dielectric. In structure (III), both the gate dielectric and the drain-side insulator are made of HfO2. In structure (IV), a heterogeneous gate dielectric and an HfO2 insulator are applied on the drain side of the gate, while in structure V, a silicon source stack is added to structure (IV). The simulation results are evaluated in comparison with the conventional TFET with structure (I), and the other structures are studied in a stepwise fashion to reveal the effect of applying each modification to the structure on their electrical performance. All the simulation parameters related to the studied structures are presented in Table 1.

Fig. 1
figure 1

A schematic representation of the studied double-gate TFETs: (I) the conventional DG-TFET, (II) the conventional DG-TFET with an HfO2 gate dielectric, (III) the DG-TFET with an HfO2 dielectric on the gate and drain sides, (IV) the DG-TFET with a heterogeneous gate dielectric and an HfO2 insulator on the drain side, and (V) the DG-TFET with a heterogeneous gate dielectric, an HfO2 insulator on the drain side, and a silicon stack on the source side

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Table 1 The parameter values for the structures under study
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All the simulations are carried out using the SILVACO ATLAS version 5.22.1.R technology computer-aided design (TCAD) simulator, applying the nonlocal band-to-band tunneling (BTBT) model to compute the tunneling current in the lateral direction. The bandgap narrowing (BGN) model is utilized to account for the highly doped regions in the devices. The Shockley–Read–Hall (SRH) and Auger models are used to consider the generation/recombination in the simulations. Furthermore, the drift–diffusion carrier transport model and Fermi–Dirac distribution function model are used in the simulations. Tunneling through the gate oxide is ignored, as in Refs. [32,33,34,35]. Since the silicon film thickness is 10 nm, quantum confinement effects arising due to the thin silicon-on-insulator (SOI) body are not considered [36]. The simulation setup is calibrated against the work of Boucart [6], shown in Fig. 2, by considering electron and hole tunneling masses of me = 0.07m0 and mh = 0.71m0, respectively. The primary objective of this work is to consider the combined relative effects of a heterogeneous gate dielectric, an HfO2 insulator on the drain side of the gate and a source stack on the drive current and ambipolar current with respect to the conventional structure by studying the qualitative trends.

Fig. 2
figure 2

The calibration of the simulation results against those presented in Ref. [6] at VDS = 1.0 V

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3 Results and Discussion

Figure 3 depicts the transfer characteristics of the five TFETs at VDS = 1.0 V. It is observed from this figure that the conventional TFET (I) as well as structure TFET (II) exhibit higher ambipolar conduction compared with the other TFETs in this figure at negative gate voltages. At positive gate voltages, is can be seen that TFETs (II), (III), and (V) show the highest drive currents. The behavior of the transfer characteristics of the devices under study can be explained based on their energy band diagram profiles obtained at a cut line placed at 1 nm below the Si–oxide interface, through the silicon active region of the devices, as shown in Fig. 4a, b. According to the Wentzel–Kramers–Brillouin (WKB) approximation, the tunneling probability, T(E), is calculated as [37]:

$$T(E) = \exp \left( { - 2\int\limits_{{_{{x_{{{\text{start}}}} }} }}^{{_{{x_{{{\text{end}}}} }} }} {K(x){\text{d}}x} } \right),$$
(1)

where K is the evanescent wavevector and xstart and xend indicate the start and end points of the tunneling path. Ideally, the start and end points of the tunneling path should be considered in the flat-band (neutral) regions at either side of the junction, where their influence can be calibrated using the carrier effective mass. Then, the calculated tunneling probability for each energy level can be used to calculate the current density [37]. For a thinner tunneling width, the tunneling probability increases [38]. Based on the above theorem and Fig. 4a, it is observed that TFETs (I) and (II) show greater band bending, thus the tunneling width is shorter in their profiles. Therefore, the ambipolar conduction is greater in these devices compared with TFETs (III), (IV), and (V). According to the results shown in this figure, incorporating the HfO2 insulator on the drain side of the gate causes the conduction band (or valence band) slope to decrease. This slope is proportional to the electric field intensity, so this leads to reduced band bending and ambipolar conduction in the devices with an HfO2 insulator on the drain side. On the other hand, Fig. 4b shows that the energy band diagrams of all the TFETs except TFET (I) exhibits an overlap in the tunneling region, so it is expected that they will exhibit the same order of drive current.

Based on Figs. 3 and 4, the role of utilizing HfO2 above the drain side or underneath the gate, a heterogeneous dielectric, and a source stack in the structures can be explained. The results show that the presence of HfO2 dielectric in the whole gate region of TFETs (II) and (III) enables the electrostatic control over the channel by the gate to be strongly increased and thus the drive current to be enhanced, while embedding HfO2 above the drain in TFET (III) leads to a reduction of the ambipolar conduction in this device by about four orders of magnitude compared with the similar structure in TFET (II). As mentioned above, this improvement is due to the formation of a greater tunneling width (Fig. 4a) in the drain–channel junction of TFET (III) compared with TFET (II) due to the incorporation of HfO2 above the drain side. The structural difference between TFETs (III) and (IV) is the embedding of a heterogeneous dielectric in TFET (IV), whose role is revealed by the difference between their ID–VG characteristics. As is obvious from Fig. 3, embedding the heterogeneous dielectric reduces both the drive and ambipolar currents. If fact, utilizing HfO2 on the source side of the gate oxide reduces the tunneling width by increase in the band bending in the channel–source junction, which in turn leads to an enhancement of the drive current. However, the use of a low-k dielectric (SiO2) on the drain side of the gate insulator increases the tunneling width in the channel–drain junction, which reduces the ambipolar conduction in comparison with the conventional structure. The structure of TFET (V) is similar to TFET (IV) but with an additional source stack on the source side. The results shown in Fig. 4b reveal that such incorporation of a silicon source stack reduces the effective tunneling width in the source–channel junction of TFET (V). In fact, as shown by Fig. 4c, the introduction of a source stack leads to the formation of a sharper potential profile in the source–channel junction of structure (V) compared with (IV). This increases the electric field and reduces the tunneling width in the source–channel junction. Therefore, the drive current in TFET (V) is enhanced. It is also obvious that the ambipolar current is comparable to TFET (IV) and the source stack has no effect on it.

Fig. 3
figure 3

The transfer characteristics (ID–VGS) of the five TFETs under study at VDS = 1 V

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Fig. 4
figure 4

The energy band diagrams of the five TFETs at aVGS = −1 V and bVGS = 1.3 V; c the potential profiles of structures (IV) and (V) at VGS = 1.3 V. For all cases, the drain bias is VDS = 1 V

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The amplification can be used as a figure of merit for analog devices, being proportional to the transconductance gm, which is defined as gm = dID/dVGS [39]. A higher gm in a device indicates that the gate has better control over the variation of the device current. Figure 5 shows that this parameter is comparable for TFETs (II), (III), and (V) and much higher than for the conventional TFET (I). Indeed, these improvements are due to the incorporation of the heterogeneous gate dielectric, the HfO2 insulator on the drain side, and the source stack in the mentioned TFET structures. This is due to the fact that these modifications enhance the gate control over the channel, as explained above.

Fig. 5
figure 5

The transconductance of the different TFETs under study at VDS = 1 V

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The effect of incorporating a high-k material (such as HfO2) on the drain side on two important capacitances, viz. the gate–drain (Cgd) and gate–source (Cgs) components, is now investigated, since it may deteriorate these parasitic capacitances [19]. Figure 6 shows that Cgd increases with increasing VGS for all the devices. This is due to the enhanced coupling between the gate and drain charges at higher gate voltages. It is observed from this figure that TFETs (II) and (III) show the highest parasitic components, while for TFETs (IV) and (V), these parasitic components are more comparable to those of the conventional TFET (I). The latter effect is due to the fact that they have a heterogeneous gate dielectric with lower permittivity (εSiO2 = 3.9) on the drain side of their structure, which reduces the coupling between the two terminals. Figure 7 shows that Cgs decreases with increasing VGS for all the devices. This occurs due to the reduced coupling between the gate and source terminals at higher gate voltages, as indicated in Ref. [19]. Since the gate dielectric in TFETs (II) and (III) is uniform HfO2, the parasitic capacitance Cgs is highest for these devices in comparison with all the other devices. In addition, the Cgs of TFETs (IV) and (V) is closer to that of the conventional TFET (I). This result emphasizes the fact that the heterogeneous gate dielectric can cause this parasitic capacitance to become comparable to that in the conventional counterpart. The results shown in Figs. 6 and 7 also reveal that the source stack has no significant effect on the parasitic components Cgd and Cgs.

Fig. 6
figure 6

The gate–drain capacitance versus the gate voltage for the different TFETs at VDS = 1 V and a frequency of 1 MHz

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Fig. 7
figure 7

The gate–source capacitance versus the gate voltage for the different TFETs at VDS = 1 V and a frequency of 1 MHz

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Figure 8 illustrates the ION/IOFF ratio, the subthreshold slope (S), and the ambipolar conduction (Iamb) for the five DG-TFETs under study. It is observed that the incorporation of a heterogeneous gate dielectric (SiO2 and HfO2) along with the source stack can enhance the ION/IOFF ratio and decrease the S parameter. It can also be seen that, for the devices with the HfO2 insulator on the drain side, Iamb is reduced; these results show that TFET (V) offers the best performance in terms of the mentioned parameters due to its supplementary specific structure compared with its counterparts.

Fig. 8
figure 8

The ION/IOFF ratio (black), subthreshold slope (red), and ambipolar drain current (blue) for the five devices under study. IOFF is measured at a bias of VDS = 1 V and VGS = 0 V, while the ambipolar conduction (Iamb) is measured at a bias of VDS = 1 V and VGS = −1 V (Color figure online)

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The influence of the source stack parameters (ts and Ls-ox) and its doping value on the performance of TFET (V) is noteworthy. As depicted in Fig. 9, there is a nonlinear relation between the device current and the source stack thickness (ts) or stack oxide length (Ls-ox). Based on the results shown in this figure, ION and the ION/IOFF current ratio will be close to optimum at ts = 7 nm and Ls-ox = 4 nm, compared with other source stack thicknesses and stack oxide lengths. It is also clear from Fig. 10 that, when the silicon source stack doping value is set to 5 × 1019 cm−3, the ION/IOFF current ratio becomes one order of magnitude higher than for the other two doping values. Moreover, the subthreshold swing (S) parameter for the selected doping of 5 × 1019 cm−3 is slightly lower (14 mV/dec) compared with the other cases. The S parameter for the source stack doping values of 1 × 1019 and 1 × 1020 cm−3 is equal to 16 and 17 mV/dec, respectively. As a result, 5 × 1019 cm−3 is chosen as the optimum source stack doping value.

Fig. 9
figure 9

The ION/IOFF current ratio along with the ION value obtained for structure (V) when varying a the stack thickness, ts and b the source stack oxide length, Ls-ox. The measurements are all taken at a bias of VDS = 1 V and VGS = 1.3 V

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Fig. 10
figure 10

The transfer characteristics of structure (V) obtained for different source stack doping values at VDS = 1 V

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4 Conclusions

The effects of incorporating a heterogeneous gate dielectric, a HfO2 insulator on the drain side of the gate, and a silicon source stack on the electrical characteristics of a double-gate TFET are studied. The results reveal that the incorporation of a heterogeneous gate dielectric along with the HfO2 insulator on the drain side can reduce the ambipolar conduction while retaining low gate–drain and gate–source parasitic capacitances with respect to the conventional double-gate TFET, by forming strong barriers in the drain–channel and channel–source junctions. Embedding the silicon source stack can further enhance the drive current along with the ION/IOFF ratio and reduce the S parameter, while having no strong effect on the mentioned parasitic capacitances. Thus, it seems that TFET (V) exhibits promising electrical behavior for use in low-power applications.