1 Introduction

Moore’s law [1], predicting that the number of transistors per square inch of integrated circuit (IC) or microchip doubles about every 2 years for traditional transistor-based semiconductor technologies such as CMOS and very large-scale integration (VLSI), has been found to be true [1, 2]. However, it now faces many challenges such as increased power consumption [3], thermal dissipation [4], and high lithography costs and leakage current [3, 4]. To solve these problems with CMOS technology, the use of quantum dot cellular automata as an emerging nanoelectronics-based technology was suggested by Lent [5] and demonstrated experimentally in 1997. The major developments in memory elements enabled by QCA technology can play an important role in nanocommunication networks based on devices such as random-access memory (RAM) [6], crossbar schedulers for system-on-chip networks [7], and modern secured static RAM (SRAM)-based true random number generator (TRNG) technology [8]. These devices have a great impact on nanocommunication and secured systems. The molecular fabrication process for QCA supports clocking frequencies in the THz range at room temperature [9]. This work considers synchronous sequential circuits (SSCs) consisting of a combinational circuit and memory element. The memory element is connected through a feedback path, enabling such devices to store binary information. The main contributions of this work are as follows:

  1. 1.

    The proposal of a new, single-layer QCA-based synchronous memory elements with D-type flip-flop (PDT-I, PDT-II) and JK-type flip-flop (PJKT) designs with a reduced number of QCA cells, design area, and area utilization factor (AUF) as calculated using the QCADesign bistable simulation engine.

  2. 2.

    The analysis of the energy dissipation of the PDT-I, PDT-II, and PJKT flip-flops using the novel layout design tool QCADesigner-E in the Coherence Vector (w/Energy) simulation engine.

  3. 3.

    A reduction of the latency of the proposed edge-triggered synchronous sequential circuits based on coplanar crossover quantum cells using the QCADesigner tool, considering a cell size of 18 nm × 18 nm.

  4. 4.

    The calculation of the average output polarization (AOP) of the proposed sequential circuits and graphical plots of temperature versus polarization.

2 Computational procedures

The architecture for the quantum dot cellular automata was designed using the coplanar crossover (single-layer) method with a majority gate (MG), inverter, and quantum wires in a regular (90°) and rotated (45°) QCA cell.

2.1 QCA cell

The fundamental unit of a QCA device is the QCA cell [10, 11], considered here to have the standard size of 18 nm × 18 nm. Each QCA cell contains four quantum dots with diameter of 5 nm, placed on the four corners of a square [11]. Two extra mobile electrons in the square QCA cell (SQC) can tunnel freely between the quantum dots under the effect of columbic repulsion. In this technology, in the null (polarization = 0) state, the electrons are not settled, while other states corresponding to digital logic bistate [12] of zeros (polarizations \(P = - 1\)) and ones (polarization \(P = + 1\)) [13], based on the electron pairs as shown in Fig. 1 [10]. The electrons experience the maximum repulsion in the horizontal/vertical position of the quantum dots and the minimum diagonally, as shown in Fig. 2 [2]. The QCA cell polarization (P) can be calculated using Eq. (1) [14], where \(\rho_{i }\) represents the charge density at the ith point [14, 15]:

$$P = \frac{{\left( {\rho_{1} + \rho_{3} } \right) - \left( {\rho_{2} + \rho_{4} } \right)}}{{(\rho_{1} + \rho_{2} + \rho_{3} + \rho_{4} )}}.$$
(1)
Fig. 1
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The cell polarizations \(P = + 1\) and \(P = - 1\) in the quantum dot cellular automata

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Fig. 2
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The repelled electron positions in a QCA cell

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2.2 QCA wires

The QCA wires are used to transmit information from the origin to the destination in the forward direction based on the electronic interaction between neighboring QCA cells [16], with either a linear 90° arrangement of straight wires, or bent as shown in Fig. 3.

Fig. 3
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a Straight and b–d bent QCA wires, where A is the input and Y is the output

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2.3 The majority voter

The majority voter (MV) lies at the heart of QCA technology. The three-input MV logic gate is presented in Fig. 4a. The majority gate design requires a minimum of five quantum cells, viz. three input cells A, B, and C, a processing cell in the center, and an output cell (Y). The mathematical function for the MG is shown in Eq. (2) [17]:

$${\text{Majority}}\;{\text{logic}}\;{\text{gate}}\;Y\left( {A, B, C} \right) = A \cdot B + B \cdot C + A \cdot C.$$
(2)
Fig. 4
figure 4

The standard QCa gates: a the majority voter, b the two-input AND gate, and C the two-input OR gate

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Gates achieving the other logical operations AND and OR can be obtained from the majority gate by fixing any one of the three inputs to a logical value of \(0\;{\text{for}}\;\left( {P = - 1} \right)\) or \(1\;{\text{for}}\;\left( {P = + 1} \right)\) [17, 18], as shown in Fig. 4b and c, respectively [19].

The function of the AND and OR logic gate is presented in Eqs. (3) and (4). The truth tables of the MG, AND, and OR logical functions using three inputs are presented in Table 1.

$${\text{AND}}\;{\text{logic}}\;{\text{gate}}\;Y\left( {A, B, 0} \right) = AB,$$
(3)
$${\text{OR}}\;{\text{logic}}\;{\text{gate}}\;Y\left( {A, B, 1} \right) = A + B.$$
(4)
Table 1 The truth tables of the majority gate, AND gate, and OR gate
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2.4 Crossover and the QCA inverter

To reduce the complexity as well as quantum cost of QCA design layouts, crossover of QCA wires can be applied using one of two methods, viz. coplanar crossover for a single layer or multilayer crossover for designs with more than one layer. The multilayer coplanar design is shown in Fig. 5a, using different interconnected quantum cells such as the normal cell, crossover cells, vertical (via), and rotated cells. Meanwhile, the basic single-layer designs for a QCA inverter and fan-out circuit are shown in Fig. 5b and c, respectively.

Fig. 5
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Interconnection elements for QCA circuits: a the crossover design, b an inverter, and c a fan-out

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2.5 The QCA clocking mechanism

The clock is one of the important features used to control CMOS circuits. Similarly, a QCA circuit is also controlled by a clock [12], which determines the tunneling barriers between the quantum dots and thus the transfer of electrons [2]. Ultralow-latency computer networks based on QCA circuits can play an important role in enabling resource sharing by facilitating communication between different users [6].

The clocking mechanism is divided into four different \(\pi /2\) phases [1], viz. clock-0: switch, clock-1: hold, clock-2: release, and clock-3: relax [1]. In a QCA design, information propagates in the forward direction [5] from one CLK zone to another, viz. from zone 1 to 2, 2 to 3, 3 to 4, then 4–1, or in the opposite direction if a feedback path is available, with the clocking scheme shown in Fig. 6 [17]. In the JK and data flip-flops, the clock (CLK) pulse is used for synchronization and also acts as an additional control input.

Fig. 6
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QCA synchronization via the four phases of the clock (CLK)

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3 A review of related work

QCA-based nanocommunication is currently a growing field of research, although very few such studies have been reported, mainly being in the field of reversible computing and networking [20]. QCA represents a novel nanotechnology paradigm and a new alternative to transistor-based technologies [21, 22] due to the small size and ultralow power consumption of such devices offering different nanocomputational logical functions [1]. Over the last two decades, QCA devices using quantum cells have had a great impact on circuit design, as well as the development of devices for use in digital circuits. Several designs have been proposed for JK flip-flops to enhance their performance by using a single layer with a bistable simulation engine [16]. Multilayer D and JK flip-flop designs have also been presented [23, 22], as well as synchronous counters and a level-sensitive D flip-flop design [13], and single-layer JK flip-flop and synchronous sequential counter designs [24]. Three different D-type flip-flop and multilayer QCA serial in serial out (SISO) shift register designs were presented by Divshali et al. [14].

4 The proposed design and its specifications

The flip-flop (FF) is an electronic circuit that is widely used in memory devices for digital counters, in telecommunications for information exchange, in spacecraft for many processes, and for the storage of logical data. QCA nanocommunication technology has now developed sufficiently to build a whole variety of types of memory. In QCA-based designs, motion through the cells is required for the memory function; i.e., the memory state must be successively moved through a set of cells [24]. Such synchronous sequential circuits (SSCs) that use a clock pulse at the inputs of the memory elements are called clocked sequential circuits. The FF controls the functionality of the integrated circuit. In this paper proposed Three different layout designs (PDT-I, PDT-II, and PJKT) using a QCA majority gate, 45° rotated cell, and crossover wires are proposed herein with the help of the standard simulation layout design tool QCADesigner (QD, version 2.0.3G) by Schulhof et al. and its modified designer tool QCADesigner-E version 2.2 by Frank Sill Torres et al. The different parameter values used in the tool are presented in Table 2 [25].

Table 2 The standard simulation design parameters used in QCADesigner (QD) and QCADesigner-E (QD-E)
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4.1 The proposed QCA synchronous D-type flip-flops

The implementation and optimization of the first and second edge-triggered synchronous sequential flip-flop designs (PDT-I and PDT-II) proposed herein using QCA technology are described in this section. The layout is described in terms of the quantum cells and the total design area in µm2, consider a maximum number of iterations of 100 per sample, a relaxation time of 1.0e−15 s, and a relative permittivity of 12.9 (corresponding to GaAs and AlGaAs). The first proposed layout (PDT-I) is a robust and simple design with only three, three-input majority voters and one 45° rotated cell for the QCA inverter, and connecting wires formed using the coplanar crossover method. The symbols for the D-FF are shown in Fig. 7, the characteristic mathematical equation of the D flip-flop in Eqs. (5) and (6), and a schematic diagram of the proposed PDT-I in Fig. 8.

Fig. 7
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The symbols for the D-type flip-flop

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Fig. 8
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A schematic diagram of the D-type flip-flop

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For PDT-I, the number of QCA cells is calculated as 23, the total circuit design area as 0.03 µm2, the cell area as 0.075, the percentage area utilization factor (AUF) as 24.84% using Eq. (7), the quantum cost of the overall design area as 0.03 µm2 using Eq. (8), and the cell density as 766.67 cell/µm2. The layout design of the simulated QCA PDT-I is shown in Fig. 9, using three majority voters and one inverter; the active trigger signal and output results are confirmed by the excitation table presented in Table 3. In the excitation table of the D flip-flop, the CLK signal is activated by high = 1, and the input data signal 0 or 1 is stored in the output state (Q); when the clock signal is low = 0, it is deactivated and the output (Q) state will never be affected by any of the inputs. The simulation results of PDT-I are shown in Fig. 10, with a maximum output polarization of 9.56e−01 and minimum output polarization of −9.50e−01, with the output result calculated at clock-3.

$$Q\left( {t + 1} \right)_{\text{next}} = D\bar{Q} + DQ$$
(5)
$$Q\left( {t + 1} \right)_{\text{next}} = D$$
(6)
$$ \% {\text{Area utilization factor}}\;({\text{AUF}}) = \frac{{\text{Net cell Area}}\;(\mu{\text{m}}^{2})}{{\text{Total Area}}\;(\mu{\text{m}}^{2})} \times 100 $$
(7)
$${\text{Quantum cost}} = {\text{Total design area}}\;(\mu{\text{m}}^{2}) \times ({\text{Latenct}})^{2}$$
(8)
Fig. 9
figure 9

The first proposed QCA layout design (PDT-I) for the edge-triggered synchronous sequential D-type FF

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Table 3 The excitation table of the D flip-flop
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Fig. 10
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The simulation results for the first proposed D-type flip-flop (PDT-I)

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A schematic layout of the architecture of the second proposed design (PDT-II) is shown in Fig. 11, consisting of three majority gates using two AND and one OR logic plus one inverter, which is beneficial for the design of digital memory-based sequential circuits. This layout architecture design utilizes 29 QCA cells, with a total design area \(\left( {{\text{length }} \times {\text{width}}} \right)\) of 0.03 µm2, cell area of 0.094 µm2, AUF of 31.32%, and cell density of 966.67 cell/µm2. The operational functionality of the layout is verified by the excitation table presented in Table 3. PDF-II was simulated using QCADesigner 2.0.3, and the generated output results are shown in Fig. 12. Table 4 compares the results obtained for PDT-I and PDT-II with previous QCA designs in terms of the cell count, total design area, latency, and cell area in µm2 (Fig. 13).

Fig. 11
figure 11

The second proposed QCA layout design for the edge-triggered synchronous sequential D-type flip-flop (PDT-II)

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Fig. 12
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The simulation results for the second proposed D-type flip-flop (PDT-II)

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Table 4 A comparison of the results obtained for different D-type flip-flop designs
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Fig. 13
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A comparison of the results obtained for PDT-I and PDT-II versus existing designs

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4.2 The proposed edge-triggered synchronous QCA-PJKT design

The novel design proposed for the JK flip-flop with a QCA architecture for memory storage offers an enhanced reduction in the number of quantum cells, design area, and delay. The edge-triggered JK-FF is a refinement of the SR-FF to solve the indeterminate state problem. In the JK flip-flop, when both inputs are zero (J = K = 0), the output in the next state Q(t + 1) is the same as its previous value, being reset (R) when J = 0, K = 1 and set (S) when J = 1, K = 0. The symbol of the JK flip-flop is shown in Fig. 14, the excitation table is presented in Table 5, while the characteristic mathematical equation of the JK flip-flop is Eq. (9).

$$Q\left( {t + 1} \right)_{\text{next}} = J\bar{Q} + \bar{K}Q.$$
(9)
Fig. 14
figure 14

The symbols for the JK flip-flop

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Table 5 The excitation table of the JK flip-flop
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A schematic diagram of the proposed edge-triggered synchronous JK FF is shown in Fig. 15, while the layout simulated in the QCADesigner-E tool is shown in Fig. 16, incorporating three 45° rotated QCA cells in place of the inverter, five three-input majority gates (MGs), three inputs J, K, and the Clock, and one output-Q in a single-layer coplanar design.

Fig. 15
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A schematic diagram of the JK-type flip-flop

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Fig. 16
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The QCA layout design for the edge-triggered synchronous sequential JK-type flip-flop (PJKT)

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This design has a cell count of 59, the total design area has selection extents of (131.00, 151.00) [178.00 × 338.72] = 60,293.02 nm2 = 0.06 µm2, the cell area is 0.019 µm2, and the utilized area fraction is 31.86%. The JK edge-triggered flip-flop with this layout design passes through four clocks in one zone, and its latency is counted as one clock cycle. The delay or latency can be calculated by using Eq. (10). Information must pass from the input to the output in a number of clock zones (CZ) as described by Frank Sill Torres [25]. The simulation results for the PJKT design are shown in Fig. 17 and compared with those obtained for existing JK flip-flop designs in Table 6 (Fig. 18).

$${\text{Delay}}\;{\text{or}}\;{\text{latency}} = \frac{1}{{4 \times f_{\text{clk}} }} \times {\text{delay }}\left( {{\text{clock}}\;{\text{zones}}} \right).$$
(10)
Fig. 17
figure 17

The simulation results for the proposed JK-type flip-flop (PJKT)

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Table 6 A comparison of the results obtained for the PJKT flip-flop versus existing JK-FF designs
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Fig. 18
figure 18

A comparison of the results obtained for the proposed JK-type flip-flop versus existing designs

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5 The energy calculation for the proposed design

The power dissipated from a quantum cell depends on the rate of change of the tunneling energy and the clock cycle [31]. The energy consumption is calculated using QCADesigner-E with the coherence vector (w/Energy) simulation engine, considering the parameter values presented in Table 2 [25]. The total power dissipated by any nanocommunication-based quantum dot circuit depends on the number of majority gates (MGs) and inverters [32]. Energy dissipation occurs due to loss of information. The heat energy dissipated by the loss of a single bit of information can be expressed by Eq. (11), where \(K_{\text{B}}\) is Boltzmann’s constant (\({\text{K}}_{\text{B}} = 1.3807 \times 10^{ - 23} \,{\text{J K}}^{ - 1}\)) and T is the absolute temperature [33]:

$${\text{Energy}}\;{\text{dissipated}} = K_{\text{B}} T \times \log_{\text{e}} 2\;{\text{J}}.$$
(11)

Tables 7, 8, and 9 present the energy consumption calculated for the PDT-I, PDT-II, and PJKT design, respectively, where E_bath_total (Ebtx) is the sum of all the energy transferred to the bath by all the quantum cells (Ebt1, Ebt2, Ebt3,…..) in each clock, E_clk_total (Ectx) is the total energy transferred (Ect1, Ect2, Ect3,….) between the quantum cells and the clock split by each clock, and in the Ectx column in Tables 7, 8, and 9 a positive sign indicates the receipt of clock energy while a negative sign indicates energy transfer, and E_Error_total is the summation of each error (Eet1, Eet2, Eet3,….) of the cell for every clock. For the whole clock cycle, the sum of the total energy movement by the QCA cell is zero, as represented in Eq. (12) [34].

$${\text{Error}} = E_{\text{bath}} - \left( {E_{\text{clock}} + E_{\text{IO}} } \right).$$
(12)
Table 7 The energy dissipation analysis of the D-type flip-flop (PDT-I) design
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Table 8 The energy dissipation analysis of the D-type flip-flop design (PDT-II)
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Table 9 The energy dissipation analysis of the JK-type flip-flop (PJKT) design
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Sum_bath Sb (Er: Sbe) is the total energy dissipation, where Sb is the energy transfer and Sbe is the related error. Avg_bath Ab (Er: Abe) is the average energy dissipated per clock cycle, where Abe is the average value of the energy transfer or movement to the bath and Sum_clk Sc is the energy moved during the whole simulation. For the whole simulation process, we consider QCA cell dimensions of 18 nm × 18 nm.

For this proposed design, no energy dissipation (Sum_Ebath) and (Avg_Ebath) occurs on average per cycle for the input cells or the fixed input cells of all the majority gates, but the output cell shows an energy dissipation (Sum_Ebath) of 7.84e−005 eV, 1.80e−004 eV, and 3.14e−004 eV and an average energy dissipation per cycle (Avg_Ebath) of 7.12e−006 eV, 1.63e−005 eV, and 2.85e−005 eV for DFF-I, DFF-II, and JK FF, respectively, as calculated using the QCADesigner-E tool.

6 The AOP calculation

The average output polarization (AOP) of an output cell can be calculated as the difference between the maximum and minimum value of polarization (in eV), divided by two, as expressed in Eq. (13) and measured in joules (J) [35]. For the considered example, at T  = 2 K, the maximum polarization is 9.56e−01 and the minimum polarization is −9.50e−01 for the output cell (Output-D) of the DFF-I design, the AOP for output-D is [(9.56e−01) − (− 9.50e−01)]/2 = 3.506 [35], as in Table 10.

$${\text{AOP}}\;{\text{for}}\;{\text{output}}\;{\text{cell }} = \frac{{{\text{Maximum}}\;{\text{polarization}} - {\text{Minimum}}\;{\text{polarization}}}}{2}$$
(13)
Table 10 The average output polarization (AOP) calculated for the PDT-I, PDT-II, and PJKT design
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The AOP versus the temperature of PDT-I, PDT-II, and PJKT flip-flop QCA designs is shown in Fig. 19 for the temperature range of 1–12 K. The AOP of the circuit decreases when raising the temperature but decreases slowly up to T of 1–7 K, in which temperature range the circuit works completed [36]. Table 10 presents the polarity calculated at different temperates, as also presented graphically in Fig. 19.

Fig. 19
figure 19

The average output polarization of the PDT-I, PDT-II, and PJKT designs

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7 Conclusions

Unique QCA-based edge-triggered synchronous sequential flip-flop circuits (PDT-I, PDT-II, and PJKT) without multilayer crossover are presented herein, being very simple and easy to implement in large nanoscale. The first (PDT-I), second (PDT-II), and JK flip-flop (PJKT) designs achieve an 46.51%, 32.55%, and 24.35% improvement in the QCA cell count. Similarly, the area of the PDT-I, PDT-II, and PJKT designs is calculated to be 28.57%, 28.57%, and 14.28%, respectively, being smaller in comparison with the design previously presented by Chakrabarty [18] with 12,800 samples. In addition, the QCADesigner-E (QD-E) simulation tool is used to calculate the energy dissipation, and the AOP at different temperatures (K) of all three designs (PDT-I, PDT-II, and PJKT).