1 Introduction

The discovery of graphene as the first two-dimensional (2D) material and its properties has raised interest in its use in new electronic devices and laid the foundations for many new areas of research [1,2,3,4]. However, the lack of a bandgap in this material has seriously jeopardized its use in various important electronics applications, e.g., in transistors [5, 6]. Indeed, despite extensive efforts, achieving a bandgap larger than 400 meV remains a challenge [5, 7,8,9]. Unlike graphene, other two-dimensional materials such as single layers (SLs) of transition-metal dichalcogenides (TMDs) exhibit a finite and direct bandgap in an appealing energy range [10, 11] and show promising properties for use in electronic applications [12]. These materials form layered structures with weak interlayer van der Waals bonds. Because of this, single layers of these materials can be easily obtained using mechanical or chemical exfoliation techniques [13, 14]. TMDs have therefore been considered for use in electronic devices such as field-effect transistors [15,16,17,18,19]. Liu reported a high-performance n-type monolayer WSe\(_2\) back-gated FET with ON-current of 210 \(\upmu \)A/\(\upmu \)m at \(V_\mathrm{DS} = 3\) V and \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) > 10\(^{6}\), with electron mobility of 142 cm\(^{2}\)/V s [19]. Radisavljevic reported a field-effect transistor with a single layer of MoS\(_2\) semiconductor as the conductive channel and HfO\(_2\) as the gate insulator. At bias voltage \(V_\mathrm{DS}\) of 500 mV, the maximal measured ON-current was 10 \(\upmu \)A (2.5 \(\upmu \)A/\(\upmu \)m), with \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) above \(10^8\) for the 4-V range of \(V_\mathrm{TG}\) and mobility of 200 cm\(^{2}\)/V s [15].

One of the methods to induce strain in TMDs is thermal expansion of the substrate. Introduction of uniform biaxial strain by exploiting the thermal expansion of the substrate has been reported [20]. The effects of strain on the electrical and mechanical properties of TMDs have been studied in several works [20, 21], and it has been shown that the bandgap of TMDs can be controlled via strain [22, 23]. With high tensile strain, the bandgap of TMDs is about zero [24]. The mobility of SL TMDs is strongly modulated by strain, and tensile strain increases the electron mobility [1, 25]. The effect of strain on the mobility of TMDs [25] stimulated us to study the effect of strain on the performance of TMD-based field-effect transistors. We present herein an analysis on the effect of biaxial strain on the DC performance of double-gate field-effect transistors (DGFETs). The methodology is briefly presented in Sect. 2. The effect of strain on DGFET performance is discussed in Sect. 2.1, and concluding remarks are presented in Sect. 3.

Fig. 1
figure 1

The energy minima of the K- and Q-valley under biaxial strain for MoS\(_{2}\) (black), MoSe\(_{2}\) (red), WS\(_{2}\) (blue), and WSe\(_{2}\) (green) [25]

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Table 1 The energy distance between K- and Q-valley
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2 Modeling approach

We used the band structures of single-layer MoS\(_{2}\), MoSe\(_{2}\), WS\(_{2}\), and WSe\(_{2}\) previously calculated [25] in the density functional theory (DFT) framework with the local density approximation. The inset to Fig. 1 shows the Brillouin zone (BZ) of the considered TMDs, identifying the valleys in the conduction band. The angle \(\theta \) describing the orientation of the Q-valleys in k-space is also depicted in this figure. The degeneracies of the lowest (K) and second lowest (Q) valley of the relaxed TMDs are 2 and 6, respectively. Figure 1 shows the energy minima of the K- and Q-valleys as functions of biaxial strain. As shown in this figure, tensile strain increases the energy distance between the valleys. Under small compressive strain, the energy distance between the valleys is reduced. With further increase of the compressive strain, the Q-valley will be the lowest of the conduction band. Table 1 presents the energy distances between these valleys in the conduction band of the relaxed TMDs. In previous theoretical studies, a fairly wide range of values for the energy distance between the K- and Q-valleys has been reported [26,27,28], and unfortunately no experimental verification has yet been reported, except for MoS\(_{2}\) [29].

The effect of strain on the effective mass has been reported [25], revealing that tensile strain decreases (increases) the effective mass of the K-valley (Q-valley), which is instead increased by compressive strain.

The methodology used to analyze the DC performance of FETs depends on the channel length. Carrier transport in FETs is dependent on the relative dimension of the channel length versus the carrier mean free path (MFP). If the channel length is sufficiently larger than the MFP, carrier transport is characterized by conventional mobility theory. In contrast, the scattering probability in a small channel (smaller than the MFP) is negligible, transport is ballistic, and the FET current is completely controlled by the electron injection from the source into the channel [30, 31]. The electron MFP of the transition-metal dichalcogenides is about 9 nm at room temperature, and we assume that the channel length of the DGFETs is smaller than this [32]. We therefore use a ballistic analytical model as the top-of-the-barrier model to assess the DC performance of the DGFETs based on single-layer TMDs (see Fig. 2) [33, 34].

Fig. 2
figure 2

Schematic of the TMD-based double-gate FET with 3-nm HfO\(_{2}\) dielectric, channel length of 8 nm, and power supply of 0.8 V

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Table 2 Comparison of our results with experimental data of [41] for various channel lengths. Single-layer MoS\(_{2}\) was used as the channel of the DGFET. \(V_\mathrm{D} = 0.5\) V and \(V_\mathrm{G}\) is 0.8 and 0 V for ON- and OFF-state (note the shift between the analytical and experimental gate voltage)
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First, the density of states was evaluated as a function of energy using the electronic band structure [1]. Then, the nonequilibrium and equilibrium electron densities can be calculated [33, 34]. The obtained electron density was then used to calculate the self-consistent potential at the top of the barrier along the channel. The calculation of the electron densities and the self-consistent potential at the top of the barrier can be done iteratively to find exact values for the carrier density and self-consistent potential at the top of the barrier. After that, the drain–source current density can be obtained by differencing the fluxes from the source and drain contacts. By modeling the contact as a resistance in series with the intrinsic resistance obtained from the ballistic model of the channel, one can investigate the effect of the contact resistance and the voltage drop across it. A wide range of contact resistance values have been reported in literature [35,36,37,38,39]. In this work, we assumed a junction between the metallic phase of MoS\(_2\) (1T) and its semiconducting phase (2H) with contact resistance of \(75\,\varOmega \,\upmu \)m [40].

The values of \(\alpha _\mathrm{G}\), \(\alpha _\mathrm{D}\), and \(\alpha _\mathrm{S}\) in the ballistic model are given by

$$\begin{aligned} \alpha _\mathrm{G} =\frac{C_\mathrm{G}}{C_\mathrm{T}} \ , \alpha _\mathrm{D} =\frac{C_\mathrm{D}}{C_\mathrm{T}} \ , \alpha _\mathrm{S} =\frac{C_\mathrm{S}}{C_\mathrm{T}} \, \end{aligned}$$
(1)

where \(C_\mathrm{T}\) is the parallel combination of the three capacitors [33]. In this work, these parameter values were calculated by fitting the results to experimental data. The experimental data in Ref. [41] were used to validate our model and calculate \(\alpha _\mathrm{G}\), \(\alpha _\mathrm{D}\), and \(\alpha _\mathrm{S}\). The structure of the investigated DGFET is shown in Fig. 2. The dielectric is 3-nm HfO\(_{2}\), and the strained single-layer transition-metal dichalcogenide is MoS\(_{2}\), MoSe\(_{2}\), WS\(_{2}\) or WSe\(_{2}\). Table 2 reports the experimental data, our fitting factors, and our results for three different channel lengths. For the remainder of this work, it is assumed that the channel length is 8 nm.

2.1 Results and discussion

We investigated the DC performance of this transistor under various biaxial strain values. The maximum investigated strain was 5 %. Figure 3 reports the \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio of the device under biaxial strain. The Fermi level of the source was chosen to adjust the OFF-current density to be 1 nA/\(\upmu \)m; it can be adjusted by changing the work function of the gate and the doping density in the source. In previous works, we investigated electron transport in strained TMDs and reported that, under biaxial strain, electron transport is independent of direction [1, 25]; this investigation shows that the current density of the DGFETs obtained using the ballistic model is also independent of direction.

Fig. 3
figure 3

\(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio of the intrinsic device based on MoS\({_2}\) (black), MoSe\({_2}\) (red), WS\({_2}\) (blue), and WSe\({_2}\) (green) under various biaxial strain values (power supply 0.8 V)

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Comparing the results in Fig. 3 with the minimum energy of the valleys in Fig. 1 reveals that the \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio strongly depends on the energy distance between the valleys. Under small values of compressive strain, the \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio is strongly reduced due to reduction of this energy distance. With further increase of the compressive strain, the Q-valley becomes the lowest, the energy distance between the valleys increases, and the K-valley will not contribute significantly to electron transport. On the other hand, the effective mass of the Q-valley decreases, thus the \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio increases. Under tensile strain, the K-valley is the lowest and the \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio depends on its properties. The enhancement of the energy distance and the reduction of the effective mass of the K-valley under tensile strain will increase the \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio. For all the considered materials, the trend of the \(I_{\mathrm{on}}/I_{\mathrm{off}}\) ratio variation as a function of strain is similar, which can be explained by the variation of the effective mass and energy distance between the K- and Q-valleys with strain.

The energy distance differs between the relaxed materials (Table 1), thus the \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio enhancement under tensile strain will be very different for these materials; For example, the \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio enhancement for MoS\(_{2}\) and WSe\(_{2}\), with energy distance between the valleys of 195 meV and 48 meV, is 8 % and 113 %, respectively.

The total gate capacitance (\(C_\mathrm{G}\)) can be calculated as \(C_\mathrm{G} = \partial Q / \partial V_\mathrm{G}\), where Q is the total channel charge [42]. The gate capacitance of unstrained MoS\(_2\), MoSe\(_2\), WS\(_2\), and WSe\(_2\) is 0.86, 0.99, 0.82, \(0.99\,fF/\upmu m\), while under 5 % strain, it is 0.78, 0.82, 0.68, and \(0.70\,fF/\upmu m\), respectively. These results reveal that not only does tensile strain not increase the gate capacitance but it actually decreases it to some extent. This means that tensile strain increases the \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio and decreases the gate capacitance to some degree, simultaneously. Note that the delay time is proportional to the gate capacitance.

Fig. 4
figure 4

The transfer characteristics of the intrinsic device based on a MoS\({_2}\), b MoSe\({_2}\), c WS\({_2}\), and d WSe\({_2}\) under various biaxial strain values. \(\epsilon _{0}\) is the compressive strain when the energy distance between the valleys is zero (\(V_\mathrm{DS} = 0.8\) V)

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Fig. 5
figure 5

Output characteristics of the intrinsic device based on a MoS\({_2}\), b MoSe\({_2}\), c WS\({_2}\), and d WSe\({_2}\) under various biaxial strain values. \(\epsilon _{0}\) is the compressive strain when the energy distance between the valleys is zero (\(V_\mathrm{GS} = 0.8\) V)

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Fig. 6
figure 6

The \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio of the intrinsic device based on relaxed and strained a MoS\({_2}\), b MoSe\({_2}\), c WS\({_2}\), and d WSe\({_2}\) as a function of the relative dielectric constant (strain value \(+5\) %)

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Figures 4 and 5 report the transfer and output characteristics of the intrinsic device based on the strained TMDs. As seen in these figures, tensile strain increases the ON-current density. Because of the small energy distance between the K- and Q-valley in relaxed WSe\(_{2}\) (Table 1), the ON-current enhancement due to tensile strain for the WSe\(_{2}\)-based DGFET is greater than for the other devices. The ON-current enhancement of the WSe\(_{2}\)-based DGFET under tensile strain is about 115 %.

The effect of small compressive strain on the ON-current is strongly dependent on the energy distance between the valleys in the relaxed TMDs. On the one hand, compressive strain decreases the energy distance between the K- and Q-valley, while on the other hand, it decreases (increases) the effective mass of the Q-valley (K-valley). Small compressive strain therefore decreases the ON-current density, while larger compressive strain partly recovers such ON-current degradation.

As seen in Fig. 5, increasing the ON-current density by strain application increases the saturation voltage of the drain. This saturation voltage enhancement is due to the voltage dropped across the contact resistance. In another words, the \(V_\mathrm{DS}\) of the MOSFET is higher than the voltage drop on the channel.

The effect of the relative dielectric constant on the \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio of the DGFETs based on the relaxed and strained TMDs is reported in Fig. 6. These results indicate that the DGFET with high-\(\kappa \) dielectric has higher \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio.

3 Conclusions

Double-gate FETs based on single-layer MoS\(_2\), MoSe\(_2\), WS\(_2\), and WSe\(_2\) and their DC performance under biaxial strain are presented. The results indicate that tensile strain increases the DC performance of the TMD-based DGFETs, while small compressive strain degrades it. The performance enhancement with tensile strain depends on the energy distance between the K- and Q-valleys. The high performance enhancement of the TMD-based FETs is due to the small energy distance between these valleys for the relaxed TMDs, such as MoSe\(_{2}\) and WSe\(_{2}\). Scaling the channel length decreases the DC performance of the DGFETs. Because of this, all methods that increase the DC performance are valuable, especially introduction of strain, which increases the DC performance while simultaneously decreasing the gate capacitance. Unfortunately, no experimental verification has been reported for the energy distance between the valleys of TMDs, but the trend of the performance enhancement under tensile biaxial strain, which is the main conclusion of this work, remains valid.