1 Introduction

Recently, wireless systems that use millimeter wave and sub-terahertz spectrum have rapidly evolved [1,2,3]. For these applications, a variable gain amplifier (VGA) is needed to improve the dynamic range. A VGA is also used as a main component of the vector-summing phase shifter [4, 5]. In addition, when a VGA is applied to a phased array for a beam-tapering function, the multi-path effect caused by the side lobe level (SLL) can be improved by reducing the SLL [6]. Moreover, controlling the polarization of an antenna by installing a VGA on each port of a dual-polarized antenna can improve the signal-to-noise ratio of the receiver [7, 8]. In particular, in the case of a phase shifter, tapered beam former, and polarization control unit for high-speed communication, minimizing the phase variation is important to prevent distorted radiation pattern or poor cross-polarization.

For these applications, a VGA is typically realized using a cascode topology. For instance, gain-control mechanisms are implemented using a PMOS switch [9], current-splitting technique [10], a variable-transistor transconductance [11], and a current-steering technique [12,13,14,15,16]. The varactor control technique [17] is also applied to a cascode amplifier to achieve a variable-gain function. However, the cascode amplifier suffers from several drawbacks compared with a CS topology, including the following: (1) narrow bandwidth owing to the rapidly changing input/output impedance with frequency and (2) low linearity by assuming that the VDD voltage is constant. Therefore, the CS topology is advantageous in this respect. However, CS VGAs, which exhibit wideband characteristics with minimized phase variation, have not been reported so far.

In this study, we demonstrate a wideband and compact 120-GHz phase-compensated VGA with a p-type metal–oxide–semiconductor (PMOS) switch. In sect. 2, analysis of the gain-control mechanism using the PMOS switch is presented. In sect. 3, the measurement results are provided, and the conclusion of this work is presented in sect. 4.

2 Phase-Compensated VGA with PMOS Switch

The 120-GHz VGA is designed for wireless chip-to-chip communication, and the detailed scenario is described in [18,19,20]. In the current work, the phase-compensated technique has been recently applied to CS VGA to obtain a flat gain in high gain (HG) and low gain (LG) modes and low phase variation.

Figure 1 shows the schematic of the 120-GHz VGA with a PMOS switch. The inter-stage matching network is designed with a single parallel inductor for low insertion loss. For the variable-gain function, the PMOS switch is installed parallel to the inductor from the 4th to the 8th stages. To prevent degradation of the noise figure of the overall amplifier, the PMOS switch is not connected from the 1st to the 3rd stages. The PMOS switches are connected in parallel to the inter-stage matching inductor. Meanwhile, the source is connected to the VDD, and the drain is connected to the drain of the NMOS amplifier. By turning the PMOS switch on and off, the overall gain of the amplifier is controlled by adjusting the parallel resistance of the PMOS. The variables of the VGA are listed in Table 1. Figure 2 shows the schematic and equivalent circuit of the PMOS switch when the latter is turned on and off. The equivalent circuit can be modeled as a parallel resistor and parallel capacitor. When the switch is turned off, the switch operates as an open circuit. When the switch is turned on, the turn-on resistance (Ron) is considerably smaller than the turn-off resistance (Roff). The parallel resistance contributes to the reduction in the unit stage gain of the amplifier due to increment of the damping factor of the amplifier (ζ).

Fig. 1
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Schematic of the 120 GHz VGA with PMOS switch

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Table 1 Variables of the proposed 120 GHz VGA
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Fig. 2
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a Schematic and b Equivalent circuit of the PMOS switch when the PMOS switch is tuned on and off (\( {Z}_{\mathrm{PMOS}}(s)=\frac{1}{s{C}_{\mathrm{on}}}\parallel {R}_{\mathrm{on}}=\frac{R_{\mathrm{on}}}{1- j\omega {C}_{\mathrm{on}}{R}_{\mathrm{on}}} \))

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Table 2 lists the simulated real and imaginary impedances and calculated resistance and capacitance when the PMOS transistor is on and off at 120-GHz. Ron, Roff, Con, and Coff are calculated as 186 Ω, 535 Ω, 3.5 fF, and 2.7 fF, respectively, where Ron is approximately three times smaller than Roff.

Table 2 Simulated real and imaginary impedance and calculated resistance and capacitance when the PMOS transistor is on and off at 120 GHz
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Generally, the gain of the nth-stage amplifier (Gn(s)) is expressed as follows:

$$ {G}_n(s)={A}_n\frac{\upomega_n^2s}{s^2+2{\upzeta}_n{\upomega}_ns+{\upomega}_n^2} $$
(1)

where s = jω, An = gmLn, \( {\omega}_n\left(=\sqrt{\frac{1}{L_n\left({C}_{n,n+1}+{C}_{\mathrm{PMOS}}\right)}}\right) \) is the resonant frequency, and ζn is the damping factor. Ln and CPMOS are inductance of the nth stage of the amplifier and parasitic capacitance of the PMOS switch, respectively. The damping factors in the HG and LG modes are given by

$$ {\upzeta}_{n,\mathrm{HG}}=\frac{1}{2{R}_{n,n+1}\parallel {R}_{\mathrm{off}}}\sqrt{\frac{L_n}{{\mathrm{C}}_{n,n+1}+{C}_{\mathrm{off}}}} $$
(2)
$$ {\upzeta}_{n,\mathrm{LG}}=\frac{1}{2{R}_{n,n+1}\parallel {R}_{\mathrm{on}}}\sqrt{\frac{L_n}{{\mathrm{C}}_{n,n+1}+{C}_{\mathrm{on}}}} $$
(3)

where Coff and Con is parasitic capacitance of the high-gain mode and low gain mode of the PMOS transistor, respectively. Rn, n + 1 is equivalent resistance of the nth stage of the amplifier.

From Eqs. (1) to (3), the relative gain (\( \frac{G_{n, LG}(s)}{G_{n, HG}(s)}\Big) \) of the nth stage is expressed as follows:

$$ \frac{G_{n, LG}(s)}{G_{n, HG}(s)}=\frac{s^2+2{\zeta}_{n, LG}{\omega}_ns+{\omega}_n^2}{s^2+2{\zeta}_{n, HG}{\omega}_ns+{\omega}_n^2} $$
(4)

In the LG mode, the gain is dominantly reduced because ζn, LG is higher than ζn, HG due to the additional parallel resistance from the PMOS switch. Figure 3 shows the simulated relative gain and phase variation in the LG and HG modes in the 4th, 5th, 6th, 7th, and 8th stages. The relative gain and phase variation represent the gain and phase variation between the HG and LG modes, respectively. From Eq. (4), the relative gain at the nth stage at frequency ωn is ζn, LG/ζn, HG (= 10log(ζn, LG/ζn, HG) dB). At ωn ≪ ω and ωn ≫ ω, the relative gain converges to one (= 0 dB). Therefore, the relative gain at the nth stage monotonically decreases from the DC frequency and monotonically increases after ωn. The VGA is designed to have a flat gain in the LG and HG modes by setting the gain-variation stage at low and high frequencies. From Eq. (4), when ω is substituted to ωn + ∆ωn, the phase variation in the nth stage (∆θn) is given as

$$ \Delta {\theta}_n\sim {\tan}^{-1}\left(\frac{\left(-{\omega}_n\Delta {\omega}_n\right)}{\zeta_{n, LG}\left({\omega}_n^2+2{\omega}_n\Delta {\omega}_n\right)}\right)-{\tan}^{-1}\left(\frac{\left(-{\omega}_n\Delta {\omega}_n\right)}{\zeta_{n, HG}\left({\omega}_n^2+2{\omega}_n\Delta {\omega}_n\right)}\right) $$
(5)
Fig. 3
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Simulated a relative gain and b phase variation in the LG and HG modes for the 4th, 5th, 6th, 7th, and 8th stages

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Equation (5) shows that, if ∆ωn is negative, ∆θn is positive. In contrast, if ∆ωn is positive, ∆θn is negative. In the 7th and 8th stages, because the center frequency of 120 GHz is larger than the resonating frequency in the seventh stage, ∆ω7 and ∆ω8 are positive, and ∆θ7 and ∆θ8 are negative. On the other hand, ∆θ4, ∆θ5, and ∆θ6 are positive. In this manner, the VGA is designed by applying the phase-compensated technique so that the phase variation approaches zero near the center frequency.

Figure 4 shows gain frequency response with continuous bias tuning. It is shown that gain is continuously controlled by tuning the control bias voltage. In this work, only two states (Vctrl = 1 and Vctrl = 0) are measured to be applied for polarization control unit.

Fig. 4
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Gain frequency response with continuous bias tuning

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3 Measurement Results

Figure 5 shows the fabricated 120-GHz VGA. The amplifier is fabricated using the 40-nm CMOS process. The addition of the PMOS switches does not affect the total chip area, and the total chip area is 450 μm × 500 μm. The total DC power consumption of the amplifier is 45 mW. Figure 6 shows the S11, S22, and gain of the amplifier. The measured S11 is less than −9 dB from 104.9 to 136.2 GHz, whereas the measured S22 is less than −9 dB from 93.3 to 141.4 GHz. Furthermore, the measured peak gains are 19.1 dB in the HG state and 13 dB in the LG state. The 3-dB gain bandwidths are 33.8 GHz in the HG state and 40.2 GHz in the LG state. The discontinuity at 110 GHz occurs because the S-parameter from 90 to 150 GHz is measured by a W-band (from 90 to 110 GHz) and D-band (from 110 to 150 GHz) vector network analyzer (VNA). Figure 7 shows the simulated and measured P1dB for the HG and LG states of the VGA. For the HG and LG states, the OP1dB values are −2.7 and −2.6 dBm, respectively. Figure 8 shows the simulated and measured phase difference of the VGA. The phase variation of the amplifier is 15.5° within the 3-dB-gain bandwidth (102.9–136.7 GHz). If the VGA is applied to polarization control unit [9], the cross-polarization could be lower than at least −11.46 dB with 15.5° phase variation. Moreover, the measured phase variation is less than 2° in the 15.1-GHz frequency band that ranges from 100.9 to 115 GHz by implementing the phase-compensated technique. Figure 9 shows the simulated and measured group delay in the HG and LG states. The similar group delay characteristics are revealed compared to [21], and measured group delay is lower than 50 ps. Figure 10 shows the simulated and measured noise figures in the HG and LG states. The measured average noise figures are 8.5 and 8.9 dB in the HG and LG modes, respectively. Figure 11 shows the simulated IIP3 values of the HG and LG states. The simulated IIP3 values are −17.5 and dB −13.9 dB in the HG and LG modes, respectively. Table 3 lists the performance of the CMOS VGAs in the millimeter-wave frequencies. The CS amplifier with a PMOS switch exhibits the widest bandwidth than the other reported VGAs owing to the application of the CS topology. The presented VGA is advantageous for system integration because it uses a relatively small area compared with the number of stages.

Fig. 5
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Chip micrograph of the proposed amplifier

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Fig. 6
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S11, S22, and gain of the proposed amplifier

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Fig. 7
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Simulated and measured P1dB in high- and low-gain states of the proposed VGA

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Fig. 8
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Simulated and measured phase difference of the proposed VGA

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Fig. 9
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Simulated and measured group delay in the high- and low-gain states of the proposed VGA

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Fig. 10
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Simulated and measured noise figure in the high- and low-gain states of the proposed VGA

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Fig. 11
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Simulated IIP3 in the high- and low-gain states of the proposed VGA. The IIP3 is simulated for 5-GHz offset

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Table 3 Reported CMOS VGAs for the millimeter-wave frequencies
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4 Conclusion

A wideband 120-GHz phase-compensated VGA with a PMOS switch is presented. The measured gain and 3-dB bandwidth of the VGA are 19.1 dB and 33.8 GHz, respectively, while consuming DC power of 45 mW in the HG state. The OP1dB is −2.7 dBm, and the phase variation between the HG and LG states are 15.5° and 2° in the 3-dB gain bandwidth and 15.1-GHz frequency band, respectively.