1 Introduction

The continuously increasing demands for higher data rate have increased attentions to phased arrays for nowadays communication systems. At the expense of hardware complexity, a higher signal-to-noise ratio is achievable in such a system where a high-performance phase shifter is a key building block to combine multi-phase signals effectively [21, 25, 31]. As for circuit implementation, with the rapid progress of silicon based radio-frequency integrated circuits (RFICs), it is possible to implement a fully-integrated phase-array system with low power consumption by taking the advantage of the highest level of integration using the CMOS technology [21, 25, 31]. Phase shifters with different topologies such as passive reciprocal networks type using transmission lines [21, 25, 31] , lumped elements networks [2, 17], vector modulated type [3, 29, 30], and other topologies [18, 24], have been extensively reported. And recently, many work implemented in advanced CMOS technology, with lower power or high-frequency operations has been reported in [1, 15, 27]. Unfortunately, a phase shifter with high frequency, accurate phase control, small silicon area, low power consumption, low loss variation within the entire working frequency range, etc., remains a great challenge. The design strategy of a phase shifter should be determined based on different applications. For example, an active vector modulator phase shifter exhibits high gain at the cost of high DC power and complexity with additional digital control circuits. By contrast, passive phase shifters usually exhibit better linearity without DC power consuming but with a certain insert loss which requires additional link budget in a communication system. In addition, the passive components in the passive phase shifter, such as transmission lines occupy a considerably large silicon area, making it less attractive in CMOS fully-integrated system. The tuning mechanism of the phase shift is another key consideration, vector summer can only provide certain phase shifts with several-bit of resolution, e.g., a 4-bit 360∘ phase shifter in 22.5∘ steps, using digital switches [27] (e.g., 22.5∘ for 3-bit operation, using digital switches). The alternative solution, a continuously varying phase shifter is able to work at a limited range only. It is therefore not possible to conclude an uniform solution to a communication system. But considering the rapid progress of millimetre wave range phase array mobile system with a high level of integration, it is of a great interest if the phase shifter can be implemented with acceptable phase accuracy, small silicon area and low power consumption. In this paper, a K-band phase shifter is presented to meet these requirements. The theoretical analysis of the phase shift in a LC tank based oscillator is presented, followed by the optimisation of the performance matrix as well as the silicon verification of the prototype in a commercial 0.13 μ m CMOS technology.

2 Design Consideration

In a K-band fully-integrated mobile communication system, the silicon area and power consumption become the major design considerations once the accuracy of the phase shifter is secured. The passive design is less attractive due to large silicon areas occupied by the passive devices [21]. The large power consumption and limited resolutions in a vector summer based phase shifter are the major drawbacks. As a design example, a K-band vector-sum phase shifter with a resolution of 22.5∘ requires a total power consumption of 25.2 mW as reported in [23]. Phase shifts based on injection locked voltage controlled oscillators have been reported as a good candidate to solve these issues [11, 26]. They has been widely used in designing quadrature (fix phase of 90∘) oscillator [9, 10, 14] or phase shifters [1, 4, 11, 26, 27]. Unfortunately, the oscillator is sensitive to process, voltage, and temperature (PVT) variations. The total linear phase tuning range is thus very limited and unstable. It is therefore of a great importance to perform a detailed analysis of this topology and to perform optimizations accordingly.

2.1 Physical Model of the Injection Locked Oscillator

A simplified scheme of injection locked oscillator (ILO) can be modeled as an oscillator locked to an external signal source, as shown in Fig. 1.

Fig. 1
figure 1

An oscillator can be injected by a source and output a same frequency wave in a very special circumstance

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The circuit works as a free running oscillator without an input signal. But the oscillator will tracks the input frequency at a certain frequency range close to its self-resonant frequency, which is called injection locking. For an oscillator with the free running frequency of ω 0, which is locked in with an input signal I inj (at the frequency of ω inj), as shown in Fig. 2, the working condition can be derived as follows.

Fig. 2
figure 2

An oscillator injected by I inj having an output current of I out

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As illustrated in Fig. 3,

$$ \mathbf{I}_{\text{{out}}} = \mathbf{I}_{\text{{inj}}} + \mathbf{I}_{\text{{osc}}} $$
(1)
Fig. 3
figure 3

The sum of the vectors of I inj and I osc is I out [22]

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It is assumed that the angle between I inj and I osc is 𝜃 and the angle between I out and I osc is φ, the relationship between 𝜃 and φ can be written as.

$$ \frac{I_{\text{out}}}{\sin\theta} = \frac{I_{\text{inj}}}{\sin\varphi} $$
(2)
$$ \sin\varphi = \frac{I_{\text{{inj}}}}{I_{\text{{out}}}}\sin\theta $$
(3)

According to Eq. 1,

$$ \sin\varphi = \frac{I_{\text{{inj}}} \sin\theta }{\sqrt{I_{\text{{out}}}^{2}+I_{\text{{osc}}}^{2}+2\cos\theta I_{\text{{out}}}I_{\text{{osc}}}}} $$
(4)

When I inj ≪ I osc , then

$$ \sin\varphi = \frac{I_{\text{{inj}}}}{I_{\text{{osc}}}}\sin\theta $$
(5)

Considering Z(ω) represents the impedance of the resonance circuit, then

$$\begin{array}{@{}rcl@{}} Z(\omega) &=& j\left( \omega L -\frac{1}{\omega C}\right)+R_{\text{{L}}} \end{array} $$
(6a)
$$\begin{array}{@{}rcl@{}} &=& j(\omega^{2} -\omega_{\text{{0}}}^{2})\frac{L}{\omega}+R_{\text{{L}}} \end{array} $$
(6b)

Where R L is the loss of the tank and ω 0 = 1L C is the resonant frequency of the tank.

Since ω is close to ω 0, so

$$ \omega^{2} -\omega_{\text{{0}}}^{2} \approx{} 2\omega (\omega - \omega_{\text{{0}}}) $$
(7)

Equations 7 and 6a gives

$$ Z(\omega) \approx{} 2j(\omega - \omega_{\text{{0}}})L+R_{\text{{L}}} $$
(8)

The phase shift φ of the tank is given as:

$$ \varphi \approx{} \arctan\left( \frac{2(\omega - \omega_{\text{{0}}})L}{R_{\text{{L}}}}\right) $$
(9)

Considering \(Q_{\text {{ext}}}=\frac {L\omega _{\text {{0}}}}{R_{\text {{L}}}}\) to be the external quality factor, Eq. 9 can be re-written as

$$ \tan \varphi \approx{} \frac{2(\omega - \omega_{\text{{0}}})Q_{\text{{ext}}}}{\omega_{\text{{0}}}} $$
(10)

When I inj ≪ I osc, φ is small enough to make sinφ ≈tanφ,

$$ \sin \theta \approx{} \frac{2(\omega - \omega_{\text{{0}}})Q_{\text{{ext}}}}{\omega_{\text{{0}}}} \cdot \frac{I_{\text{{osc}}}}{I_{\text{{inj}}}} $$
(11)

The phase shift between injected signal and output, 𝜃 − φ ≈ 𝜃 (at the extreme case that φ is so small that can be ignored), can now be approximated as

$$ \theta \approx{} \arcsin\left( \frac{2(\omega - \omega_{\text{{0}}})Q_{\text{{ext}}}}{\omega_{\text{{0}}}} \cdot \frac{I_{\text{{osc}}}}{I_{\text{{inj}}}}\right) $$
(12)

Supposing the injection source is a stable oscillation source, function of 𝜃 is relevant to ω 0, Q ext and I osc.

$$ \theta \approx{} F_{\text{{ps}}}(\omega_{\text{{0}}},Q_{\text{{ext}}},I_{\text{{osc}}}) $$
(13)

The phase shift depends on at least three design parameters. It is possible to change ω 0, Q ext, or I osc to obtain the phase shift as suggested in Eq. 13. Given a constant Q ext and ω 0, e.g., Q ext = 10 and f = 24 GHz, the phase shift vs. I osc can be illustrated in Fig. 4. Moreover, Fig. 5 suggests that phase shift is strongly linear over I osc/I inj if Δω = ω − ω 0, the frequency shift, is small enough, which suggests that to adjust the phase shift by controlling I osc is a high linearity way.

Fig. 4
figure 4

Phase shift created by oscillator injected by a stable oscillation source when Q ext = 10, f = 24 GHz with different Δω

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Fig. 5
figure 5

The slopes of the phase shift curves with different Δω

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Unfortunately, the range of phase shift is quite limited in this solution, as illustrated in Fig. 4. Likewise, the changing of Q ext(while I osc and ω 0 is locked) exhibits similar characteristic. Tuning ω 0 to change the phase induces the largest phase shift range, because

$$ {\Delta}\omega \approx{} \frac{\omega_{\text{{0}}}}{2Q_{\text{{ext}}}} \cdot \frac{I_{\text{{inj}}}}{I_{\text{{osc}}}} \cdot \sin\theta $$
(14)

Δω reaches maximum value

$$ {\Delta}\omega_{\max} = \frac{\omega_{\text{{0}}}}{2Q_{\text{{ext}}}} \cdot \frac{I_{\text{{inj}}}}{I_{\text{{osc}}}} $$
(15)

when sin𝜃 = 1, or maximum absolute value

$$ {\Delta}\omega_{\text{{-max}}} = -\frac{\omega_{\text{{0}}}}{2Q_{\text{{ext}}}} \cdot \frac{I_{\text{{inj}}}}{I_{\text{{osc}}}} $$
(16)

when sin𝜃 = −1. [ω + Δω -max,ω + Δω max] is the locking range. If ω 0 is able to reach both lower and upper bound, 180∘ phase shift can be achieved theoretically.

2.2 Voltage-Controlled Oscillator

2.2.1 General Design Considerations

Supposing the oscillator of the ILO mentioned above is designed as a voltage controlled oscillator(VCO), it is possible to obtain variable phase shifts by changing the free running frequency of the VCO, ω 0. Both ring oscillators [1, 7, 13, 28] and LC oscillators [9, 11, 19, 26, 27] can be possibly implemented as a phase shifter. Considering the working range of tens of GHz, only the LC tank based VCO as shown in Fig. 6a is analyzed in this work.

Fig. 6
figure 6

Schematic diagram of LC-VCOs

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The working frequency of this ILO (Fig. 6b), ω 0 is given as Eq. 17

$$ \omega_{\text{{0}}} = \omega \cdot \left( \frac{1}{2Q_{\text{{ext}}}} \cdot \frac{I_{\text{{inj}}}}{I_{\text{{osc}}}} \cdot \sin\theta + 1 \right)^{-1} $$
(17)

The major challenge in the frequency tuning of the VCO is the optimization of the varactor, which has been widely used to change the effective load capacitance in the LC tank. The strong desire of wide tuning range of capacitance is actually limited by the minimal required quality factor. The sizing of the varactor is thus one of the key trade-offs. As illustrated in Eq. 14 and [16], a tank with low quality factor, Q ext, is preferred if a larger locking range is desired. However, it is risky to design a low Q ext tank which results in a larger power consumption and poor phase noise performance.

2.2.2 Optimisation of the LC Tank

The key issue in this design will be the optimisation of the LC tank. The operating frequency and quality factor of the oscillator can be determined as follows.

Considering the tank as a parallel LC circuit, the relationship between the inductor, the capacitor and the quality factor of the tank, Q tank, can be addressed as (18)

$$ Q_{\text{{tank}}} = \frac{1}{\frac{1}{Q_{\text{{L}}}}+\frac{1}{Q_{\text{{C}}}}} $$
(18)

where

$$ Q_{\text{{L}}} = \frac{\omega_{\text{{0}}}L}{R_{\text{{L}}}} $$
(19)
$$ Q_{\text{{C}}} = \frac{1}{\omega_{\text{{0}}}CR_{\text{{C}}}} $$
(20)

At a relatively low frequency, the Q L is the dominator of the Q tank. But at K-Band, the quality factor of both the inductor and capacitor are important. To achieve a high resonant frequency, the L tank and the C tank of the tank circuit should be determined as:

$$ \omega_{\text{{0}}} = \frac{1}{\sqrt{LC}} $$
(21)

Where L ≈ L tank and \(C \approx {} \frac {1}{\frac {1}{C_{\text {{tank}}}}+\frac {1}{C_{\text {{para.total}}}}}\)(C para.total refers to the total parasitic capacitance).

As mentioned in Eq. 14, low Q tank results in a larger locking range at the expenses of large device (C para.total) and total power consumption.

According to Eqs. 14, 15 and 16, if the minimum VCO working frequency is larger than the lower bound(or the maximum working frequency is smaller than the upper bound), the Δω is too small for the sin𝜃 to reach −1 (or 1), thus shrinking the phase shift range. Which also means that, to achieve full 180∘ phase shift, the locking range needs to be located within the VCO frequency tuning range. In this work, the term “full 180∘ range” refers to “the frequency range of the input which can be shifted 180∘ by the phase shifter” to address this issue. Figure 7a shows how the full 180∘ range almost covers the entire frequency range. If the locking range is much larger and not ignorable, full 180∘ range will shrink, as shown in Fig. 7b. Assuming a wide locking range which is even larger than the frequency range as shown in Fig. 7c, the phase shift generated by this ILO can never achieve 180∘. Meanwhile, it can be concluded that small locking range are more sensitive to tuning voltage (a small deviation on tuning voltage), which suggest that the large locking range topology exhibits a higher precision.

Fig. 7
figure 7

Three kinds of locking and frequency ranges ratios

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By taking the advantage of the unique characteristic of varactor capacitance curve, fine tuning of phase shift is now possible. Figure 8 shows the C-V curve of the varactor used in this work, which has a lower slope at around −0.4 V and higher slope at around 0 V. If the injection is just located at the frequency when varactor is biased at −0.4 V, the ΔC/ΔV is small so that the phase changes smoothly. When V tune is 0 V, phase tuning around this biasing condition is the best way to perform a coarse tuning. It should be noticed that the coarse tuning area exhibits better linearity than the fine tuning area [27], which suggests that the low ΔC/ΔV area may also affect the linearity or precision.

Fig. 8
figure 8

A typical normalized varactor capacitance curve

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High-quality factor means higher power efficiency, but it narrows the locking range down and the phase shifts are more sensitive to control voltage(harmful to the precision of phase shift). Besides, to maintain a high-quality factor at a given frequency, lumped elements of the circuit should be balanced and properly sized as suggested in Eq. 21. For example, if MIM capacitors (MIMs) are sized to be smaller (both capacitance and size) to increase the quality factor, the inductors need to be larger (usually both inductance and size). If quality factor is lowered to increase the precision, the power consumption is increased when using larger transistors. The increased parasitic capacitance that grows with power consumption will also narrow the frequency range down. Although a narrow frequency range results in a better precision, the frequency shift generated by model mismatch and small working bandwidth are additional issues.

3 Circuit Design

A guideline is therefore summarized to design the ILO based phase shifter with a good balance among these design considerations.

  1. Step 1.

    Design a VCO circuit, which covers the desired working range. The quality factor of the LC tank can be determined subject to different applications. For example, to have a smaller silicon area, a small inductor without significant Q decrease is usually preferred.

  2. Step 2.

    Determine the locking range. One of the three kinds of schemes, which are shown in Fig. 7, can be selected to set a goal in future quality factor optimisation. Larger locking range needs lower Q in small signal condition while smaller one needs higher.

  3. Step 3.

    Tank optimization. Since the locking range has been determined, the tank should be adjusted to achieve the target quality factor. The sizing of both inductors and capacitors are possible solutions in tuning the tank quality factor. Higher quality factor usually means smaller inductors or MIMs but it may cause frequency up-shift. The width and length of each finger of MOS varactors can be reduced to have higher quality factor at the cost of narrow scaling range [6, 32]. Considering the large silicon area contributed by the inductor, a smaller inductor is always preferred, hence the change of inductors should be at the lowest priority.

  4. Step 4.

    Circuit optimization. The negative resistance path consumes most of the power and brings large amount of parasitic capacitance. Back to step 3 once the path changes and repeat this procedure until a satisfied result is achieved. Offsets of frequency can be set to re-locate the locking range at the desired frequency range in low ΔC/ΔV area at the cost of lower linearity, as shown in Fig. 7.

As a design example, an injection locked oscillator phase shifter(core of the circuit) is designed under this guideline. The K-band phase shifter is implemented in a commercial 0.13 μm RF CMOS technology. The schematic is based on the conventional topology shown in Fig. 6b. The input signal is injected at the tail transistor of the oscillator. Buffers are used to isolate the oscillator from output port, or power will be drained from the oscillation cycle and the circuit can hardly oscillate. Low power and small silicon area are the key considerations in this design. The LC tank is designed to have a mid-frequency range to solve frequency drift problems and with 180∘ frequency coverage. A high-quality factor is designed to achieve a low power operation.

3.1 Optimization

The inductor and capacitor should be properly sized to reach the target frequency at K-band. For example, 0.9 nH L tank need about 1.9 pF C tank to achieve around 24 GHz. Since the C tank can be adjust in future without much area consideration and it is desirable to have a certain margin of potential parasitics, a smaller capacitor is used in this design.

Equation 14 suggests that both lowering the Q ext and increasing the I inj are helpful to enlarge the locking range. However, both solutions increase the I osc and thus increasing power consumption [5, 12, 20]. The first and second schemes in Fig. 7 are preferred in this design. These schemes exhibit a slightly lower precision but a lower power (high Q) and full 180∘ phase shift are achieved compared with the third scheme in Fig. 7.

Further optimization can be performed as well. The varactors of the tank are shown in Fig. 9, where C 0 are used to keep varactors in zero voltage biasing. Since a mid-frequency range is chosen to improve the precision, small L varactors can be used to lower the scale ability. Ratios of C 0 and varactors also have related with the scale ability and quality factor, as illustrated in Fig. 10.

Fig. 9
figure 9

Varactors are zero biased by blocking DC voltage from negative-resistance path

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Fig. 10
figure 10

Scaling ratio (left) and normalized Q C of the capacitor circuit (right). The circuit has a fix maximum capacitance and C 0 vary along with fingers of varactors

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Supposing the capacitor circuit of the tank has a fix maximum capacitance, the capacitance of C 0 should be decreased when the fingers of MOS varactors increase (W and L remained) and vice versa. This will affect the scaling ratio and Q C of the capacitor circuit. It can be seen in Fig. 10 that ratios goes down as fingers grow while Q C has a maximum value at about 22 fingers. Since neither maximum Q nor maximum frequency range is the goal of optimisation, the number of fingers can be determined within [10,22].

Usually, the negative-resistance path consumes most of the power of the phase shifter. Reducing the biasing current of the path is an essential way to lower the power consumption. That means the width or the number of fingers of the transistors should be kept as small as possible. However, changing the size of the transistor will have a side-effect, changing the parasitic capacitance. The C tank has to be increased to maintain desired phase shifts within the same frequency range, since the parasitic capacitance has been lowered unconsciously. Besides, considering the efficiency of signal injection and redundancy of process variations, the path still need further adjustments.

Based on this design strategy, the parameters of instances of the tank can be determined as Table 1.

Table 1 Instances of the tank
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For simplicity, the input network is not perfectly matched to a perfect 50 Ohm match to save silicon area. In case there is a need of inject efficiency, the matching work can be added [8].

4 Simulation and Experiment Results

In this paper, the complete schematic of the proposed circuit is shown in Fig. 11. The V inj is the injection port(also the input port) while the RF + and RF − is both connected to the 50-Ohm port. V tune is used to change the VCO working frequency. Buffers are added to isolate the core from output port. Under proper DC condition, the input of the circuit is connected to an input frequency source, the output will locked in to the input and generate tunable output with certain phase shifts. The proposed circuit is simulated using Cadence Spectre RF with EM extraction of critical interconnections.

Fig. 11
figure 11

Complete schematic of the proposed circuit

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The circuit is first simulated as a VCO. It can be seen in Fig. 12 that the frequency increase along with the V tune and has a tuning range of about 1.5 GHz, from 23.5 to 25.0 GHz in periodic steady state (PSS) analysis.

Fig. 12
figure 12

Frequency and output power of output signal when V tune from − 1 V to 1 V

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To verify the stability of the phase tuning, post-layout transient simulations at different operating frequencies and tuning voltages are performed as well. In these simulations, the amplitude of the injected signal is set to be 550 mV. Figures 13 and 14 implies that with the increase of V tune, phase increases as well, which verifies the theoretical analysis above. The increase rate of the phase is about 1.3∘/mV. In this case, voltage steps around 8.65 mV can make 11.25∘ shifts. A polar plot, Fig. 15, also shows that the output amplitude variation is smaller than 0.5 dBV from 23.8 to 24.4 GHz. As shown in Fig. 13, the phase noise variation is smaller than 8 dB from 23.8 to 24.4 GHz at 100 kHz offset.

Fig. 13
figure 13

Simulated phase noise at various frequency at 100 kHz offset

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Fig. 14
figure 14

Related phase and amplitude vs. V tune

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Fig. 15
figure 15

Polar plot of output amplitude vs. phase at various frequency

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The circuit is fabricated using Grace Semiconductor Manufacturing Corporation(GSMC) 0.13 μm RF CMOS technology. Die photo of the circuit is shown in Fig. 16, which occupies an silicon area of about 540 μm × 620 μm (including I/O pads) or about 316 μm × 388 μm (excluding I/O pads). The on-wafer measurement is carried out using an Agilent MXA Signal Analyzer N9020A with a Cascade Probe Station. RF probes are attached to the GSGSG (output) pads on die. All measurement with a DC power consumption of ILO core of about 3.14 mW with a DC Voltage of 1.2 V. A spectrum measurement is performed at the very first stage. Figure 17 shows the ILO has a frequency range of 22 ∼ 23.4 GHz.

Fig. 16
figure 16

Die photo of the phase shifter

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Fig. 17
figure 17

Frequency range of the VCO

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Compared Fig. 17 with Fig. 14, it is clear that the operating frequency and tuning range of the oscillator reduce considerably. This is due to insufficient EM extraction of interconnections and inaccurate device model at tens of GHz. The working frequency in measurement is about 22 to 23.4 GHz with a range of 1.4 GHz.

The S-parameter measurement is on an R&S ZVA67 network analyzer (VNA) with same Probe Station. RF probes calibrated through the on-wafer 12-term TOSM calibration are attached to the GSG(input) and GSGSG(output) pads on die. The measured S-parameters are shown in Figs. 18 and 19.

Fig. 18
figure 18

Normalized data of phase shift vs. Freq at different V tune

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Fig. 19
figure 19

Normalized data of phase shift vs. V tune at different frequency

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As can be seen in Fig. 19, with the increase of V tune, phase shift drops and the range of it is about 180∘, almost reach the theoretically maximum range. Compared with the simulation results, the locking range is smaller and the increase rate of the phase is even larger, about 4∘/mV. In this case, to be used as a phase shifter, the V tune should be precisely controlled to achieve desired phase shift, e.g., a high 10-bit DAC to provide 1 mV steps. Table 2 summarizes the proposed work with literatures, which suggests the successful implementation of a low power phase shifter with a small silicon area.

Table 2 Phase shifters using ILO method
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5 Conclusion

An ILO-based phase shifters in K-band with continuous phase tuning is proposed. Several key design considerations have been analyzed to reach a design strategy of a low cost and low power operation at K-band. The proposed phase shifter is implemented using a 0.13 μm CMOS technology. Measurement results show that the proposed design is able to provide about 180 degree phase shift continuously while consuming 3.14 mW from a 1.2 V supply voltage.