1 Introduction

It is expected that CMOS technology will reach the fundamental physical limits in the near future [7] by its property like power dissipation and short-channel effects, which intern will degrade the performance in the nano-scale. So as to conquer these issues and to proceed with, the researcher has proposed many new technologies in recent past years like Quantum-dot Cellular Automata (QCA) [38, 44], Single Electron Device (SED) [41], Molecular Electronics [10], Resonant Tunneling Diodes (RTD)[18] to name a few. Among these feasible alternative approaches, QCA is more promising technology with the striking concept of quantum dots to the traditional CMOS technology [20]. This transistor-less paradigm capable of computing in nano-scale offering remarkable lead as high density, low power consumption, and performing at high speed with terahertz frequency [35, 40] and operates by the accommodation of electrons.

A square-shaped QCA cell is made up of four dots with two electrons doped inside it. Majority voter gate [29] and inverter [13] are the basic components for QCA design. A polarized state of a cell is engendered via QCA wire. The signal transition occurs with the influence of the clocking signal, unlike the current flow as, in the case of CMOS [32].

The right and effective polarization of QCA cells are empowered by an external clock signals [21], through which the potential barriers can be controlled within the quantum dots. These clock zones are also defined by these clock signals. With these foundations, many circuits in sequential, as well as the combinational approach in QCA have been proposed so far [2, 23, 25, 31, 36, 37, 39]. Woefully, most of the cases, the proposed works have a diversion from the use of a regular clocking circuit.

Apart from that, the incorporation of the interconnect issue in any electronic device must be addressed. Generally, a wire-crossing can be implemented by passing one wire over the other [5, 28]. Clock phase-based wire crossing directly affects the cost of the circuit, because, with the increase of clock phase, the latency also increases. On the other hand, rotated cell-based crossing or multi-layer based wire crossing results in a circuit with fabrication issue, as doping of rotated cell or incorporating a number of layers is still an area of concern in implementing the practical logic circuitry. Therefore, using a large number of wire-crossing leads to downscaling of the circuit and increasing the complexity of cost efficiency and fabrication. Thus, it is important to ensure the minimum amount of wire crossing in a coplanar architecture.

An appropriate clocking scheme has an important significance in developing the specification of logic design in QCA technology. Few clocking schemes for QCA had been reported in [6, 12, 19, 33, 45, 47]. The prior three are neither universal nor even complete in terms of efficiency, flexibility, and scalability. They do not even support the feedback path, which is not a suitable choice for sequential circuits. A clocking with the feedback path is realized in [45], with an increased number of cells, and the complexity of the circuit. It has been addressed by in [6] but, there exists wire crossing in it. The RES clocking scheme [12] emerged as an alternative utilizing coplanar wire crossing with three directional information flow facility. As the clock zone “3” does not relay a regular underlying metal wire, it incorporates more underlying metal wire crossings, thus increasing the fabrication overhead. Optimized 2-D clock in proposed in [47], incorporating these issues with no metal wire crossing. However, the cost of wires increases extensively with the expansion of the clocking or realizing the larger circuitry.

All these matters of contention have motivated us to think and design a new Efficient, Scalable & Regular (ESR) clocking scheme with reliability, scalability, and, more importantly, with a reduced number or elimination of underlying wire crossing. This paper presents a novel clocking scheme and also capable of realizing QCA circuits as efficiently as the earlier schemes. The proposed clocking scheme is fabricable using fabrication technologies, which can convert the circuit to realistic and practical. The research contributions in this work include the followings:

  • A new clocking scheme is proposed for the QCA logic circuit.

  • The proposed clocking scheme enables optimum underlying wire crossing to reduce the fabrication complexity.

  • It permits the development of QCA circuits with a feedback path facility.

  • The scalability and performance analysis of the proposed clocking scheme is presented, which outperforms all the existing schemes.

  • Both combinational and sequential design is simulated using the proposed ESR clocking scheme.

  • QCADesigner tool has verified the functionality of the design.

This research primarily focuses on proposing a new ESR clocking and realize combinational and sequential design using the same. The rest of the paper is organized in the following manner; Sect. 2 discusses the basics of QCA. In Sect. 3, a literature review of different existing underlying clocking schemes has been made. The Proposed clocking is being illustrated in Sect. 4. Section 5 deals with the performance analysis of the proposed design using the proposed ESR clocking, and lastly, concluded in Sect. 6.

Fig. 1
figure 1

Basic structural components of QCA

Full size image

2 QCA basic elements

The fundamental structure of QCA cell is illustrated in Fig. 1(a), it is a square-shaped block unit and consists of four different dot regularly distributed in the corners. A pair of electrons resides within it, due to the coulombic force of repulsion it takes diagonal position [19]. They represent the digital logic bit (1 or 0) by cell polarization (+1 or \(-\)1) depending on cell arrangement in either diagonal. Figure 1 captures the concepts in a frame. The Majority gate (Fig. 1(c) plays a dominant role in designing QCA circuits [11, 27]. The functional logic is expressed as \(Output(F) = P.Q + Q.R + R.P\) which is usually represented as Maj(P, Q, R) with 3 inputs P, Q and R. With the help of this gate and the polarization property of QCA cell, the basic logic gate like OR & AND can be realized by applying +1 & \(-\)1 respectively in one of the inputs [4, 24]. The wire in QCA comprises of array of cells to propagate the value from input to output or the intermediate circuitry. The inverters for the opposite polarization of input cell can be realized with cell arranged as Fig. 1(d). Wire-Crossing: While fabricating, the interconnection of QCA wires needs special care for a better stabilized circuit. The coplanar approach, as depicted in Fig. 1(b-i) (Rotated Cell based crossing) & Fig. 1(b-ii) (Clock zone based crossing) and Multi-layer (Fig. 1b-iii) approach are commonly used crossover methods. The coplanar approach uses two different types of QCA cells for crossing. In contrast, the Multi-layer approach is implemented with more than one cell layer like multiple metal layers, as in the case of traditional IC.

Clocking To control the flow of data and to supply power to automation in the QCA clock is used, which intern controls the flow of information. The clocking is realized by controlling the potential barrier, which generates four operating phases [43]. Figure 1(e) demonstrates the clocking concept and different zones with separate colors. The barriers between dots start rising in the locking stage, followed by a locked stage, where the situation occurs when barriers are fully raised, which restricts the electron move between dots. In the relaxing stage, the tunneling barriers start lowering and finally completely lowered in a relaxed stage where electrons can move freely at this stage [1, 42]. Alternatively, these phases are known as the Switch phase, Hold phase, Release and Relax phase, respectively [34].

Fig. 2
figure 2

Different existing Regular Clocking Schemes based on QCA

Full size image

3 Related work

Present status of Wire crossing Coplanar wire crossing consists \(90^0\) and \(45^0\) orientated cell in opposite directional wire (Fig. 1b-i), may lead to cell misalignment resulting in cross-coupling and ultimately decreases the robustness of the circuit [3]. The second mechanism (Multi-layer, Fig. 1b-iii) yields in a costly circuit as creating layers while fabrication in QCA is an issue till date [8]. Wire crossing can also be implemented utilizing the clock zones (Fig. 1(b)-ii), where the switch, and release phase is crossed and the cells in the hold and relax phase are crossed, without any polarization effect [9]. It utilizes all four phases, which also increases the clocking count and gradually increases the QCA cost of a circuit, too [22]. Considering all these points, it is utmost required to minimize the number of wire crossing (if not possible to eliminate) to design a robust, cost-effective, and fabricatable QCA circuit.

Fig. 3
figure 3

Schematic view of QCA Underlying Clocking

Full size image

Present status of Clocking scheme On the other hand, clocking has an expandable role in realizing the QCA circuits with unique benefits like restoration of lost signal and attenuation. In the present scenario of QCA, most of the work emphasizes cell count in a clock zone, which lacks any established rules. It typically doesn’t legitimize their choice and also disregards the clocking circuit implementation, which is responsible for generating the clock regions. The tunneling barrier between the quantum dots are induced or prompted by the electric field, which generates the clocking in QCA. The commonly known approach, where Carbon Nanotubes [26] or the metal wire are buried underneath the layers of QCA cell (see Fig. 3), to realize the underlying clocking circuits is proposed in [14]. This section discusses the different clocking schemes available in QCA.

One-Dimensional Clocking Scheme The concept of QCA clocking was first proposed by [19] with a uni-dimensional placement of the clocking zones, also known as the One-Dimensional Clocking Scheme. Having this base, a later study in [14, 17] suggested it should be a regular, bounded shape and uniform as well. As depicted in Fig. 2(a), it divides the clock zones along with the horizontal axis only. Thus, the enlargement of QCA wire in any sophisticated design along with the vertical axis keeps them in the same zone. Whereas, the vertical line could make a significant contribution to the circuit. Though the clocking demands can be fulfilled, it prevents the execution of feedback paths.

Two-Dimensional Clocking Scheme Different problems like wire length difference, non uniform clock zone width, the difference in cell number between zones, and importantly feedback path and un-utilized area have been reported in [30] proposing Trapezoidal and the Universal clocking scheme. But neither the scheme was revealed, nor the zones were equal in shape and size. Hence, a formal proposal for two-dimensional clocking schemes reported in [45] with bi-directional input and output facility. The most encouraging 2DDWave scheme is based on a grid of rectangular clock zones having the same size (Fig. 2b). The thermodynamic effects due to the large QCA wire length have been able to be avoided. However, the implementation of a sequential circuit remains an issue due to the uncertainty of realizing the feedback path.

Regular Cell based Clocking Scheme A new clocking scheme is proposed in [33] based on one-dimensional technique primarily aims in avoiding the use rotated cell in wire crossing as in case of 2DDWave, instead using regular cells only for the flawless flow of information as shown in Fig. 2(c). Here, the circuit is divided into many regular clock zones for each clock phase in a uni-directional way, as in 1-Dimensional clocking. But the same issue of feedback path remains along with the QCA cost, as the clock zone increases multiple times.

USE Clocking Scheme A Universal, Scalable, and Efficient (USE) clocking scheme facilitates the effective implementation of feedback, proposed in [6]. The clock zones with immediate effect of data propagation are kept together (like clock zone 0 propagates data to zone 1, zone 2 propagates to zone 3 and so on), as shown in Fig. 2(d). There are four grids with a loop facility automatically maintaining the clock zones. It also maintains the opposite directional transformation of information in the adjacent rows and columns. An electric field generation circuitry is proposed for the regular clock zones where metal wires are buried diagonally under the layer. It is to be noted that, it integrates underlying metal wire crossing for the circuit realization. Additionally, in this scheme, multi-layer cross over is entertained for circuit synthesis, which is not a proper or suitable method for fabrication.

RES Clocking Scheme The Robust, Efficient and Scalable (RES) clocking scheme is proposed in [12]. It utilizes only coplanar wire crossing eliminating the cons of USE clocking. Unnecessary white spaces created for opposite directional cell placement to achieve routing purpose as in case of USE have been taken care of by fixing the cell below the top left corner to clock zone 1 as shown with a red marker in Fig. 2(e). Three directional flow of information has been considered as an added benefit. In achieving the advantages described above, this scheme lacks in generating a uniform underlying layout for the particular clock zone 3. It is responsible for unnecessary wire crossing under the QCA layer, and at the same time, the complexity of fabrication also increases.

Optimized 2-D Clocking Scheme A new tile structured timing scheme is proposed in [47], which is capable of realizing all functionalities of existing clocking. The optimized 2-D clocking scheme, as shown in Fig. 2(f), resolves the trouble of underlying metal wire crossing. According to the proposed structure, it acquires a rectangular shape clock zone having a 2:1 aspect ratio. Importantly, it indicates a clocking circuitry with no wire crossing. However, a shift in the blocks (clock zone) in the consecutive row makes it practically difficult to fabricate. It facilitates bi-directional information propagation only in each block or zone. Moreover, the wiring cost (the number of wires) gets doubled with the addition of every single row.

Compiling these clocking schemes, it can be concluded that, underlying metal wire crossing is a matter of concern for fabrication. The wiring cost should also be considered and at the same time. The clocking scheme must be well defined as two-dimensional clocking, uniform, and flexible like USE, robust and scalable similar to RES and optimized in metal wire crossing like Optimized 2-D clock for the design of cost effective circuits with feedback. The next section proposes ESR clocking scheme complying with these demands.

4 Proposed ESR clocking scheme

In this section, a novel timing scheme for the nanotechnology based QCA circuit is proposed. The proposed clocking scheme bears a resemblance to the drawbacks of 2DDWave, Regular Cell based clocking, USE & RES clocking with a significant reduction in underlying metal wire crossing.

Fig. 4
figure 4

Clock zone arrangement for the proposed ESR scheme

Full size image

As suggested in RES [12], just having side by side opposite direction may lead to unnecessary white spaces in the circuit. So, the transmission directions in the proposed scheme are not always opposite to each other. The placement of clock zones are regular and uniform with the interacting zones together like USE [6]. The interacting zones are kept adjacent to each other (As an example, clock 2 interacts with clock 3, clock 4 interacts with clock 1 and so on). It can be noticed that the upper two rows are arranged like 2DDWave with bi-directional inputs and outputs. However, the feedback loop can be realized in the bottom rows, which is suitable for the sequential circuit. A square zone based proposed Efficient, Scalable & Regular (ESR) clocking scheme is depicted in Fig. 4. The proposed clocking circuitry used to electric field generation for the clock zones indicating the metal wire orientation and wire crossing (shown in Fig. 5). The proposed clocking scheme provides a homogeneous electric field with the metal wire distributed over a single clocking zone. The clock generator proposed here can be realized using the fabrication technique used CMOS technology[15].

Fig. 5
figure 5

Clocking circuitry of proposed ESR clocking scheme

Full size image

It (proposed ESR clocking) allows a straight line, a zig-zag line and a feedback loop with a minimum metal wire crossing. Both directional feedback (clockwise or anti-clockwise) can also be utilized, which is vital for sequential circuit and memory design lowering the burden as shown in Fig. 6(a). According to the area or size of the circuit, the proposed clocking scheme can be expanded as and when required, as referred in Fig. 6(b) with an outline of the overview of clocking circuitry on expansion. It is observed that clock zone ’1’ and clock zone ’3’ are configured a zig-zag like a pattern; thus, it can also be named as Zig-Zag clocking scheme. All the clock zones follow a predefined direction of information flow and also with an existence of a feedback path. Additionally, with the advent of zig-zag direction, this scheme also allows three-directional input as well as output, which improves the fan-out of the circuit. If the zig-zag pattern of clock zone ’3’ is noticed, then it can be observed that, when it makes a cross over with clock zone 4, it facilitates a three dimensional input from clock 3 to clock 4. While making a cross over with clock 2, it has the three-dimensional output from clock 2 to clock 3. Similarly, clock zone 1 creates three-dimensional input and output on the cross over with clock zone 2 and clock zone 4, respectively.

Fig. 6
figure 6

Expandability & Scalability of the proposed ESR clocking scheme

Full size image

It is worth mention that the proposed clocking scheme takes all advantages of previously known timing schemes and introduces a new scheme combining them with a minimal metal wire crossing. However, considering the optimization of wire crossing and complexity of buildabilty/fabrication it is required to eliminate the underlying metal wire crossing. The optimized 2-D timing scheme with the structure of a tile, as proposed in [47], deals with this issue. But, the metal wire complexity also increases as the number of wires gets doubled for each row expanded for the realization of a large or complex circuit. Considering the optimization of wire crossing, and at the same time, the wiring complexity, an alternative wire orientation is at this moment proposed in Fig. 7. It can be observed that the underlying metal wire crossings are eliminated with optimization in wire complexity. The diagonal orientation of metal wire reduces the increase in the number of wires with the extension of grids according to the circuit area.

Fig. 7
figure 7

Alternate metal wire orientation for ESR, eliminating underlying wire crossing

Full size image

5 Performance analysis and discussion

In this section, the comparative study of the proposed scheme with the previously known better schemes of clocking in terms of metal wire crossing is discussed. The basic combinational and sequential circuit using this scheme is implemented to prove the acceptability and applicability of proposed scheme and also compared with metrics of the circuits using Two dimensional (2-DDWave), Universal, Scalable and Efficient (USE), Robust, Efficient and Scalable (RES) and Optimized 2-D (Tiles) timing scheme for the same design.

5.1 Structural comparison

To permit metal wire crossing, an extra metal layer has to be utilized and to generate uniform electric field, the implementation of metal pad is required in a third layer below each clock zone (see Fig. 3).

Fig. 8
figure 8

Underlying Metal Crossing in RES, USE and Optimized 2-D Clocking respectively

Full size image

So, to reduce the fabrication overhead, metal wire crossing needs to be reduced in number. With this technique along with diagonal orientation of wire to minimize complexity, the clocking circuitry for USE, RES, and Optimized 2-D clocking (Tiles) are shown in Fig. 8. The underlying metal wire crossing for corresponding schemes are marked as red circles. Besides the advantages of ESR clocking, the reduction in the metal wire crossing perceptible as compared to USE, RES or Optimized 2-D in the circuitry to generate the electric fields, which yields a lower complexity and cost-effective circuit design.

Table 1 Structural Comparison with \(4\times 4\) grid
Full size table

Table 1 shows the comparison table based on the \(4\times 4\) structural grid. It can be noticed in this table that, 2DDWave clocking scheme may be implemented with no wire crossing, but it fails in providing feedback path. However, it can generate feedback with a long-distance wire by placing six (6) rotated grid of cells as reported in [45], which produces an extensive number of underlying wire crossing, and also the fabrication constraint remains very high. It also shows that the metal wire crossing reduced to two (2) as compared to six (6) in the case of USE and four (4) as in RES. Considering the wire orientation as Fig. 8(c), the proposed ESR clock also reduces wire crossing as compared to three (3) in Optimized 2-D (Tiles) scheme. Along with these, it provides three-dimensional input and output as compared to input at one point in RES. This facility is not available in the case of 2DDWave, USE, or Optimized 2-D clocking scheme. Moreover, the alternate orientation for wire, as proposed in Fig. 7, optimizes the underlying meta wire crossing as it succeeds in eliminating the same.

5.2 Circuit realization

To comply with the applicability of the proposed ESR clocking scheme, both combinational and sequential circuits are designed. A 2:1 Multiplexer which plays an an important role in boolean function recognition & circuit designs and the SR-Latch, the basic in the sequential circuit are compared to its counter design using 2DDWave clocking, USE clocking, and RES clocking scheme. All results are based on simulations with the QCADesigner [46] tool version 2.0.3 in the coherence vector simulation engine mode.

5.2.1 2:1 Multiplexer

A 2-to-1 multiplexer is presented following the design principle of the proposed ESR clocking scheme with the schematic, as shown in Fig. 9.

Fig. 9
figure 9

The schematic diagram for 2:1 MUX implementation

Full size image

QCADesigner based implementation of the 2-1 multiplexer circuit using the proposed clock scheme is displayed in Fig. 10(a). The simulated waveform of the proposed 2-1 multiplexer, as depicted in 10(b), verifies the output and operations of the design.

Fig. 10
figure 10

2:1 Multiplexer a Cell Layout using the proposed ESR and b Simulated Output

Full size image

5.2.2 SR Latch

The sequential circuit (SR Latch) is designed with the proposed ESR clocking scheme to comply with the realization of the feedback path. The schematic diagram for the SR Latch can be found in Fig. 11, as discussed in[12, 16].

Fig. 11
figure 11

The schematic diagram for SR Latch implementation

Full size image

Figure 12(a) depicts the clock zones for SR-Latch using proposed ESR clocking, and the simulation results are highlighted in Fig. 12(b). The simulation waveform confirms the sequence of order as hold, reset, set and hold; with the input vectors S = 0000 1111; R = 0101 0101 and the output Q = X011 1011. This affirms the exact functionality of the SR latch.

Fig. 12
figure 12

SR Latch a Cell Layout using the proposed ESR and b Simulated Output

Full size image
Table 2 Performance Comparison of ESR clocking scheme
Full size table

The proposed circuits are compared with the counterpart designs in 2-DDWave [45], USE [6], RES [12] & Optimized 2-D (Tiles) [47] clocking scheme in respect to the metrics like Cell count, Area, and latency. The comparative analysis is presented in Table 2. A significant improvement is observed for all parameters. In this table, the last row considers the linear wire orientation in each row of Tiles clocking scheme as presented in [47] and the alternative wire orientation of the proposed ESR clocking scheme. All the analytical results verify the superiority and flexibility of the proposed clocking scheme.

6 Conclusion

In this paper, an Efficient, Scalable & Regular (ESR) clocking scheme is established, which reduces wire-crossing drastically in the underlying clocking circuit. In the comparison of the \(4\times 4\) grid of the clocking layout, it outperform the existing clocking schemes achieving 50% and above fewer wire-crossings. At the same time, the alternate approach for wire layout delivers optimum performance eliminating the wire crossing in underlying metal wire. It also enables feedback paths with small loops incurring less area and can apply current integrated circuit fabrication technologies to realize efficient clocking circuitry. Case studies presented in this paper advocates the prominence of an area reduction of factors 3 to 5 and delay decrease by up to factor 3 in comparison with an existing advanced clocking scheme. Besides, it’s worth noting to mention that the single timing region of the clock phase under our proposed timing scheme is larger than the region under other timing schemes for a particular circuit, which also eradicates the need for excessive clock zone. Thus, the proposed scheme simplifies the development of placement and routing algorithms for QCA technology by its all-round flexibility.

In future works, algorithms for automatic placement and routing of future QCA standard cells using the proposed clocking scheme can be developed.