1 Introduction

The incredible demand for high performance ADC is forcing towards the employ of dynamic comparator to optimize the speed-power trade-off. In most of all ICs, a significant component called ADC, that bridges the gap between the analog world and the digital systems, is used. The comparator forms the main heart of any ADC architecture used in contemporary technology for conversion from analog to digital and vice versa. The accuracy of such converters has strong relation on design of inter stage gain amplifier and comparator.

The performance of a comparator will determine overall performance of A/D converter because of large number of comparators is used compared to inter stage gain amplifier. The large number of comparator makes it the most critical block of a ADC architecture, not allowing efficient background calibration of all the comparators which directly affects the effective resolution of the ADC due to the comparator input offset voltage.

The overall performance of ADC the speed and the power consumption of the comparator have significant effect; owing to the enormous number of comparisons in ADC [2]. The speed of the ADC is prime concern for high speed digital system and speed of comparator is the key factor [3]. The prerequisite to prolong the battery life of the digital system, speed and accuracy of the ADC is major concern; for comparator it is essential to have low offset, high speed with optimum power. In recent years the emphasis has been given towards the design of high speed comparator with power optimization. The comparator circuits should be immune to speed, power and offset trade off.

Several approaches have been proposed in the literature discussed either differential architecture or double tail architecture with offset voltage varies from 10 to 50 mV. In comparators, a lower offset comes at the cost of bigger transistor dimension therefore it will lead to more power dissipation and increased in delay. In addition, the traditional comparators are difficult to design and there are not many design procedures to diminish the offset voltage. To decrease power spending and area of the comparators, dynamic comparators are proposed [3,4,5,6]. However, such comparators generally experience comparatively large offset voltage in comparison to static comparators [6, 7]. Some designs have been proposed for dynamic comparators in the literatures. The dynamic comparators are categorized into three groups: Resistor divider [6], Differential pair and Charge Sharing dynamic comparator [6]. Other structures are mainly derived from these architectures [3,4,5,6,7,8].

The designs proposed in literature, few are anxious with speed [7], few give emphasis to power optimization and enhance resolution [2], some on offset elimination [6]. In this paper authors come out with novel design one with low offset with optimum power and speed.

In order to break the deadlock between offset and power consumption authors have proposed novel architecture which combines the features of differential pair and double tail. The proposed architecture is more robust against any misalignment and non idealities. More importantly, it involves a significantly smaller input offset voltage without sacrificing speed and power penalty.

The paper is organized in 5 sections; Sect. 2 discussed the existing architecture of fully differential dynamic comparator (FDDC). Section 3 presents the novel architecture of fully differential double tail dynamic comparator (FDDTDC). Section 4 discussed the design consideration and simulation results, Sect. 5 conclude the paper.

2 Existing architectures of fully differential dynamic comparator

The existing fully differential dynamic comparator (FDDC) structure is illustrated in Fig. 1 [7]. When Фclk goes high comparator makes the decision. For the tail clock signal, an identical phase controlled voltage swing clock has been employed rather using same clock which swing from V SS to V DD . To ensure tail current remains in the saturation the limited clock swing is used for tail transistor M5 and make sure that tail current not enter into linear region.

Fig. 1
figure 1

(Reproduced with the permission from [7])

Fully differential dynamic comparator (FDDC).

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All transistors M1–M4 are of the equal dimension and perfectly balance to ensure all input transistors have same currents the differential pair V in + and V ref + (and V in − and V ref −) are grouped in single differential pair [4, 5]. During the time of decision all input transistors will contribute respectively.

The inner nodes are reset to V DD when comparator is in ideal mode and help comparator to retune all the nodes prior to the comparator enters into the evaluation mode.

3 Proposed comparator

The fully differential double tail dynamic comparator (FDDTDC) is illustrated in Fig. 2. Some modification has been made to the structure in comparison to the structure shown in Fig. 1. Transistors M13 and M14 are removed from the structure because transistors MA and MB will serve the same purpose to reset the internal nodes D 1 and D 2 . On the removal of two clock driven transistors M13 and M14 the power dissipation of the comparator has drastically reduced in comparison to FDDC. The FDDTDC can work at lower supply voltages in comparison to the FDDC due less stacking.

Fig. 2
figure 2

Proposed fully differential double tail dynamic comparator (FDDTDC)

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3.1 Operation of the proposed comparator

Reset Mode: When Φ Clk is low, transistors MA, MB, M9 and M12 are on. Out+ and Out− are precharge to VDD similarly inner nodes D 1 and D 2 are retune to VDD.

Comparison Mode: When Φ Clk is high, Φ Clk,B is active, transistors MA, MB, M9 and M12 are off. Out+ and Out− are discharge to ground through M1–M4. If the voltage at V + in is higher than the voltage at V − in (V + in > V − in ), Out− is discharged faster than Out+. The addition of two transistors of the MA and MB convert the single tail comparator into double tail comparator with differential input and on removal of transistors M13 and M14 reduced the power dissipation and reduces the offset voltage with moderate increase in propagation delay.

3.2 Performance analysis

The comparator depends on many aspects of the performance parameter. The parameters such as gain, offset, kickback noise, linearity, overdrive recovery, speed and supply voltage are important along with speed and power dissipation, and. In practice, comparator design is a multi-dimensional optimization problem because most of these constraints deal with each other. The performance analysis for offset voltage, delay and power is presented in the following subsection.

3.2.1 Offset

By definition, the offset voltage V OS of the comparator equals to the differential input voltage that establishes the condition V + out  = V − out .

In the beginning of the decision moment, M1 to M4 and M5 are in the saturation region. This is the main reason of the low sensitivity of this topology to the transistor mismatch as will be demonstrate hereafter. If all the transistors of the two differential pairs have the same dimensions, β 1 = β 2 = β 3 = β 4 , then in the balanced point the two output currents are equal [8, 9].

$$I_{O}^{ + } = I_{D7} , I_{O}^{ - } = I_{D8} , I_{D7} = I_{D8} , I_{D7} = M_{2} + M_{4} , I_{D8} = M_{1} + M_{3}$$
(1)
$$I_{ds1} = \mu_{1} C_{ox} \cdot \left( {\frac{{W_{1} }}{{L_{1} }}} \right) \cdot \left( {V_{in + } + \Delta V_{in} - V_{t1} - \frac{{V_{ds1} }}{2}} \right) \cdot V_{ds1}$$
(2)
$$I_{ds2} = \mu_{2} C_{ox} \cdot \left( {\frac{{W_{2} }}{{L_{2} }}} \right) \cdot \left( {V_{ref + } - V_{t2} - \frac{{V_{ds1} }}{2}} \right) \cdot V_{ds1}$$
(3)
$$I_{ds3} = \mu_{3} C_{ox} \cdot \left( {\frac{{W_{3} }}{{L_{3} }}} \right) \cdot \left( {V_{ref - } - V_{t3} - \frac{{V_{ds3} }}{2}} \right) \cdot V_{ds3}$$
(4)
$$I_{ds4} = \mu_{4} C_{ox} \cdot \left( {\frac{{W_{4} }}{{L_{4} }}} \right) \cdot \left( {V_{in - } - V_{t4} - \frac{{V_{ds3} }}{2}} \right) \cdot V_{ds3}$$
(5)
$$I_{ds7} = \mu_{7} C_{ox} \cdot \left( {\frac{{W_{7} }}{{L_{7} }}} \right) \cdot \left( {V_{out + } - V_{s7} - V_{t7} } \right)^{2}$$
(6)
$$I_{ds8} = \mu_{8} C_{ox} \cdot \left( {\frac{{W_{8} }}{{L_{8} }}} \right) \cdot \left( {V_{out - } - V_{s8} - V_{t8} } \right)^{2}$$
(7)

The threshold voltage Vth and µCox can be explicit in terms of a nominal part and a deviation part owing to mismatch between M7 and M8. For ease of calculation collective deviation between µ and C ox can be consider as only deviation in mobility µ [8, 9].

$$\upmu_{7} =\upmu_{\text{n}} + \Delta\upmu_{7}$$
(8)
$$\upmu_{8} =\upmu_{\text{n}} + \Delta\upmu_{8}$$
(9)
$${{V_{t7} }} = {{V_{tn} }} + \Delta {{V_{t7} }}$$
(10)
$${{V_{t8} }} = {{V_{tn} }} + \Delta {{V_{t8} }}$$
(11)

The mismatch between M2 and M3 random offset is:

$$\sigma_{{V_{OS\_M2M3} }}^{2} = \sigma_{{V_{t2} }}^{2} + \sigma_{{V_{t3} }}^{2} + \left( {V_{ref + } - V_{d5} - V_{tn} - \frac{{V_{ds2} }}{2}} \right)^{2} \cdot \sigma_{{\mu_{2} /\mu_{n} }}^{2} + \left( {V_{ref - } - V_{d5} - V_{tn} - \frac{{V_{ds3} }}{2}} \right)^{2} \cdot \sigma_{{\mu_{3} /\mu_{n} }}^{2}$$
(12)

The mismatch between M1 and M4 results in random offset is

$$\sigma_{{V_{OS\_M1M4} }}^{2} = \sigma_{{V_{t1} }}^{2} + \sigma_{{V_{t4} }}^{2} + \left( {V_{in + } - V_{d5} - V_{tn} - \frac{{V_{ds1} }}{2}} \right)^{2} \cdot \sigma_{{\mu_{1} /\mu_{n} }}^{2} + \left( {V_{in - } - V_{d5} - V_{tn} - \frac{{V_{ds4} }}{2}} \right)^{2} \cdot \sigma_{{\mu_{4} /\mu_{n} }}^{2}$$
(13)

The mismatch between M7 and M8 results in random offset is

$$\sigma_{{V_{OS\_M7M8} }}^{2} = \left( {\frac{{W_{8} }}{{W_{1} }}} \right)^{2} \frac{{\left( {V_{out - } - V_{s8} - V_{tn} } \right)^{2} }}{{V_{ds1}^{2} }}\sigma_{{V_{t8} }}^{2} + \left( {\frac{{W_{7} }}{{W_{1} }}} \right)^{2} \frac{{\left( {V_{out + } - V_{s7} - V_{tn} } \right)^{2} }}{{V_{ds1}^{2} }}\sigma_{{V_{t7} }}^{2} + \left( {\frac{{W_{8} }}{{W_{1} }}} \right)^{2} \frac{{\left( {V_{out - } - V_{s8} - V_{tn} } \right)^{4} }}{{4 \cdot V_{ds1}^{2} }}\sigma_{{\mu_{8} /\mu_{n} }}^{2} + \left( {\frac{{W_{7} }}{{W_{1} }}} \right)^{2} \frac{{\left( {V_{out + } - V_{s7} - V_{tn} } \right)^{4} }}{{4 \cdot V_{ds1}^{2} }}\sigma_{{\mu_{7} /\mu_{n} }}^{2}$$
(14)

The mismatch between M10 and M11 results in random offset is

$$\sigma_{{V_{OS\_M10M11} }}^{2} = \left( {\frac{{W_{10} }}{{W_{1} }}} \right)^{2} \frac{{\left( {V_{DD} - V_{out + } - V_{tn} } \right)^{2} }}{{4 \cdot V_{ds1}^{2} }}\sigma_{{V_{t10} }}^{2} + \left( {\frac{{W_{11} }}{{W_{1} }}} \right)^{2} \frac{{\left( {V_{DD} - V_{out - } - V_{tn} } \right)^{2} }}{{4 \cdot V_{ds1}^{2} }}\sigma_{{V_{t11} }}^{2} + \left( {\frac{{W_{10} }}{{W_{1} }}} \right)^{2} \frac{{\left( {V_{DD} - V_{out + } - V_{tn} } \right)^{4} }}{{16 \cdot V_{ds1}^{2} }}\sigma_{{\mu_{10} /\mu_{n} }}^{2} + \left( {\frac{{W_{11} }}{{W_{1} }}} \right)^{2} \frac{{\left( {V_{DD} - V_{out - } - V_{tn} } \right)^{4} }}{{16 \cdot V_{ds1}^{2} }}\sigma_{{\mu_{11} /\mu_{n} }}^{2}$$
(15)

In general static random offset voltage σ Vos in the proposed fully differential double tail dynamic comparator is as follows:

$$\sigma_{{V_{OS} }}^{2} = \left( {\sigma_{{V_{OS\_M1M4} }}^{2} + \sigma_{{V_{OS\_M2M3} }}^{2} + \sigma_{{V_{OS\_M7M8} }}^{2} + \sigma_{{V_{OS\_M10M11} }}^{2} } \right)^{{{\raise0.7ex\hbox{$1$} \!\mathord{\left/ {\vphantom {1 2}}\right.\kern-0pt} \!\lower0.7ex\hbox{$2$}}}}$$
(16)

The random mismatch in the V th and µ of transistor pair can be modelled as follows [8, 9]:

$$\sigma_{{V_{th} }}^{2} = \frac{{A_{{V_{th} }}^{2} }}{WL} + S_{{V_{T0} }}^{2} D^{2}$$
(17)
$$\sigma_{\mu }^{2} = \frac{{A_{\mu }^{2} }}{WL} + S_{\mu }^{2} D^{2}$$
(18)

where A Vth is process-dependent parameter, S VT0 is the variation of V T0 , W, L are the width and length of transistor, D is the distance between the transistor pair in layout. In 180 nm CMOS process, for nMOS is \(A_{Vth} \approx 5\;{\text{mV}}\;\upmu{\text{m}}, A_{\mu } \approx 1.04 \%\). For pMOS \(A_{Vth} \approx 5.49\;{\text{mV}}\;\upmu{\text{m}}, A_{\mu } \approx 0.99\%\).

For fully differential dynamic comparator static random offset voltage σVos is as follows:

$$\sigma_{{V_{OS} }}^{2} = \left( {\sigma_{{V_{OS\_M5M6} }}^{2} + \sigma_{{V_{OS\_M1M4} }}^{2} + \sigma_{{V_{OS\_M2M3} }}^{2} + \sigma_{{V_{OS\_M7M8} }}^{2} + \sigma_{{V_{OS\_M10M11} }}^{2} } \right)^{{{\raise0.7ex\hbox{$1$} \!\mathord{\left/ {\vphantom {1 2}}\right.\kern-0pt} \!\lower0.7ex\hbox{$2$}}}}$$
(19)

In literature various digital calibration techniques and offset cancellation circuits [10], such supplementary circuits to diminish offset voltages comes with area, power penalty and decline the overall speed. The challenging demand of area and power efficient, high speed applications such as A/D converters pushes to the investigation and usage of dynamic comparator to optimize area, power with enhance the speed. In this paper, new high-speed low offset power efficient comparator structure is introduced.

3.2.2 Delay

The delay is characterized as the time between the start of the amplification phase and the time where 50% of the latch final output is reached. Based on this definition, the inner latch delay can be calculated from derivations presented in [11, 12].

The delay of the comparator consists of two major parts, t 0 and t latch [11]. The charging of the load capacitance C Lout until the first n-channel transistor (M7/M8) turns on is represented as delay t 0 , subsequently the start of latch regeneration; thus t 0 is derived as

$$t_{0} = \frac{{V_{Thn} C_{Lout} }}{{I_{B1} }} \approx 2\frac{{V_{Thn} C_{Lout} }}{{I_{M7} }}$$
(20)

The drain current of the M7 is defined as (I B1  ≈ (I M5 /2)).

As soon as first nMOS transistor for instance M7 of the latch turns on, the analogous output (Out p ) will discharged to the ground, will lead pMOS transistor M11 to turn on, charging subsequent output (Out n ) to the supply voltage. For initial voltage difference at the output at time t 0 , ∆V 0 we have

$$\Delta V_{0} = \left| {V_{outp} \left( {t = t_{0} } \right) - V_{outn} \left( {t = t_{0} } \right)} \right| = V_{Thn} - \frac{{I_{B2} t_{0} }}{{C_{Lout} }} = V_{Thn} \left( {1 - \frac{{I_{B2} }}{{I_{B1} }}} \right)$$
(21)

Considering ∆Ilatch = |IB1 − IB2| = ∆Vfn/fp, (21) can be rewritten as

$$\Delta V_{0} = V_{Thn} \frac{{\Delta I_{latch} }}{{I_{B1} }} \approx 2V_{Thn} \frac{{\Delta I_{latch} }}{{I_{M5} }} = \frac{{2V_{Thn} }}{{I_{M5} }}\Delta V_{fn/fp}$$
(22)

It can concluded that at time t 0 , ∆Vf n /f p is the voltage difference at the first stage output is the parameter which affect the initial output difference voltage (∆V 0 ) and thus latch regeneration time.

The differential voltage (∆Vf n /f p ) at time t 0 can be derived as

$$\Delta V_{fn/fp} = \left| {V_{fn} \left( {t = t_{0} } \right) - V_{fp} \left( {t = t_{0} } \right)} \right|$$
$$\Delta V_{fn/fp} = t_{0} \cdot \frac{{I_{N1} - I_{N2} }}{{C_{L,fn\left( p \right)} }}$$
$$\Delta V_{fn/fp} = t_{0} \cdot \frac{{g_{m1,2,3,4} \Delta V_{in} }}{{C_{L,fn\left( p \right)} }}$$
(23)

In the above equation discharging current IN1 and IN2 of input transistors (M1–M4), dependent on the differential input voltage (i.e., ∆I N = g m1,2,3,4 ∆V in ).

Substituting (23) in (22), ∆V0 will be

$$\Delta V_{0} = 2V_{Thn} \frac{{g_{m1,2,3,4} }}{{I_{M5} }}\Delta V_{fn/fp}$$
$$\Delta V_{0} = \left( {\frac{{2V_{Thn} }}{{I_{M5} }}} \right)^{2} \cdot \frac{{C_{Lout} }}{{C_{L,fn\left( p \right)} }} \cdot g_{m1,2,3,4} \Delta V_{in}$$
(24)

Above equation illustrates that transconductance of input transistors, voltage difference at input (∆Vin), current of latch tail, and the ratio of CLout to CL,fn(p) have strong influence on ∆V0. The entire delay of the FDDTDC comparator is derived by substituting ∆V0 in latch regeneration time.

$$t_{delay} = t_{0} + t_{latch} = 2\frac{{V_{Thn} C_{Lout} }}{{I_{M5} }} + \frac{{C_{Lout} }}{{g_{m,eff} }} \cdot \ln \left( {\frac{{V_{DD} /2}}{{\Delta V_{0} }}} \right)$$
$$t_{delay} = 2\frac{{V_{Thn} C_{Lout} }}{{I_{M5} }} + \frac{{C_{Lout} }}{{g_{m,eff} }} \cdot \ln \left( {\frac{{V_{DD} \cdot I_{M5}^{2} \cdot C_{L,fn\left( p \right)} }}{{8V_{Thn}^{2} C_{Lout} g_{m1,2,3,4 } \Delta V_{in} }}} \right)$$
(25)

The differential output voltage (∆V0) is under enormous influence of the first stage output voltage difference and consequently on latch delay time t0. The first stage voltage difference should be increased to reduce the delay of the comparator.

The delay of the FDDC is defined as below [11]:

$$t_{delay} = 2 \frac{{C_{L} \left| {V_{thp} } \right|}}{{I_{tail} }} + \frac{{C_{L} }}{{g_{m,eff} }} \cdot \ln \left( {\frac{{V_{DD} }}{{4\left| {V_{thp} } \right|\Delta V_{in} }}\sqrt {\frac{{I_{tail} }}{{\beta_{1,2,3,4} }}} } \right)$$
(26)

3.2.3 Power analysis

The dynamic power consumption is used to estimate the power is as below [1, 2].

$$P = f_{CLK} C_{L} V_{DD}^{2} + V_{DD} \cdot I_{leakage}$$
(27)
$$P_{Dynamic} = \frac{1}{2} \cdot V_{DD}^{2} \cdot f \cdot C_{L}$$
(28)
$$P_{static} = V_{DD} \cdot I_{leak}$$
(29)

These formulas do not disclose the design parameters which count for power consumption still they are acceptable for the designers with acceptable estimation [13].

In dynamic comparator extensive equation of power is expressed as below [13].

$$P_{avg} = f_{clk} V_{DD} I_{sp5} \left( {\frac{1}{{8n\emptyset_{t}^{2} }}} \right) \cdot \tau_{latch} \left| {V_{Thp} } \right| \times \left[ {2k - n\left| {V_{Thp} } \right| + \left( {2k + n\left| {V_{Thp} } \right|} \right) \cdot exp\left( { - 2\frac{{t_{p} - t_{0} }}{{\tau_{latch} }}} \right) - 4K \cdot exp\left( { - \frac{{t_{p} - t_{0} }}{{\tau_{latch} }}} \right)} \right]$$
(30)

In the equation, k is equal to the V DD -|V Thp | and t p and t 0 are

$$t_{0} = \frac{{C_{Load} \left| {V_{Thp} } \right|}}{{{\raise0.7ex\hbox{${I_{tail} }$} \!\mathord{\left/ {\vphantom {{I_{tail} } 2}}\right.\kern-0pt} \!\lower0.7ex\hbox{$2$}}}}$$
(31)
$$I_{tail} = I_{M5} + I_{M6} for FDDC and I_{tail} = I_{M5} for FDDTDC$$
(32)
$$t_{p} = \frac{{C_{Load} }}{{G_{m,eff} }} \cdot \ln \left( {\frac{{V_{DD} }}{{\Delta V_{in} }}} \right)$$
(33)

Equation (30) indicates that the dominant design parameters are clock frequency, dimensions of input transistors, V DD and evaluation period (t p –t 0 ) which influence the most on the power expenditure of the comparator.

4 Design considerations and simulation results

4.1 Design considerations

  1. a.

    Differential Design or Double Tail Design: Numerous techniques to realize comparator such as open loop comparator, preamplifier based comparator, dynamic latch comparator and double tail comparator. None of the literature discussed on configuring the feature of differential pair with double tail.

  2. b.

    Design of Tail Transistor: It confines the current flow through the both of the output branches; it shows greater reliance on speed and offset voltage with different values of V CM .

  3. c.

    The isolated input and output latch stage: The comparator have a low and more stable offset voltage over a wide range of input common mode voltage and function at a reduced supply voltage.

  4. d.

    The previous code dependent errors or decision: The internal nodes should be initialized to V DD during the phase when the comparator is not making a decision.

4.2 Simulation results

To verify its operation and the consistency with the analytical derivations including delay, offset ICMR, frequency response and input –output noise spectral density. The circuit operates from a ± 0.9 V power supply. The simulation results and layouts are shown in Figs. 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 and 16, the delay of FDDTDC comparator is 0.37 ns, absolute offset voltage of 0.36 mV, ICMR is − 0.40 to 0.56 V with power consumption of 216.37 mW which is quite low in comparison FDDC and other reported structures. The FDDTDC can successfully resolve difference of 1 mV (10 bit resolution) at 1.3 GS/S. Considering that there is no extra circuitry require for offset cancellation, the new-flanged design is appropriate for applications demanding high resolution, high speed with optimum power. The transistor sizing is illustrated in Table 1.

Fig. 3
figure 3

Transient response of FDDC. a i/p square, b i/p sine

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Fig. 4
figure 4

FDDC. a offset voltage, b ICMR

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Fig. 5
figure 5

Transient response of FDDTDC. a i/p square, b i/p sine

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Fig. 6
figure 6

FDDTDC. a Offset voltage, b ICMR

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Fig. 7
figure 7

Input–Output Noise Spectral Density of a FDDC, b FDDTDC

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Fig. 8
figure 8

Frequency response of a FDDC, b FDDTDC

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Fig. 9
figure 9

a Common mode voltage v/s offset voltage, b common mode voltage v/s power dissipation

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Fig. 10
figure 10

a Delay v/s VDD, b delay v/s ∆Vin

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Fig. 11
figure 11

FDDTDC. a Delay v/s VDD, b delay v/s ∆Vin

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Fig. 12
figure 12

Monte Carlo simulation for each transistor pair input random offset voltage

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Fig. 13
figure 13

Histogram of Monte Carlo simulation for the offset voltage. a DDC, b FDDTDC

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Fig. 14
figure 14

Layout. a FDDC, b FDDTDC

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Fig. 15
figure 15

Corner analysis. a Delay, b offset voltage

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Fig. 16
figure 16

Corner analysis. a Power dissipation, b FOM

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Table 1 Transistor sizing for FDDC and FDDTDC
Full size table

Figure 7 illustrates the input–output noise spectral density for FDDC and FDDTDC. It is evident from the simulations that FDDTDC is more immune to noise in comparison to FDDC. Figure 8 depicts the frequency response of FDDC and FDDTDC.

Figure 9 illustrates the sensitivity of the offset voltage to common input mode voltage (V CM ) and power expenditure as a function of V CM . As V CM incases power dissipation is decreasing in both the comparator in identical manner. The Proposed fully differential double tail dynamic comparator has low offset voltage as compared to FDDC mentioned in the Fig. 3.

Figure 10(a) depicts effect of power supply on delay for differential input voltages. The delay is 370 ps (0.37 ns) at V DD  = 0.9 V for ΔV in  = 1 mV. As V DD changes from 0.9 to 1.5 V, the delay decreases from 370 to 132 ps. Furthermore, lower the delay for the higher value of the differential input voltage for a given V DD . In addition, For a given V DD , the higher the differential input voltage, the lesser the delay of comparator.

Figure 10(b) illustrates the effect of different input common-mode voltage V CM , on delay of the comparator for differential input voltage. The delay of the comparator is 370 ps (0.37 ns) for ΔV in  = 1 mV@V cm  = 200 mV. The delay reduces as differential input voltage enlarges for a given value of V CM .

Figure 11(a) shows the performance of the FDDTDC for delay versus variation in supply voltage for different input voltages. Figure 11(b) shows the effect of delay of the FDDTDC against differential input voltage under different values of V CM .

Figure 12, demonstrates the random offset voltage with the Monte Carlo Simulation for 1σ due to mismatch in different transistor pair of FDDC and FDDTDC as described conditions in Eqs. (16) and (19). From the simulation results and the Eq. (16) and (19) it affirms that FDDTDC has lower offset voltage than the FDDC. The transistor pair which causes the major offset and more venerable to mismatch is M5–M6.The \(\sigma_{{V_{OS\_M5M6} }}^{2}\) which represents the maximum mismatch for transistor pair M5 and M6, is not present according to Eq. (16) for the FDDTDC result into lower offset voltage.

Figure 13 shows Histogram of Monte Carlo Simulation for the Offset Voltage for DDC and FDDTDC. The Monte Carlo simulations for 500 iterations have been carried out for FDDC and FDDTDC. The FDDTDC have very offset voltage and improved ICMR. In case of FDDTDC the absolute value (average offset voltage) of the input offset voltage is 0.36 mV at one sigma, with the standard deviation from the simulation is 0.4 mV.

Figure 14 shows the layout of DDC and FDDTDC. All the transistors are positioned symmetrically to diminish mismatch and parasitics. Figures 15 and 16 shows the corner analysis (FF, FS, TT, SF, SS) for Delay, Offset Voltage, Power Dissipation and Figure of Merit for FDDC and FDDTDC.

Table 2 evaluates the performance of the FDDTDC with the FDDC. The FDDTDC provides low offset with high dynamic range and better sensitivity at low input for optimum power with considerable reduction in delay.

Table 2 Performance comparison
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Table 3 compares the FDDTDC with other reported comparator architectures. The FDDTDC has the very low offset and lowest FOM energy dissipated per conversation for optimum power with low offset voltage.

Table 3 Performance summary and comparison
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5 Conclusion

A novel design structure of Differential Double Tail Dynamic Comparator for high performance ADC is proposed with comprehensive offset and delay analysis. A new structure of the circuit are used to improve head room as well as the accuracy with which comparator can make decision. Simulation is carried out in 180 nm CMOS technology and result affirms that design metrics, delay, offset power and FoM are improved to a immensely. The simulation results illustrates that a comparator designed with the proposed techniques is 45% faster, and 30% more power efficient than reference comparator FDDC. The FDDTDC exhibits 91% low offset without any power hungry offset cancellation circuits as compared with conventional comparator. Parametric variations also carried out to verify the performance parameter of the proposed comparator and demonstrate stable performance over the process variations and for different transistor corners. The FDDTDC makes a superior trade-offs among speed, resolution, power, offset and area for applications which requires high speed, high resolutions such as ADCs, wearable electronics, and recently captured attention of IoT.