1 Introduction

With the increasing use of smart mobile devices such as wireless sensor devices, smart phones, smart watches, and smart glasses, various technologies have been developed to extend the battery life and reduce the chip area [1,2,3]. To achieve a longer battery life, the power management integrated circuit (PMIC), which generates multiple supply voltages, requires a high power efficiency and needs a wide voltage range for the battery. For compact power management systems, the PMIC should have fewer power transistors and external components, such as inductors and capacitors.

To meet the aforementioned requirements, single-inductor multiple-output (SIMO) and single-inductor dual-output (SIDO) converters have been researched [4,5,6,7,8,9,10,11,12,13]. In [4,5,6,7], the time-multiplexing and time-sharing methods regulated the multiple output voltages of the converter, but showed poor ripple and cross-regulation characteristics. In [8], the power-distributive control method with freewheeling switching achieved reasonable cross-regulation, but was still limited in lowering cross-regulation further because the cross-regulations of all outputs were interdependent. In [9], the hybrid converter using the current sensor and a low-dropout (LDO) regulator improved cross-regulation, but only when the input voltage was higher than the output voltage. The extended-PWM control method in [10] only employs the current sensor without using the LDO, thereby performing poor load- and cross-regulations. Furthermore, it occupies a large area due to many power switches needed to implement a buck and boost topology. The SIMO converter controlled by the freewheel charge pump in [11] uses the current sensor with the charge-pump, but the charge pump is only used for generating the additional output voltage, not for improving the regulation characteristic. Thus, it occupies a large area due to many power switches and requires a large output capacitor for the charge pump, and shows a poor regulation of the final output. Moreover, its power efficiency would be estimated to be low due to many switches and diodes, and charge pump operation at steady state.

In this paper, a SIDO converter is proposed to generate stable output voltages and achieve low load- and cross-regulations while minimizing the chip area; this is accomplished by using a fewer number of power switches with a small-sized freewheeling switch at a zero inductor current. The proposed converter using an error amplifier and comparators generates stable step-up and step-down output voltages, which are greater and less than the input voltage of the battery, respectively. The adaptive current sensor, which accurately detects the inductor current, and the LDO regulator with selectable charge pump is implemented in the proposed converter to achieve low load- and cross-regulations in both the buck–boost and boost modes. In Sect. 2, we describe the detailed architecture and operation principle of the proposed SIDO converter with an adaptive current sensor. In addition, the LDO regulator with a selectable charge pump is explained in detail. In Sect. 3, the experimental results are analyzed and compared with prior works. Finally, conclusions are given in Sect. 4.

2 The proposed SIDO converter

2.1 Architecture and operation principles

Figure 1 shows the block diagram of the proposed SIDO converter with four power switches (M FR , M N , M OP1, and M OP2), of which the main power switches (M FR and M N ) control the inductor current (I L ) to adjust the load currents (I OUT1 and I OUT2), and the output power switches (M OP1 and M OP2) deliver I OUT1 and I OUT2 to the dual outputs (V OUT1 and V OUT2), respectively. The proposed converter operates in the buck–boost or boost mode according to the mode selection signals (V B ) generated from the mode selector by comparing the input voltage (V IN ) with the target dual output voltages (V REF1 and V REF2).

Fig. 1
figure 1

Block diagram of the proposed SIDO converter

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An adaptive current sensor detects I L , then scales down and mirrors the peak I L . The sensor subsequently generates the sensing voltage (V SEN ), which is used in the power delivery control block to improve the regulation characteristics using the current-programmed control [12,13,14]. A 4-input folded cascade error amplifier compares V OUT1 and V OUT2 with V REF1 and V REF2, respectively, and generates an output error voltage (V ERR ) by accumulating all output errors. The comparators (CMP 1 and CMP 2) compare V OUT1 and V OUT2 with V REF1 and V REF2, and generate V CM1 and V CM2, which control V OP1 and V OP2, respectively, to prevent the dual outputs from the over-voltage. The power delivery control block then generates the non-overlapping gate driving signals (V FR , V N , V OP1, and V OP2) according to V SEN and V ERR in order to adjust the energizing and de-energizing periods of the inductor. V FR controls the free-wheeling switch (M FR ) at a zero inductor current to avoid a reversely flowing inductor current, whereas V N , V OP1, and V OP2 control the switches (M N , M OP1, and M OP2, respectively) to energize and de-energize I L . The energizing and de-energizing periods, along with V CM1 and V CM2, determine the amount of power to be delivered to the dual outputs so that V OUT1 and V OUT2 can be regulated to V REF1 and V REF2, respectively. In addition, the LDO regulator with a selectable charge pump having a high bandwidth is implemented to improve the regulation characteristics of the proposed converter, while rapidly regulating the dual outputs by activating the charge pump for a step-up voltage, which will be explained in detail in Sect. 2.3.

Figure 2(a–c) respectively show the input voltage of the proposed converter, the timing diagram of the operation of switches (M OP1, M OP2, and M N ), and I L in the buck–boost and boost modes.

Fig. 2
figure 2

a Input voltage of the proposed SIDO converter, b timing diagram of the switches (M OP1, M OP2, and M N ), and c inductor current (I L ) in the buck–boost and boost modes

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When V IN is between V REF1 and V REF2, the proposed SIDO converter operates in the buck–boost mode, in which the I L flows through paths (3), (1), and (2) in sequence, where the inductor is energized in paths (3) and (1), and de-energized in path (2). First, when M OP1 and M OP2 are turned off and M N is turned on, I L flows through path (3) and increases with a slope of V IN /L. Second, when M OP2 and M N are turned off, and M OP1 is turned on, I L flows through path (1) and increases with a slope of (V IN  − V OUT1)/L. Last, when M OP1 and M N are turned off, and M OP2 is turned on, I L flows through path (2) and decreases with a slope of (V IN  − V OUT2)/L.

When V IN is less than V REF1 and V REF2, the proposed SIDO converter operates in the boost mode, in which I L flows through paths (3), (1), and (2) in sequence, where the inductor is energized in path (3), and de-energized in paths (1) and (2). First, when M OP1 and M OP2 are turned off, and M N is turned on, I L flows through path (3) and increases with a slope of V IN /L. Second, when M OP2 and M N are turned off, and M OP1 is turned on, I L flows through path (1) and decreases with a slope of (V IN  − V OUT1)/L. Last, when M OP1 and M N are turned off, and M OP2 is turned on, I L flows through (2) and decreases with a slope of (V IN  − V OUT2)/L. Thus, in the buck–boost and boost modes, the energizing and de-energizing periods are adjusted differently by controlling the flowing path of I L using V N , V OP1, and V OP2, and thereby V OUT1 and V OUT2 are regulated to V REF1 and V REF2, respectively.

2.2 Proposed adaptive current sensor

Figure 3(a) shows the schematic of the proposed adaptive current sensor, which consists of a current_sensor1, a current_sensor2, and a summing circuit.

Fig. 3
figure 3

a Schematic of the proposed adaptive current sensor, and timing diagrams of I L and V SEN and b in buck–boost mode and c in boost mode

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In the current_sensor1, when I L flows through path (3), the peak I L is scaled down by 1/K, where K is the scaling ratio of the transistor size between M N and M SC1, and then flows through M SC1. The scaled current (I SC1) is mirrored to the currents of switches (M N1–M N5) (I SEN ) through OTA 1, where M N5 and OTA 1 are used to achieve a high current accuracy by minimizing the channel length modulation effect [15].

In the current_sensor2, when I L flows through path (1) [or path (2)], the peak I L is scaled down by 1/K, where K is the scaling ratio of the transistor size between M OP1 (or M OP2) and M SC2 and then flows through M SC2 and M K1. The scaled current (I SC2) is mirrored to the currents of switches (M K1–M K6) (I SEN ) through OTA 2, where M K1 and OTA 2 are also used to achieve a high current accuracy. To have an accurate scaling ratio, K, the source-drain voltage of M SC2 is designed to be equal to that of M OP1 and M OP2, assuming that M S1 and M S2 have a large size so that their resistance values can be ignored.

In the summing circuit, I SEN is converted to the summing voltage (V S ) via the sensing resistor (R SEN ). However, when M N and M OP1 (or M OP2) are simultaneously turned on, glitches such as switching noise and voltage drop at V S occur during the transition. Thus, to remove these glitches, a diode (D 1) and a capacitor (C 1) are used in the summing circuit, and M K7 periodically refreshes V SEN using a reset signal (V CLK ) synchronized at the operating clock of the converter.

Since I SC1 and I SC2 of the current sensor should be regulated within a minimum on-time of V N and V OP1 (or V OP2), respectively, the required bandwidth of the current sensor should be greater than 1/[minimum on-time of V N and V OP1 (or V OP2)]. The minimum on-time of V N and V OP1 (or V OP2) can be obtained by the product of the minimum on-duty of V N and V OP1 (or V OP2), and the operating period of the proposed converter, respectively [14]. In addition, the tolerable error of I SEN can be determined according to an acceptable variation in V OUT .

Figure 3(b, c) show the timing diagrams of I L and V SEN in the buck–boost and boost modes, respectively. In the buck–boost mode, the peak I L in paths (3) and (1) is sequentially sensed by enabling both current_sensor1 and current_sensor2, and I SEN is then converted to V SEN through the summing circuit. In the boost mode, the peak I L in path (3) is sensed by enabling current_sensor1 and disabling current sensor2, and I SEN is converted to V SEN . Therefore, the proposed adaptive current sensor accurately detects the peak I L and generates V SEN , which is used in the power delivery control block to improve the regulation characteristics.

2.3 LDO regulator with selectable charge pump

When the load current of the proposed SIDO converter abruptly changes, the LDO regulator is used to achieve a fast transient response by compensating for the insufficient inductor current of the switching converter because the bandwidth of the LDO regulator is greater than that of the switching converter [16,17,18,19,20]. The selectable charge pump, which is used to generate two step-up voltages of V CP1 and V CP2 according to the input and output voltages, always operates both in the steady state and in the load transient, whereas the LDO regulator only operates in the load transient. The LDO regulator with selectable charge pump is designed with smaller-sized power transistors compared with the switching converter [21, 22], thereby achieving low load- and cross-regulations without degrading power efficiency.

Figure 4 shows the structure of the LDO regulator with a selectable charge pump. The selectable charge pump consists of a pumping ratio control and driving block, and pumping blocks for V CP1 and V CP2. Each pumping block has three stages, which are used to sufficiently pump up V CP1 and V CP2 to regulate V OUT1 and V OUT2, respectively. The LDO regulator, which consists of two error amplifiers (OTA 3 and OTA 4), pass transistors (M P1 and M P2), and a transient detection block, has a dropout voltage (V LDO ). In the selectable charge pump, a pumping ratio control and driving block determines the pumping ratios according to V IN , V REF1, and V REF2 by enabling or disabling each stage using the driving switches and capacitors. When a stage is enabled, its output voltage increases by V IN , whereas when a stage is disabled, its output voltage remains at its input voltage.

Fig. 4
figure 4

Structure of the LDO regulator with a selectable charge pump

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When V IN is greater than V REF1 + V LDO , considering the dropout voltage of the LDO regulator, the proposed SIDO converter operates in the buck–boost mode. In this case, the selectable charge pump enables only one stage for V CP2 and disables the rest of the stages for V CP1 and V CP2, and so V CP1 and V CP2 become V IN and 2 × V IN , resulting in being greater than V REF1 + V LDO and V REF2 + V LDO , respectively. When V IN is less than V REF1 + V LDO , the proposed SIDO converter operates in the boost mode. In this case, the selectable charge pump enables one, two, or three stages among stages in the pumping blocks according to V IN , V REF1, and V REF2, thereby generating 2×, 3×, or 4 × V IN , respectively, for both V CP1 and V CP2. Thus, V CP1 and V CP2 can be sufficiently pumped up to be greater than V REF1 + V LDO and V REF2 + V LDO , respectively. The sizes of the pumping capacitors for V CP1 and V CP2 (C Ln and C Hn ) are determined given that the supplied charge to the charge pump should be larger than or equal to the released charge from the charge pump. Furthermore, the sizes of the load capacitors for V CP1 and V CP2 (C CP1 and C CP2) are determined by considering the output ripple voltage [23].

In the LDO regulator, the transient detection block detects the load transition at V OUT1 and V OUT2, and enables OTA 3 and OTA 4 to convert V CP1 and V CP2 to V REF1 and V REF2 through M P1 and M P2, respectively, with a voltage drop of V LDO . Therefore, V OUT1 and V OUT2 can be rapidly regulated to V REF1 and V REF2, respectively.

3 Experimental results

Figure 5(a) shows the chip microphotography of the proposed SIDO converter, which is fabricated using a 0.18-µm CMOS technology and occupies an area of 1142 mm2 (1568 μm × 728 μm). Figure 5(b) shows the photograph of the printed circuit board (PCB) with a module size of 18 mm × 16 mm, including the proposed chip, an inductor, and capacitors. To verify the performance of the proposed converter, an input voltage ranging between 3.2 and 1.0 V is used and two output voltages are designed to be 1.8 and 3.3 V with a maximum output current of 200 mA at an operating frequency of 500 kHz.

Fig. 5
figure 5

a Chip microphotograph of the proposed SIDO converter and b photograph of the PCB

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Figure 6 shows the measured input and output voltages, and I L at V OUT1 = 1.8 V, V OUT2 = 3.3 V, I OUT1 = 100 mA, and I OUT2 = 100 mA: (a) when V IN  = 3.1 V in the buck–boost mode and (b) when V IN  = 1.0 V in the boost mode. Figure 7 shows that the dual output voltages can be regulated in an extended range of between 1.0 and 4.5 V.

Fig. 6
figure 6

Measured input/output voltages and I L at V OUT1 = 1.8 V, V OUT2 = 3.3 V, I OUT1 = 100 mA, and I OUT2 = 100 mA a when V IN  = 3.1 V in the buck–boost mode and b when V IN  = 1.0 V in the boost mode

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Fig. 7
figure 7

Measured input/output voltages and I L at V OUT1 = 1.0 V, V OUT2 = 4.5 V, I OUT1 = 200 mA, and I OUT2 = 200 mA when V IN  = 3.0 V in the buck–boost mode

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Figure 8 shows the measured load-regulation of V OUT2 and cross-regulation of V OUT1 when I OUT2 changes from 10 to 50 mA and vice versa. Without the LDO regulator and selectable charge pump, the load- and cross-regulations are 0.375 and 0.264 mV/mA, respectively, as shown in Fig. 8(a). With the LDO regulator and selectable charge pump, the load- and cross-regulations are 0.120 and 0.088 mV/mA, respectively, as shown in Fig. 8(b), showing that the voltage fluctuation is not noticeable. When V IN changes from 2.0 to 3.0 V and from 3.0 to 2.0 V as shown in Fig. 9(a, b), respectively, V OUT2 varies by less than 63 mV, and thereby the proposed converter has a line regulation of less than 0.063 mV/mV. On the other hand, V OUT1 varies unnoticeably. These measurement results demonstrate that the output voltages of the proposed SIDO converter are well regulated using the LDO regulator with selectable charge pump regardless of the changes in the load current and input voltage.

Fig. 8
figure 8

Measured load-regulation of V OUT2 and cross-regulation of V OUT1 when I OUT2 is changed from 10 to 50 mA and vice versa a without and b with the LDO regulator and selectable charge pump

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Fig. 9
figure 9

Measured line-regulation of V OUT1 and V OUT2 when V IN is changed a from 2.0 to 3.0 V and b from 3.0 to 2.0 V

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Figure 10(a, b) show the power efficiencies according to the load currents at V OUT1 = 1.8 V and V OUT2 = 3.3 V, where the maximum efficiencies are 89.2% in the buck–boost mode at the I OUT1 and I OUT2 of 100 mA, and 88.3% in the boost mode at a I OUT1 of 100 mA and a I OUT2 of 0 mA, respectively. Although the proposed converter achieves small-area and high current density, the maximum power efficiency was limited to 89.2% mainly due to the conduction and switching losses of power switches, having 5.490 and 4.476%, respectively.

Fig. 10
figure 10

Power efficiency according to the load currents at V OUT1 = 1.8 V and V OUT2 = 3.3 V a when V IN  = 3.1 V in buck–boost mode and b when V IN  = 1.0 V in boost mode

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Table 1 shows the performance summary of the proposed converter compared with prior works. The proposed SIDO converter achieves the low load- and cross-regulations of 0.120 and 0.088 mV/mA, respectively. Moreover, it has the highest current density of 350.00 mA/mm2, which is represented as the ratio of the maximum load current to the chip area and the smallest value of the product of LC, compared with prior works.

Table 1 Comparison and performance summary
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4 Conclusions

In this paper, a SIDO converter that operates in the buck–boost and boost modes is proposed to generate stable output voltages and achieve low load- and cross-regulations. The proposed adaptive current sensor detecting the peak inductor current without glitches and an LDO regulator with a selectable charge pump are adopted to achieve low load- and cross-regulations. The proposed SIDO converter was fabricated using a 0.18-µm CMOS process technology and occupies an area of 1568 μm × 728 μm. The regulated dual output voltages are 1.8 and 3.3 V and can be extended to be between 1.0 and 4.5 V. The measured load- and cross-regulations of the proposed SIDO converter are reduced to 0.120 and 0.088 mV/mA when the load current changes from 10 to 50 mA. In addition, the proposed SIDO converter achieves a high current density and the smallest value for LC product compared with prior works. Therefore, the proposed SIDO converter is suitable for mobile devices, which require low load- and cross-regulations, a high current density, and a small form factor.