A new current mode implementation of a balanced-output-signal generator

Abstract

This paper presents a new current mode implementation of a balanced-output-signal generator that utilizes an operational floating current conveyor (OFCC) as a basic building block. The OFCC, as a current-mode device, shows flexible properties with respect to other current or voltage-mode circuits. The advantages of the proposed current mode balanced-output-signal generator (CMBG) are threefold. Firstly, it offers an accurate phase and amplitude performance over a wide bandwidth without requiring matched resistors. Secondly, it has a differential input and it can provide either current or voltage outputs. Finally, the proposed CMBG circuit offers a significant improvement in accuracy compared to other CMBGs based on the current conveyor. The proposed CMBG has been analyzed, simulated and experimentally tested. The experimental results verify that the proposed CMBG outperforms existing CMBGs in terms of the number of basic building blocks used and accuracy.

1 Introduction

Generating a balanced-output-signal from a sinusoidal input over a large frequency range is used in many application areas, such as synchronous detection [1] and lock-in-based systems [2]. Also, signals which are both amplitude matched and phase balanced are very important in the transmission of analog signals over long lines in order to reject unwanted common mode signals [3]. Nowadays, lab-on-a-chip which requires the integration of the actuation and sensing parts, as well as the read-out circuitry in a single chip, needs also a wide bandwidth balanced-output-signal generator to generate two 180° out-of-phase signals from a sinusoidal input [4].

The voltage-mode balanced-output-signal generators (VMBG) based on an operational amplifier, as shown in Figs. 1 and 2, require the matching of amplifier poles [5, 6]. Also, due to the fixed gain bandwidth product of the operational amplifier, the system cannot simultaneously provide both a minimum phase-difference error between the outputs and minimum amplitude difference without compromising the bandwidth performance of the system. Additionally, VMBGs require precise resistor matching to achieve high common-mode rejection ratio (CMRR) [5, 6].

Fig. 1

Circuit proposed in Ref. [5] for 180^o out-of-phase signals

Fig. 2

Circuit proposed in Ref. [6] for 180^o out-of-phase signals

A current-mode balanced output signal generator (CMBG) is used as shown in Fig. 3 [7]. It uses two op-amps working in conjunction with two second-generation current conveyors (CCII). Unlike the circuits in Ref. [5] and [6], this circuit does not require precise matching of amplifier poles. However, when this circuit, see Fig. 3, works in a single ended input mode, i.e., v_in1 is active and v_in2 is grounded, the phase difference and the amplitude between v_o1 and v_o2 are: [7]

$$\Delta \phi = \tan^{ - 1} (\omega C_{1} R_{G} ) + 180^{\text{o}}$$

(1)

$$|\Delta V|_{dB} = 10\log (1 + \omega^{2} C_{1}^{2} R_{G}^{2} )$$

(2)

Fig. 3

Two CCII+ used in conjunction with two Op-amps CMBG, Ref. [7]

Equation (1) shows that there is a phase error [tan⁻¹(ωC ₁ R _G )] which increases with both the frequency and R_G. Thus in order to minimize the phase error, R_G should be as small as possible. Equation (2) also indicates an increase of the output-signal amplitude difference (error) with frequency and with R_G. Additionally, this approach suffers from higher power consumption and a more complicated circuit topology when compared with the topologies shown in Figs. 1 and 2. Recently, a CMBG based on four CCIIs is presented [8] and is shown in Fig. 4, where the two Op-amps (OP1 and OP2) in Fig. 3, are replaced by two CCIIs. Figure 4 is taking into consideration the equivalent input resistance at X terminal (R_X) of the CCIIs. This circuit used only CCII as a building block. However, this circuit has the same issue associated with the circuit shown in Fig. 3, i.e., when works in a single ended input mode, v_in1 is active and v_in2 is grounded, the phase difference and the amplitude between v_o1 and v_o2 are exactly the same ones given in Eqs. (1) and (2). Thus, it suffers from increasing the output-signal amplitude difference (error) with frequency and with R_G.

Fig. 4

Four CCII+ based CMBG, Ref. [8]

In this paper, the new proposed CMBG circuit has the following advantages: (1) it is simple and has symmetric circuit topology, (2) it has much improved amplitude and phase difference compared with the other voltage or current-mode balanced output signal generators, and (3) it has a differential input and it can provide either a balanced output current or voltage. The proposed CMBG circuit is based on the Operational Floating Current Conveyor (OFCC), which exhibits flexible characteristics with respect to other current-mode or voltage-mode devices [9–13]. The remainder of this paper is organized as follows:

Section 2 introduces and reviews the basic concept of the OFCC and its characteristics. Also, a simple model of the OFCC, as well as, the effect of feedback on the OFCCs performance are presented and discussed. A detailed analysis of the proposed CMBG is presented in Sect. 3. Section 4 presents the simulation and experimental results. Section 5 discusses the performance of the proposed CMBG and compares it to the performance of currently used CMBGs. Section 6 concludes the paper and discusses the merits of the proposed CMBG based on the experimental findings.

2 The operational floating current conveyor (OFCC)

The OFCC is a five-port network, comprised of two inputs and three output ports, as shown in Fig. 5 [9–13]. In this diagram, the port labeled X represents a low impedance current input, port Y is a high impedance input voltage, W is a low impedance output voltage, and Z+, and Z− are the high impedance current outputs with opposite polarities. The OFCC operates where the input current at port X is multiplied by the open loop transimpedance gain Z_t to produce an output voltage at port W. The input voltage at port Y appears at port X and thus a voltage tracking property exists at the input port. Output current flowing at port W is conveyed in phase to port Z+ and out of phase with that flowing into port Z−, so in this case a current tracking action exists at the output port. Thus, the transmission properties of the ideal OFCC can be conveniently described as:

$$\left[ {\begin{array}{l} {{\text{i}}_{{\text{y}}} } \\ {{\text{v}}_{{\text{x}}} } \\ {{\text{v}}_{{\text{w}}} } \\ {{\text{i}}_{{{\text{z+}}}} } \\ {{\text{i}}_{{{\text{z}-}}} } \\ \end{array} } \right] = \left[ {\begin{array}{lllll} 0 & 0 & 0 & 0 & 0 \\ 1 & 0 & 0 & 0 & 0 \\ 0 & {{\text{Z}}_{\rm t} } & 0 & 0 & 0 \\ 0 & 0 & 1 & 0 & 0 \\ 0 & 0 & { - 1} & 0 & 0 \\ \end{array} } \right]\left[ {\begin{array}{l} {{\text{v}}_{{\text{y}}} } \\ {{\text{i}}_{{\text{x}}} } \\ {{\text{i}}_{{\text{W}}} } \\ {{\text{v}}_{{{\text{z+}}}} } \\ {{\text{v}}_{{{\text{z}-}}} } \\ \end{array} } \right]$$

(3)

where i_y and v_y are the inward current and voltage at the Y port, respectively, as shown in Fig. 5. i_x and v_x are the input current and voltage at the X port, respectively. i_w and v_w are the output current and voltage at W port, respectively. i_z+ and v_z+ are the output current and voltage at Z + port, respectively. Similarly, i_z- and v_z- are the output current and voltage at the Z− port, respectively. Z_t represents the impedance between X and W ports.

Fig. 5

Block diagram representation of the operational floating current conveyor

The OFCC can be implemented by applying the principle of supply current sensing to a current feedback (CFB) op-amp [14] such as illustrated in Fig. 6. The current mirrors CM1 and CM2 establish the output current at port Z+. Also, CM1 and CM2 and their cross-coupling with the current mirrors CM3 and CM4 through the current steering transistors CS1 and CS2 generate a complementary output current at port Z−. The OFCC is basically designed to be used in a closed loop configuration, with current being fed back from port W to port X [9].

Fig. 6

Circuit scheme of the OFCC

2.1 A simple model

A simple model of the OFCC based on the circuit topology shown in Fig. 6 is illustrated in Fig. 7. In this figure, R_x and R_y are the resistances of the CFB op-amp at negative (−) and positive (+) ports, respectively. C_x and C_y are the input capacitances of CFB op-amp (−) and (+) ports, respectively. R_T and C_T are the small signal resistance and internal compensation capacitance of the CFB op-amp. R_Z+ and R_Z− are the small signal output resistances of the respective current mirrors at node Z+ and Z−, respectively at the d.c. operating point. C_Z+ and C_Z− represent the output capacitances of the respective current mirrors at nodes Z+ and Z−, respectively.

Fig. 7

The OFCC’s model, Ref. [10]

2.2 OFCC with feedback

The OFCC, unlike the CCII, is designed with a feedback resistor between W and X, i.e. negative feedback between W and X. This feedback resistor allows the OFCC to operate at a positive or negative current-conveyor while simultaneously reducing the input resistance at X port [11]. Also, the negative feedback improves the dc stability as well as the transfer function accuracy [7, 9, 10].

To understand why the input resistance at the X terminal is reduced by negative feedback, consider the OFCC with feedback resistor R_W, as shown in Fig. 8. The capacitive reactance to ground due to C_x is quite high and can therefore be ignored in the frequency range of interest. In this case, the input current i_in is defined as:

$${{\rm i}_{\rm in}} = \, {{\rm i}_{1}} + {{\rm i}_{\rm e}}$$

(4)

and,

$${\text{i}}_{ 1}= \frac{{{\text{v}}_{\text{in}} {\text{ - v}}_{\text{w}} }}{{{\text{R}}_{\text{W}} }}$$

(5)

where v_in is the input voltage at port X, v_w is the output voltage at port W, R_w is the feedback resistance, i₁ is the feedback current, and i._e. is the error current.Using Eq. (3), the output signal voltage v_w is given as,

$${{\rm v}_{\rm w}} = - {{\rm i}_{\rm e}} \rm {{\rm Z}_{\rm t}}$$

(6)

where Z_t = R_T//(1/jωC_T). For low frequencies (ω < <1/R_TC_T) the reactance due to C_T is very high and can be ignored. Thus Z_t ≈ R_T and

$${{\rm v}_{\rm w}} = - {{\rm i}_{\rm e}} {{\rm R}_{\rm T}}$$

(7)

Now since the Y port is connected to ground, v₂ = 0, and therefore the error current is defined as:

$${\rm i}_{\text{e}} = \frac{{{\rm v}_{\text{in}} - 0}}{{{\rm R}_{{\rm X}} }} .$$

(8)

By substituting Eqs. (5), (7), and (8) in (4), i_in can be expressed as

$${\text{i}}_{\text{in}} = \frac{{{\text{v}}_{\text{in}} ({\text{R}}_{\text{X}} + {\text{R}}_{\text{T}} + {\text{R}}_{\text{W}} )}}{{{\text{R}}_{\text{X}} {\text{R}}_{\text{W}} }}$$

(9)

The low frequency input resistance at X port can therefore be expressed as,

$${\text{R}}_{\text{in}} = \frac{{{\text{v}}_{\text{in}} }}{{{\text{i}}_{\text{in}} }} = \frac{{{\text{R}}_{\text{X}} {\text{R}}_{\text{W}} }}{{{\text{R}}_{\text{X}} + {\text{R}}_{\text{T}} + {\text{R}}_{\text{W}} }} .$$

(10)

Fig. 8

Circuit to measure OFCC’s R_X, Ref. [10]

With typical resistor values of: R_x = 50 Ω, R_w = 1 KΩ, and R_T = 200 MΩ. Equation (10) yields R_in = 0.0025 Ω. Therefore, the input resistance at X is greatly reduced, thus minimizing the voltage tracking error between X and Y, and therefore can be neglected at low frequencies.

3 The proposed CMBG

The proposed CMBG consists of two operational floating current conveyors (OFCC), two feedback resistors (R_W1 and R_W2), a gain determined resistor (R_G) and a ground loads (R_L1 and R_L2), as shown in Fig. 9. The two OFCC are arranged such that the output current into the load resistor R_L1 is equal and 180^o out of phase of the current into R_L2. C₁ and C₂ are the parasitic capacitances at the inverting input (X) of OFCC1 and OFCC2, respectively, while C_Z1, and C_Z2 are that parasitic capacitances at the outputs.

Fig. 9

The Proposed CMBG circuit

Taking into consideration both the voltage and current tracking errors of the OFCC, the current tracking error between ports X, Z + and Z− is:

$$\upalpha = 1 - \upvarepsilon_{+}$$

(11)

and

$$\upgamma = \, 1 - \upvarepsilon_{ - }$$

(12)

where: $\varepsilon_{ + }$ and ε_- denotes the finite current tracking error at the high impedance output Z+ and Z−, respectively. Thus, the port currents may then be expressed as ${\text{i}}_{{{\text{z}} + }} = \alpha {\text{i}}_{\text{x}}$ and ${\text{i}}_{{{\text{z}} - }} = \gamma {\text{i}}_{\text{x}}$.The voltage tracking error between ports X and Y is defined as:

$$\upbeta = 1 - \upvarepsilon_{\rm V}$$

(13)

where εV denotes the finite voltage tracking error at the low impedance X from the high input impedance node Y.The voltage at nodes vA and vB, as shown in Fig. 9, can be expressed as:

$${{v}_{A}} = {\beta_{1}} {v_{{in1}}} {\text{ and }}{v_{B}} = {\beta_{2}} {v_{{in2}}}$$

(14)

where β ₁ and β ₂ are the voltage tracking error of OFCC (1) and OFCC (2), respectively. Because of the effect of the OFCC, the voltage transfer error is zero, i.e., β ₁ = β ₂ = 1 [9–12]Thus,

$${\text{v}}_{\text{A}} = {\text{v}}_{\text{{\rm {in1}}}} \;{\text{and}}\;{\text{v}}_{\text{B}} = {\text{v}}_{\text{{\rm {in2}}}}$$

(15)

The current i _x can be expressed as:

$$i_{X} = \,i_{1} + i_{3}$$

(16)

$$i_{1} = \,v_{\rm {in1}} (sC_{1} )$$

(17)

$$i_{3} \, = \frac{{\,v_{{\rm {in1}}} - v_{{\rm {in2}}} }}{{R_{G} }}$$

(18)

From (17) and (18) into (16),

$$i_{x} = \,v_{\rm {in1}} \,\left( {sC_{1} + \frac{1}{{R_{G} }}} \right) - v_{\rm {in2}} \left( {\frac{1}{{R_{G} }}} \right)$$

(19)

3.1 Differential input mode

For the differential Input mode, $v_{{\rm {in1}}} = \, - v_{{\rm {in2}}} = \frac{{v_{d} }}{2}$. The resulting current i _x and i ₄ can be calculated as:

$$i_{x} = \,\frac{{v_{d} }}{{R_{G} }}\left(\frac{{sC_{1} R_{G} }}{2} + 1\right)$$

(20)

Similarly,

$$i_{4} = \,\frac{{v_{d} }}{{R_{G} }}\left(\frac{{sC_{2} R_{G} }}{2} + 1\right)$$

(21)

The output currents i ₅ and i ₆ are calculated as follows:

$$i_{5} = \, \alpha_{1} i_{x} = \frac{{\alpha_{1} v_{d} }}{{R_{G} }}\left(\frac{{sC_{1} R_{G} }}{2} + 1\right)$$

(22)

$$i_{6} = \, \gamma_{1} i_{x} = \frac{{\gamma_{1} V_{d} }}{{R_{G} }}\left(\frac{{sC_{1} R_{G} }}{2} + 1\right)$$

(23)

The output voltages v _o1, and v _o2 are:

$$v_{\text{o1}} = \, ({\text{i}}_{5} )\,\left( {{\text{R}}_{\text{L1}} //\frac{1}{{{\text{sC}}_{\text{Z1}} }}} \right)$$

(24)

$$v_{o2} = { - }(i_{6} )\,\left( {R_{L2} //\frac{1}{{sC_{Z2} }}} \right)$$

(25)

where C _Z1 and C _Z2 are the output node capacitance at Z + , Z− terminals which are in parallel with R_L1 and R_L2.

Using i₅ and i₆ from Eqs. (22) and (23), respectively, v _o1 and v _o2 can now be computed,

$$\frac{{v_{o1} }}{{v_{d} }} = \frac{{\alpha_{1} R_{L1} (1 + sC_{1} R_{G} /2)}}{{R_{G} (1 + \,sC_{Z1} R_{L1} )}}$$

(26)

$$\frac{{v_{o2} }}{{v_{d} }} = - \frac{{\gamma_{1} R_{L2} (1 + sC_{2} R_{G} /2)}}{{R_{G} (1 + \,sC_{Z2} R_{L2} )}}$$

(27)

The phase differences Φ ₁, and Φ ₂ of v _o1 and v _o2 are given by:

$$\phi_{1} = \tan^{ - 1} \left(\frac{{\omega C_{1} R_{G} }}{2}\right) - \tan^{ - 1} (\omega C_{Z1} R_{L1} )$$

(28)

$$\phi_{2} = \tan^{ - 1} \left(\frac{{\omega C_{1} R_{G} }}{2}\right) - \tan^{ - 1} (\omega C_{Z2} R_{L2} ) - 180^{o}$$

(29)

The output phase difference ΔΦ ₁₂ is given by:

$$\Delta \phi_{12} = \phi_{1} - \phi_{2} = \tan^{ - 1} (\omega C_{Z2} R_{L2} ) - \tan^{ - 1} (\omega C_{Z1} R_{L1} ) + 180^{\text{o}}$$

(30)

The output signal amplitude difference Δv₁₂ can be calculated from (26) and (27)

$$\Delta v_{12} = \frac{{v_{o1} }}{{v_{o2} }} = \frac{{\alpha_{1} {\text{R}}_{{{\text{L}}1}} }}{{\gamma_{1} {\text{R}}_{{{\text{L}}2}} }}.\frac{{(1 + \,{\text{sC}}_{Z2} {\text{R}}_{{{\text{L}}2}} )}}{{(1 + \,{\text{sC}}_{Z1} {\text{R}}_{{{\text{L}}1}} )}}$$

(31)

For ideal OFCCs, α₁ = γ₁ = 1, thus the output voltage is:

$$\Delta v_{12} = \frac{{{\text{R}}_{{{\text{L}}1}} }}{{{\text{R}}_{{{\text{L}}2}} }}.\frac{{(1 + \,{\text{sC}}_{{{\text{Z}}2}} {\text{R}}_{{{\text{L}}2}} )}}{{(1 + \,{\text{sC}}_{{{\text{Z}}1}} {\text{R}}_{{{\text{L}}1}} )}}$$

(32)

Assuming matched resistors and capacitors, i.e., R _L1 = R _L2 and C_z1 = C_z2. ∆φ ₁₂  = 180° and ∆v ₁₂  = 0 dB, i.e., the phase and amplitude errors disappear. v _o1 and v _o2 therefore become balanced amplitude-matched signals. The mismatching impacts of R _L1, R _L2 and C_z1 and C_z2 will be discussed and investigated in details in part 4.

3.2 Single ended input mode

For a single ended input, v _in1 = v ₁ and v _in2 = 0, then i _x and i ₄ can be expressed as:

$$i_{x} = \,v_{1} \,\left( {sC_{1} + \frac{1}{{R_{G} }}} \right)$$

(33)

and

$$i_{4} = \,v_{1} \,\left( {\frac{1}{{R_{G} }}} \right)$$

(34)

Using a routine circuit analysis we can prove that:

$$\frac{{v_{o1} }}{{v_{1} }} = \frac{{\alpha_{1} R_{L1} (1 + sC_{1} R_{G} )}}{{R_{G} (1 + \,sC_{Z1} R_{L1} )}}$$

(35)

$$\frac{{v_{o2} }}{{v_{1} }} = \frac{{ - \gamma_{1} R_{L2} (1 + sC_{1} R_{G} )}}{{R_{G} (1 + \,sC_{Z2} R_{L2} )}}$$

(36)

The phase differences Φ ₁ and Φ ₂ of v _o1 and v _o2 are given by:

$$\phi_{1} = \tan^{ - 1} (\omega C_{1} R_{G} ) - \tan^{ - 1} (\omega C_{Z1} R_{L1} )$$

(37)

$$\phi_{2} = \tan^{ - 1} (\omega C_{1} R_{G} ) - \tan^{ - 1} (\omega C_{Z2} R_{L2} ) - 180^{\text{o}}$$

(38)

The output phase differences ΔΦ ₁₂ is given by:

$$\Delta \phi_{12} = \phi_{1} - \phi_{2} = \tan^{ - 1} (\omega C_{Z2} R_{L2} ) - \tan^{ - 1} (\omega C_{Z1} R_{L1} ) + 180^{\text{o}}$$

(39)

The output signal amplitude difference Δv ₁₂ is:

$$\Delta v_{12} = \frac{{\alpha_{1} {\text{R}}_{{{\text{L}}1}} }}{{\gamma_{1} {\text{R}}_{{{\text{L}}2}} }}.\frac{{(1 + \,{\text{sC}}_{{{\text{Z}}2}} {\text{R}}_{{{\text{L}}2}} )}}{{(1 + \,{\text{sC}}_{{{\text{Z}}1}} {\text{R}}_{{{\text{L}}1}} )}}$$

(40)

For ideal OFCCs, α₁ = γ₁ = 1, thus the output voltage is:

$$\Delta v_{12} = \frac{{{\text{R}}_{{{\text{L}}1}} }}{{{\text{R}}_{{{\text{L}}2}} }}.\frac{{(1 + \,{\text{sC}}_{{{\text{Z}}2}} {\text{R}}_{{{\text{L}}2}} )}}{{(1 + \,{\text{sC}}_{{{\text{Z}}1}} {\text{R}}_{{{\text{L}}1}} )}}$$

(41)

From (40) and (41), and assuming matched resistors and capacitors (i.e., R _L1 = R _L2 and C_z1 = C_z2). Then ∆φ ₁₂  = 180° and ∆v ₁₂ = 0 dB, i.e., the phase and amplitude errors disappear. v _o1 and v _o2 therefore become balanced amplitude-matched signals. The mismatching impacts of R _L1, R _L2 and C_z1 and C_z2 will be discussed and investigated in details in part 4.

4 Impact of mismatch variations on the proposed CMBG performance

In this section, the ideal assumption made in Eqs. (31) and (41) where R_L1 = R_L2 and C_z1 = C_z2, is investigated. It is assumed that resistances R_L1 and R_L2 have a mismatch ΔR. Capacitances C_z1 and C_z2 are assumed to have a mismatch ΔC. Ten thousands Monte Carlo simulation points are calculated for different values of ΔR/R and also for different values of ΔC/C. Following that, the resulting magnitude variations around the nominal value of 1.0 and the phase variations around the nominal value of 180^o is determined.

4.1 Resistor mismatch

The resistance mismatch variation (i.e., ΔR/R) is assumed to be 2, 5, 10, and 20 %. Monte Carlo simulations are performed to get the corresponding mean and standard deviation of the magnitude and the phase. Figure 10 shows the relative variations of the magnitude and phase (i.e., the standard deviation divided by the nominal mean value) resulting from different resistance mismatch values (i.e., 2, 5, 10, and 20 %) when the operating frequency is 1 MHz.

Fig. 10

The relative variations of the magnitude and phase for different resistance mismatch variations

From Fig. 10, it is obvious that the relative phase variations are higher than the relative magnitude variations, especially at higher resistance mismatch values. In addition, as the resistance mismatch variations increase, the relative magnitude variations increase at a lower rate than that of the relative phase variations.

Also, the relative magnitude variations and the relative phase variations are calculated for different operating frequency values (1, 5 and 10 MHz) when the resistance mismatch variations are fixed at 20 % and are shown in Fig. 11. In Fig. 11, it can be noted that the effect of the operating frequency on the relative magnitude and phase variations is not significant.

Fig. 11

The relative variations of the magnitude and phase at different frequencies (the resistance mismatch variations are fixed at 20 %)

4.2 Capacitor mismatch

Similarly, the relative variations of the magnitude and phase are calculated for different values of the capacitance mismatch (i.e., 2, 5, 10, and 20 %) at 1 MHz operating frequency and plotted in Fig. 12.

Fig. 12

The relative variations of the magnitude and phase for different capacitance mismatch variations

As shown in Fig. 12, the relative phase variations are higher than the relative magnitude variations and also increasing at a higher rate. Moreover, the relative variations in magnitude and phase due to the capacitance mismatch are smaller than that due to the resistance mismatch by a factor of 10. This shows that the selection of the resistances should be done very carefully as the resistance mismatch has an impact on the proposed circuit performance. However, this impact is still not significant as it is less than 4 % when the resistance mismatch variations are 20 %.

Figure 13 displays the relative magnitude and phase variations for different frequency values at 20 % capacitance mismatch. It is shown that increasing the operating frequency helps in reducing the relative phase variations significantly (i.e., when the frequency changed from 1 to 10 MHz, the relative phase variations dropped by a factor of 5).

Fig. 13

The relative variations of the magnitude and phase at different frequencies (the capacitance mismatch variations are fixed at 20 %)

5 Experimental and simulation results of the proposed CMBG

To verify the operational characteristics of the proposed CMBG, the circuit of Fig. 9 was simulated using PSPICE version 9.1. The proposed CMBG was also prototyped, tested in the single-ended input mode and the simulation results verified. Each OFCC was constructed using an Analog Devices AD846AQ current feedback op amp [15] and current-mirrors composed of Harris transistor array CA3096CE [16]. The AD846AQ has a bandwidth of 80 MHz at unity gain, and slew rate 450 V/μs. We connected the input voltage to v_in1 and connected v_in2 to the ground. Resistors R_w1 and R_w2 were set at 1 KΩ, while R_L1 and R_L2 were set at 1.5 KΩ and R_G was tested at values of 220Ω and 1 KΩ. All resistors have 1 % tolerance. For these resistors values, the low frequency gains were 6.8 (16.7 dB) and 1.5 (3.5 dB), respectively. The output-signal phase and amplitude differences were measured with respect to frequency. The amplitude error |∆V |in dB for the two values of R _G is shown in Fig. 14. This error is 0 dB for R_G = 220 and 1 KΩ for frequencies up to 1 MHz. The phase-difference error ∆Φ for the two values of R _G is shown in Fig. 15, the system phase error remained less than about 1◦ for frequencies up to 1 MHz for R _G  = 1 kΩ and R _G  = 220 Ω. This performance up to 1 MHz is superior to the circuit performances in Ref [5–8]. Figures 14 and 15 confirm the independence of both the phase and amplitude responses with changing of R_G. Also, from these figures, we can observe that the experimental results validate the simulated results and the analytical results of Eqs. (40) and (41), except at frequencies approaching the bandwidth of the OFCC. The difference between the experimental and simulation results can be interpreted as a result of tracking errors and the presence of additional stray capacitances at the various nodes in the circuit. The oscilloscope output taken at 1 MHz is shown in Fig. 16 with R_G = 1 KΩ.

Fig. 14

The amplitude response with R_G = 220 and 1 K Ohm

Fig. 15

The phase response with R_G = 220 and 1 K Ohm

Fig. 16

Sample of the results with R_G = 1 K Ohm and frequency = 1 MHz

6 Discussion

Table 1 shows a performance comparison between the proposed current-mode balanced generator circuits and the other circuitry that used to provide the same functions [5–7]. Balanced generator circuits proposed in Ref. [5, 6] which utilized the operational amplifiers, these circuits require the amplifier-pole matching and gain restrictions. Inversely, the current-mode balanced generator, which uses two CCII+ and two Op-amps, or four CCII+ , Ref. [7, 8], respectively, have better amplitude and phase performance at low frequencies. However at high frequencies, the amplitude and phase errors increase and depend on the gain dependent resistor (R_G), see Eqs. (1) and (2). Also, these topologies use 2 CCII+ in conjunction with 2 op-amps or 4 CCII+, which means more power consumption. The power consumptions and the expected fabrication area of the circuits proposed in Refs. [5–8] are as shown in Table 2 [15–18]. From Table 2, the expected fabrication die area of the proposed circuit is outperforming the circuits provided in Refs [7, 8]. For example, the expected die area of the circuit proposed in Refs [5, 6] is calculated as follows: the die area of a single LF351 Op-Amp is 2.286 × 2.286 mm² = 5.2258 mm² [17], there are two Op-amps used to implement the circuit proposed in Refs [5, 6], thus the total expected die area is 2 × 5.2258 mm² = 10.4516 mm². The expected die area of the proposed circuit is calculated as follows: The OFCC consists of 1 × AD846 current feedback amplifier and 2 × CA3069 transistor array [15, 16]. The die area of AD846 current feedback amplifier is 2.2 × 2.64 mm² = 5.808 mm² [15]. The die area of the CA3096 is 0.74 × 0.74 mm² = 0.5476 mm² [1]. Thus, the total die area of a single OFCC is 5.808 + (2 × 0.5476) = 6.9032 mm² and the total die area of the proposed CMBG which includes 2 × OFCC is 2 × 6.9032 = 13.8064 mm². Similarly, the expected die areas of the circuits proposed in Ref. [7, 8] are calculated and shown in Table 2. The power consumption of the proposed circuit is better than Refs [5–7]. However, Ref [8] shows better power consumption compared to the proposed circuit. On the other hand, the proposed topology uses only two OFCCs. It has a phase and amplitude errors 1 and 0 dB, respectively, up to frequency 1 MHz. This performance up to 1 MHz is superior to the circuit performances of Ref. [7, 8]. The proposed circuit’s output phase and amplitude are independent of R_G, see Eqs. (39) and (41). In other words, in the proposed circuit R_G controls only the gain of v_o1 and v_o2, as shown in Eqs. (35) and (36) and it does not control the phase or amplitude difference, as proven in Eqs. (39) and (41). Figure 17 shows the amplitude and phase performance of the proposed circuit and the circuit in Ref. [7], when R_G = 1 KΩ. This figure shows that the proposed circuit provides accurate amplitude and phase-matched balanced signals for frequencies up to 1 MHz compared with circuit in Ref. [7]. The power consumption and expected fabrication area of the proposed circuit are 179.5 mW and 13.8064 mm², respectively.

Table 1 Comparison between the proposed and other CMBG circuits

Table 2 Power consumption and expected die area of the proposed and other CMBG circuits

Fig. 17

The amplitude and phase responses of the circuit in Ref. [7] and the proposed circuit when R_G = 1 K Ohm

7 Conclusion

A new CMBG circuit based on an OFCC has been proposed, simulated and prototyped. The experimental results show that the new CMBG configuration has the following advantages: it produces accurate amplitude-matched balanced signals for frequencies up to 1 MHz without using matched devices. The voltage gain, as well as the bandwidth, of the proposed CMBG is independent of R_x of the current feedback op-amp used and dependent only on the external resistors (i.e., R_G and R_L). The mismatching impacts on the proposed CMBG are presented and discussed. The proposed CMBG is not complicated and offers advantages over and above currently used CMBG. On the other hand, it would be suitable candidate for integration in an IC process. Thus, it can be used in many applications, such as biomedical and lab-on-a-chip.