1 Introduction

Since the invention of transistor, outstanding evolution of semiconductor industry has made the world’s electronic life faster and easier beyond imagination [1]. The origin of this tremendous growth of microelectronic industry is the continuous down-scaling of transistor size. Various parasitic capacitances involved in a circuit also reduce with the down-scaling of device size and thereby, speed of the circuit is enhanced [2,3,4]. However, the adverse effect of various short channel effects (SCEs) on device electrical characteristics is becoming more severe with every advancement of transistor technology [5]. At different phases of time, microelectronic industry came up with unique solutions to the increasing problem of SCEs. Down-scaling of planer 2-D MOSFETs has achieved its physical limit long ago and hence, these are being replaced by new FET architectures such as SOI FETs, multi-gate FETs, FinFETs etc. However, these contemporary devices have their own limitations. SOI FETs, which outperform 2-D planer FETs in terms of speed and power consumption, are not being largely produced anywhere in the world due to its costly wafer development process [6,7,8,9]. Using double-gate in a planer FET enhances gate control and provides increased drive current (Ion) by creating two separate 2-D inversion layers. However, these inversion layers may overlap with each other beyond a critical body thickness (5 nm or less) [10, 11]. In such case, carriers in the overlapped channels encounter two opposite gate-fields as a consequence of which carrier–carrier scattering and surface roughness scattering increases and thereby Ion degrades [11,12,13,14]. Further, on-current (Ion) degradation due to SOI-thickness-fluctuation-induced-scattering in thin-body multi-gate transistors limits scaling of device size [14]. Double/triple gate FinFETs with very thin fins also suffer from Ion degradation for the same reason explained for multi-gate planer FETs. Besides, down-scaling of FinFETs demands high aspect ratio (height to width) fins. But, manufacturing of such fins is becoming a challenging task for lower technology nodes, as these 3-D fins standing alone may be damaged/washed away during cleaning, particularly when using sonication for enhanced particle removal, which is important for cleaning of 3-D relief [10, 11, 15, 16].

Therefore, we need a reliable FET architecture which is capable of mitigating the current limitations of various contemporary devices (SOI FETs, multi-gate FETs, and FinFETs). In 2014, a new FET structure called vertical super-thin body (VSTB) FET [11] was proposed. VSTB FET is a single-gate structure, in which its vertical thin body is firmly supported by one or more shallow trench isolation (STI) dielectric walls. Unlike multi-gate FETs, a single gate controls overall electrostatics of such device; thus for ultra-thin body (UTB) dimensions, carrier–carrier scattering reduces in the channel and Ion improves [10,11,12,13,14]. Also, STI dielectric wall supports the vertical thin body to enhance its mechanical strength and hence, helps reliable scaling process [10, 11]. 2-D analytical modeling for surface potential and threshold voltage of VSTB FET has also been developed [17]. But, an extensive study on vertical super-thin body (VSTB) FET performance in presence of various device constraints is needed to be developed to establish its reliability for circuit applications. For deep-submicron FETs, substantial increase in gate leakage current through thin SiO2 gate dielectric layer is a serious concern [18, 19]. To solve this issue, replacement of SiO2 gate dielectric by several high-k dielectrics such as Y2O3, Al2O3, La2O3, HfO2, and their related compounds has been investigated [20, 21], out of which, Hf-based oxides have drawn most research attention as the interface quality of these oxides with bulk Si is better than any other high-k dielectric/Si interface [22,23,24]. However, it has been reported in many research papers that HfO2/Si interface suffers from large number of trap charges [25,26,27]. Therefore, performance assessment of transistors with such oxide–semiconductor (HfO2/Si) interface is needed to be investigated in terms of various trap distribution types and concentrations. Apart from that, MOS device operation is affected by various noise sources such as diffusion, generation–recombination/G–R, and flicker noise [28,29,30,31].

In this work, a simulation study on net noise (diffusion + generation–recombination + flicker) and RF performance of VSTB FET in presence of uniform and Gaussian trap distributions is reported. The basic physics working behind the degradation of device performance due to trap presence at the oxide–semiconductor (HfO2/Si) interface is discussed. The dependency of individual noise power spectral density (PSD) on trap distribution types, trap concentrations, and operating frequency is also addressed here.

2 Device geometry and simulation strategy

Figure 1a depicts the complete 3-D view of VSTB FET and Fig. 1b shows 2-D cross-sectional view of the same. Different steps for fabrication method of such structure are also described [11]. The thin vertical body is supported by STI dielectric wall at one side. Arsenic (As) is used as the doping element in the source and drain regions and phosphorus (P) is used for doping in the body region. The doping concentrations used for various regions are: source: 1019 cm−3, channel: 1015 cm−3, drain: 1017 cm−3, and substrate: 1015 cm−3. To reduce leakage current (Ioff), lower doping is used in the drain region as compared to the source region. However, on-current (Ion) degradation due to increased drain resistance in the lightly doped drain (LDD) is an issue. High-k dielectric oxide HfO2 (εr = 22) and TiN (work function = 4.66 eV) are used as gate dielectric oxide and gate metal, respectively. Various device dimensions used are: channel length (LCH = 26 nm), gate thickness (Tg = 5 nm), body thickness (Tb = 5 nm), and oxide thickness (Tox = 2 nm). Equal source and drain extension length (w = 4 nm) are used. Height of body (h1) and substrate (h2) uses are 35 and 20 nm, respectively. Height of SiO2 layer (h) placed between source/drain/gate contacts and substrate is 15 nm.

Fig. 1
figure 1

Vertical super-thin body (VSTB) MOSFET a complete 3-D view, and b 2-D cross-sectional view across XY plane

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3-D and 2-D Sentaurus TCAD tool based on drift diffusion transport model [17, 32, 33] was used to perform the work. Initially, the input and output characteristics were studied using 3-D TCAD tool [32]. As the ITRS outlined all the desired values of various figures of merit (FoM) of future technology nodes in terms of per micrometer [34], we eventually focused on device cross-sectional performance in presence of traps and various noises. Therefore, device noise characteristics and RF performance were investigated by 2-D TCAD tool [32]. Relevant physics models were activated in the simulator to study various realistic phenomena effecting device electrical characteristics. Influence of high doping concentrations was taken care of by activating the Fermi–Dirac statistics and doping-dependent Shockley–Read–Hall (SRH) recombination model [32]. Bandgap narrowing was enabled to take care of highly doped source and drain regions [32]. Influence of device doping profile and high-k dielectric oxide on carrier mobility was accounted by enabling doping-dependent Masetti model and enhanced Lombardi model with high-k degradation, respectively [32]. Velocity saturation effect, which is a very common SCE for nanoscale device, was taken care of by triggering high-field saturation model [32]. Quantum density gradient model was also enabled to consider quantum correction effect [32]. Stress and strain may be induced in the thin vertical body by the thick STI dielectric wall. To acknowledge the stress effect, stress-induced electron mobility model and stress-dependent saturation velocity model were included [32, 35, 36]. Deformation potential model was activated to consider strain effect [32, 35, 36]. Device performance in n-type FET mainly gets degraded due to acceptor-like traps [37]. Regarding traps located at the insulator–semiconductor (HfO2/Si) interface, two types of trap (acceptor-type) distribution were considered in this work: uniform and Gaussian [28, 32] as below:

$$d_{{{\text{UNI}}}} = N_{0} \;{\text{for}}\;E_{0} - 0.5E_{{\text{S}}} < E < E_{0} + 0.5E_{{\text{S}}} ,$$
(1)
$$d_{{{\text{GAU}}}} = N_{0} \exp ( - (E - E_{0} )^{2} /2E_{{\text{S}}}^{2} ).$$
(2)

Various parameters related to the above distribution functions are described in Table 1. Also, both the trap distributions over an energy range considered in this work are shown in Fig. 2 [28].

Table 1 Various parameters of trap distribution
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Fig. 2
figure 2

Uniform and Gaussian trap distribution vs. energy [28]

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3 Results and discussion

The main objective of the work is to study device performance dependency on trap distribution type and concentration. In Sect. 3.1, input characteristics of FinFET and VSTB FET are compared. Also, a basic study on output characteristics of 3-D VSTB FET device is presented with the help of energy band diagram. Section 3.2 presents the transfer characteristics (ID–VGS) degradation in presence of various types of trap distributions and concentrations. Net noise parameters for the cumulative effect of three noise sources (diffusion + generation–recombination/G–R + flicker) at low and high frequencies (f = 1 MHz and f = 10 GHz) are also discussed. In Sect. 3.3, frequency and trap dependency of G–R and diffusion noise are addressed. Lastly, in Sect. 3.4, variation of RF FoM with respect to variation in trap concentration and distribution type is presented.

3.1 Study of basic characteristics (input and output)

TCAD extracted 3-D simulated views of single gate FinFET, inner view of FinFET, and VSTB FET are shown in Fig. 3a–c, respectively. The simulation set up, various dimensional parameters, and materials used for FinFET is kept as the same (described in Sect. 2) as used for VSTB FET. The input characteristics (ID–VGS) of both the devices are compared in Fig. 3d, which demonstrates that VSTB FET exhibits much better off-current (Ioff) and subthreshold swing (SS) as compared to the same-scale FinFET device. Such superiority in Ioff and SS is found since, vertical STI dielectric wall in VSTB FET offers pseudo-SOI type of isolation between source and drain [11]. On the other hand, absence of such isolation in FinFET device increases Ioff and thus, SS deteriorates significantly. Table 2 presents a comparative overview between various electrical parameters of FinFET and VSTB FET. Drain-induced barrier lowering (DIBL) for VSTB FET is calculated from Fig. 3e using the relation [38]:

$${\text{DIBL}} = (V_{{\text{T,lin}}} - V_{{\text{T,sat}}} )/(V_{{{\text{DS}}_{{{\text{sat}}}} }} - V_{{{\text{DS}}_{{{\text{lin}}}} }} ),$$
(3)
Fig. 3
figure 3

TCAD extracted views of simulated 3-D devices a FinFET, b inner view of FinFET excluding gate and gate oxide, c VSTB FET; ID–VGS plots of d FinFET and VSTB FET, e FinFET for DIBL calculation, f ID–VDS plot of VSTB FET for different VGS values

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Table 2 Comparative performance analysis of FinFET and VSTB FET
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where \(V_{{{\text{DS}}_{{{\text{sat}}}} }} = 1\;{\text{V}}\) and \(V_{{{\text{DS}}_{{{\text{lin}}}} }} = 0.05\;{\text{V}}\). VT,lin and VT,sat are threshold voltages (estimated for a constant current of 10–7 A) at \(V_{{{\text{DS}}_{{{\text{lin}}}} }}\) and \(V_{{{\text{DS}}_{{{\text{sat}}}} }}\), respectively. The output characteristics (ID–VDS) of the device is depicted in Fig. 3f, which shows that the device works for low values of VDS too. At VDS = 0, a little ID flow is observed (Fig. 3f) and the reason for that has been explained later on.

Device energy band (E-band) diagrams corresponding to three different bias conditions: zero bias/equilibrium (VGS = 0, VDS = 0), bias 1 (VGS = 0.8, VDS = 0), and bias 2 (VGS = 0.8, VDS = 0.4), are shown in Fig. 4a–c, respectively, from which the internal physics working behind device electronics can be understood. Under equilibrium condition, source-to-channel transition barrier (Fig. 4a) is very high for which channel cannot form. Besides, level of conduction band (EC) at drain side (64–94 nm) is higher than that of source side (0–30 nm) due to the doping nature of the device (source: 1019 cm−3, drain: 1017 cm−3). Thus, ID is zero for zero bias condition. Under bias 1 (VGS = 0.8, VDS = 0), gate field reduces source to channel barrier height, which is also evident from Fig. 4b; thus source electrons move to channel region and form inversion layer. Another observation of Fig. 4b is that in the channel region (34–60 nm), conduction energy level (EC) lies below the electron Fermi level (Efn), which illustrates that the channel behaves as degenerate semiconductor. At such condition, although VDS = 0, gate fringing fields contribute a little amount of lateral fields which lead to weak movement of the channel electrons to the drain [39]. Thus, at VDS = 0 too, a negligible flow of ID is observed (Fig. 3f), which increases with the increase in VGS. In Fig. 4c, under bias 2 (VGS = 0.8, VDS = 0.4) EC at the drain side goes down that of source and channel region; thus channel electrons can easily move to the drain and contribute to significant ID flow. Here also, channel behaves as degenerate semiconductor.

Fig. 4
figure 4

Energy vs. device length for a zero bias/equilibrium (VGS = 0, VDS = 0), b bias 1 (VGS = 0.8, VDS = 0), and c bias 2 (VGS = 0.8, VDS = 0.4)

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3.2 Study of device characteristics in presence of traps and corresponding net noise performance

This section presents device performance in presence of various trap distributions and the net noise (diffusion + G–R + flicker) characteristics. From Fig. 5a, b, which depict ID–VGS plot for uniform trap (UT) and Gaussian trap (GT) distributions, respectively, it is clear that with increasing trap concentration (TC) for both the distributions (UT and GT), the transfer characteristics deteriorate from their ideal nature (under no trap condition). Traps present in the semiconductor-insulator surface create extra energy states, which randomly capture and later release carriers moving through the channel and thus, alter E-band diagram of the device. Figure 5c, d represent, respectively, E-band diagrams for UT and GT distribution. For both the distributions, at the channel region (34–60 nm) EC goes up of Efn, which illustrates the fact that interface trap reduces carrier density at the channel region. Thus, at a fixed value of VGS, number of channel charges decreases more and more with increasing TC and hence, ID degrades (Fig. 5a, b). For a particular trap concentration, degradation of ID is more severe in case of GT (Fig. 5b). This happens due to non-uniform distribution of Gaussian traps. Although, degradation in ID for any type of trap (UT/GT) is negligible for lower TC [(1011–1013) eV−1 cm−2], effect of the traps on ID becomes prominent for TC = 1014 eV−1 cm−2 (Fig. 5a, b).

Fig. 5
figure 5

ID–VGS plot variations for a uniform trap (UT) distribution, and b Gaussian trap (GT) distribution; energy vs. device length for c UT distribution, d GT distribution

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For ideal condition (no trap), the estimated value of cross-sectional ID is 114.562 µA/µm at VGS = 0.65 V and 127.18 µA/µm at VGS = 0.7 V. In this section, at VDS = 0.4 V, Ion is calculated as ID at VGS = 0.65 V (VGS = 0.7 V) for UT (GT) distribution. For such estimated Ion, in ideal condition (no trap), value of Ion/Ioff is 0.73 × 108 for UT and 0.81 × 108 for GT. The values of Ioff (at VGS = 0 V and VDS = 0.4 V) and SS under no trap condition are 1.56477 pA/µm and 66.17 mV/dec, respectively. Variations of Ioff, Ion, Ion/Ioff, and SS with respect to trap distribution type and TC are shown in Fig. 6a–h. Figure 6a, c, e, g corresponds to UT and Fig. 6b, d, f, h corresponds to GT. Both, Ioff (Fig. 6a, b) and Ion (Fig. 6c, d), decrease for the presence of UT/GT traps. However, since, decrease in Ioff is relatively higher than decrease in Ion, Ion/Ioff (Fig. 6e–f) shows improvement for increasing TC (UT/GT) except for the case of GT of TC = 1014 eV−1 cm−2 (Fig. 6f). For GT with such high TC (1014 eV−1 cm−2), Ion reduces drastically (Fig. 6d), which leads to fall of Ion/Ioff. On the other hand, to attain any particular value of ID, since, device with interface traps needs more VGS than any ideal device (with ideal interface), deterioration in SS increases with increasing TC (Fig. 6g, h). Percentage changes in Ion/Ioff and SS in trap-affected device with respect to ideal condition (no trap) is presented in Table 3.

Fig. 6
figure 6

Different parameters as a function of trap distribution types and concentration a Ioff for UT, b Ioff for GT, c Ion for UT, d Ion for GT, e Ion/Ioff for UT, f Ion/Ioff for GT, g SS for UT, and h SS for GT

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Table 3 Device performance deviation for different types of trap distribution and concentration
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Figure 7a, b represents gate voltage electron noise spectral density (Svgee) as a function of VGS for UT and GT, respectively. Electron density across the channel length for maximum GT concentration of 1014 eV−1 cm−2 at two frequencies is shown in Fig. 7c. Plots of drain current noise spectral density (Sid) vs. VGS for UT and GT are shown in Fig. 7d, e, respectively. From Fig. 7a, b, d, e, it is clear that at a fixed VGS value, PSDs of both types of noise (Svgee and Sid) fall by a large order for high frequency (f = 10 GHz), as the charge trapping probability also reduces at higher frequencies [40]. This property helps the device to work efficiently at higher frequencies.

Fig. 7
figure 7

Net noise (diffusion + G–R + flicker) PSDs: gate voltage electron noise spectral density (Svgee) for a uniform trap (UT), and b Gaussian trap (GT); c electron density across the channel length (LCH); drain current noise spectral density (Sid) for d uniform trap (UT), and e Gaussian trap (GT)

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At f = 1 MHz, under no trap condition and for both the trap distributions (Fig. 7a, b), Svgee plots, following several spikes, gradually decrease with increase in VGS. Such nature of plot can be explained by the carrier concentration variation in the channel for varying VGS values. At lower VGS, channel consists of very low concentration of charges. In such a state, random capturing and releasing of charges by the traps lead to large variation in the number and velocity of channel charges, which eventually reflect on Svgee values. At higher VGS, inversion layer is formed and channel charge concentration becomes very high. Therefore, any type of variation in charge concentration due to traps is now weakly felt by the high concentrated channel charges, and hence, Svgee decreases for higher VGS.

However, at f = 10 GHz, for lower values of VGS (Fig. 7a, b), Svgee initially increases and then slowly gets saturated at higher VGS. For the same VGS value, charge density developed across the channel at high frequency is lower than that of low frequency (Fig. 7c). As such, at lower VGS, very less number of charges exist in the channel and hence, probability of charge trapping also becomes low at high frequency. But, beyond a critical value of VGS charge concentration in the channel increases, and due to this, charge trapping probability becomes high; thereby, Svgee also starts to increase (for VGS > 0.15 V in Fig. 7a, b). However, for very high VGS (> 0.75 V in Fig. 7a, b), Svgee gets saturated due to the same reason explained for reduction in Svgee at f = 1 MHz for high VGS. Another observation of Fig. 7a, b is that the net value of Svgee at any particular frequency increases with increasing trap (UT/GT) concentration. This happens due to the greater charge-trapping probability with higher TC. Also, compared to UT distribution, GT distribution contributes to higher Svgee.

Sid variations with respect to change in VGS follow such pattern (Fig. 7d, e), which increases initially for lower VGS, but gets saturated for VGS> 0.6 V, as ID also saturates at higher VGS. Also, PSD of Sid is lesser at f = 10 GHz due to reduction in the charge trapping probability at high frequency [40]. It is observed that for TC of the order of 1014 eV−1 cm−2, Sid pattern deteriorates to a large extent from its linear characteristics at lower VGS. Also, GT distribution (Fig. 7e) has more significant effect on Sid compared to UT distribution (Fig. 7d).

3.3 Individual noise (G–R and diffusion) performance

It is observed that at low and high frequencies, the net noise (diffusion + G–R + flicker) characteristics of the device are dominated by generation–recombination (G–R) noise and diffusion noise, respectively [28]. Flicker noise, the origin of which is the conductance fluctuation of charge carriers moving through a channel affected by contaminants, is much prominent at lower frequencies and decreases significantly with increase in frequency [29, 30]. As the primary focus is on high frequency, flicker noise effect can be ignored for advanced devices. In this section, we perform a study on G–R and diffusion noise nature of the device. We have considered only Gaussian trap (GT) distribution, as with this type of distribution device performance gets more affected, which have already been seen in Sect. 3.2. Figure 8a, b shows Svgee vs. VGS plots for G–R noise at f = 1 and 10 GHz, respectively. Same type of plots for diffusion noise are shown in Fig. 8c (f = 1 MHz) and (d) (f = 10 GHz).

Fig. 8
figure 8

Gate voltage electron noise spectral density (Svgee) for Gaussian trap (GT) distribution a G–R noise at f = 1 MHz, b G–R noise at f = 10 GHz, c diffusion noise at f = 1 MHz, and d diffusion noise at f = 10 GHz

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Comparing Fig. 8a, c, it is clear that for any given value of VGS in the case of G–R noise, the PSD of Svgee is much higher at f = 1 MHz than that of diffusion noise. At low frequency, the fluctuation in concentration and velocity of the carriers is mainly caused by Shockley–Read–Hall (SRH) and defect centres associated with the channel [31] and hence, Svgee for G–R noise becomes high. Also, PSD of Svgee increases for higher trap concentration (Fig. 8a). Again, at f = 1 MHz for a given value of VGS comparing Figs. 7b and 8a (Sect. 3.2), it can be seen that the net Svgee curves (Fig. 7b of Sect. 3.2) for different trap concentrations are also following almost the same pattern of Svgee corresponding to G–R noise only (Fig. 8a). At f = 10 GHz, for all values of VGS, amplitude of Svgee exhibits higher values in case of diffusion noise (Fig. 8d) than that of G–R noise (Fig. 8b). At high frequency, probability of charge trapping and de-trapping by recombination centres is reduced. For fast variation of VGS, channel charges undergo a diffusion mechanism, the rate of which is a strong function of VGS. Thus, if VGS varies very fast, the average diffusion rate of carriers also changes significantly with time, leading to a prominent diffusion noise at high frequency. Irrespective of VGS values, the net noise PSDs (Svgee in Fig. 7b of Sect. 3.2) at f = 10 GHz are comparable to diffusion noise Svgee curves (Fig. 8d).

3.4 Device RF performance in presence of traps

The RF performance is studied under three cases: no trap (NT), uniform trap (UT), and Gaussian trap (GT). Figure 9a–f correspond to various RF parameters like transconductance (gm) at f = 10 GHz, total input capacitance (Cgg) at f = 10 GHz, total input capacitance (Cgg) at f = 1 kHz, gate-drain capacitance (Cgd) at f = 10 GHz, unit-gain cutoff frequency (fT) at f = 10 GHz, and gain–bandwidth-product (GBP) at f = 10 GHz as a function of VGS, respectively. The variations shown are for trap concentration of 1014 eV−1 cm−2.

Fig. 9
figure 9

RF figures of merit (FoM) as a function VGS and trap nature a transconductance (gm), b input capacitance (Cgg) in f = 10 GHz, c input capacitance Cgg in f = 1 kHz, d gate-drain capacitance (Cgd), e unit-gain cutoff frequency (fT), and f gain–bandwidth-product (GBP)

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It can be seen from Fig. 9a that as VGS starts to increase, gm rises sharply at three different VGS values for three different cases (NT, UT, and GT). The point of VGS, at which gm rise occurs, shifts towards right as we go from NT to UT to GT. Generally, for a fixed value of VDS, when VGS is applied, rise in ID occurs at the lowest VGS under NT condition. But, presence of traps hinders the normal ID rise nature by participating in channel transport mechanism. At such condition, effective channel charge becomes a function of interface traps and mostly reduces. Therefore, both ID and gm fall. This is the reason behind the right shifting of gm rise point across VGS axis. As the effect of GT is more prominent than that of NT and UT distribution, gm rise requires larger VGS in case of GT as compared to the other two cases. From Fig. 9b, it is clear that at f = 10 GHz for a given amplitude of VGS as we go from NT to UT to GT, the value of Cgg follows a descending order. Also, distortion/stretch out in capacitance–voltage (C–V) plot (Fig. 9b) is not observed. The reason of such nature of C–V plot is as follows: at high-frequency (f = 10 GHz) interface traps, which have longer charging/discharging time constant compared to time-period of applied high-frequency gate bias, cannot response as fast as applied gate field; thus the distortion/irregularity in charge distribution caused by interfacial traps becomes minimal at high frequency. However, at low frequency (f = 1 kHz), interfacial traps actively participate in channel charge distribution and thus randomness/distortion is added to the C–V plot, which is also observable in Fig. 9c. The peak value of Cgd (Fig. 9d) is seen to follow an ascending order going from NT to UT to GT. The unit-gain cutoff frequency (fT) and GBP are calculated from the relations [28, 41, 42]:

$$f_{{\text{T}}} = g_{{\text{m}}} /2\pi C_{{{\text{gg}}}} ,$$
(3)
$${\text{GBP}} = g_{{\text{m}}} /20\pi C_{{{\text{gd}}}} ,$$
(4)

fT and GBP (Fig. 9e, f) attain peak values at smaller VGS under NT condition. But, introduction of traps degrades fT and GBP at lower VGS by suppressing gm (Fig. 9a). All the values of different RF FoM: peak transconductance (gmp), peak input capacitance (Cggp), peak gate-drain capacitance (Cgdp), maximum cutoff frequency (fTmax), and maximum gain–bandwidth product (GBPmax) for the three cases (NT, UT, and GT) are listed in Table 4, from which it can be concluded that VSTB FET is suitable for high-frequency operations.

Table 4 RF FoM for various trap distributions
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4 Conclusion

In this work, the effect of various interfacial trap (HfO2/Si) distributions on VSTB FET performance is presented. It is observed that the Gaussian trap (GT) distribution disturbs fundamental parameters such as Ion, Ion/Ioff, and SS significantly. Irrespective of trap distribution types (UT/GT), for trap concentration < 1014 eV−1 cm−2 device performance shows negligible deterioration. The change in energy band diagram for a particular bias condition in presence of interfacial traps (UT or GT) is also discussed. A qualitative analysis of net noise (diffusion + G–R + flicker) and individual noise PSD dependency on trap distribution type and concentration is also reported. It is observed that for lower values of VGS too, the values for unity-gain cutoff frequency (fT) and gain–bandwidth-product (GBP) of the device are in gigahertz (GHz) range; this property helps the device to work efficiently in low-power high-speed circuits.