Keywords

1 Introduction

The oscillator is a closed loop system with positive feedback which follows the Barkhausen criteria to get a sustained oscillation. If the oscillator circuit can generate two outputs with 90º phase difference, then it is known as a quadrature oscillator (QO). Oscillators are very important and integral part of the various communications and control systems [1, 2]. An enormous variety of quadrature oscillators using different active building blocks (ABB) were already reported in [3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29]. Oscillators reported in [3,4,5,6,7,8,9,10] are able to generate current-mode outputs while voltage mode outputs are obtained in [11,12,13,14,15,16,17,18,19,20,21,22,23]. Also, among these oscillators, none is able to generate both voltage mode (VM) and current mode (CM) signals at the same time. This issue is compensated in the circuits reported in [24,25,26,27]. In [28], a digitally programmable VMQO was firstly introduced. But, these oscillators have one or more than one of the following drawbacks

  1. (i)

    Require two or more ABBs [25,26,27];

  2. (ii)

    Require four or more passive components [24, 26, 27];

  3. (iii)

    Require floating passive components for realization [26];

  4. (iv)

    Lack of electronic tuning [24, 26]

  5. (v)

    Except [28] no other circuits can provide digital control feature.

So in this manuscript, an electronically tunable, digitally controlled CM QO is designed to overcome all the drawbacks mentioned above. The proposed QO topology requires one DC-VDTA with three grounded passive elements. As this circuit utilizes only passive elements, so the presented design is acceptable for IC realization. The functioning of DC-VDTA is explained in the next section.

2 DC-VDTA

The DC-VDTA is a modified version of VDTA [29] as shown in Fig. 1. The aspect ratio of all the transistors utilized in realization of DC-VDTA is defined in Table 1. In VDTA, the digital controllability is achieved by adding an n-bit DCU between first and second stage

$$I_{x} = {\text{Kg}}_{m2} V_{Z} \quad {\text{where}}\,K = \frac{\beta N}{{2^{n} }}$$
(1)
Fig. 1.
A circuit diagram of D C V D T A. 2 sets of parallelly connected CMOS inverters, M 1 to 4 with I B 1 and 2, and M 5 to M 7 with I B 3 and 4 respectively are on either end. A 4-bit D C U with A 1 to 4 is connected in between. Set M 1 to 4 has V P and V N, while M 5 to 8 has x negative and positive.

CMOS structure of DC-VDTA

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Table 1 Aspect ratio
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where K is the n-bit digital control input, n is number of control lines in DCU, and N is the digital control word.

The other port characteristics of DC-VDTA is given as

$$I_{N} = I_{P} = 0,\quad I_{Z} = g_{m1} \left( {V_{N} - V_{p} } \right)$$
(2)

where \(g_{m1}\) and \(g_{m2}\) are the transconductances of DC-VDTA.

3 Digital Control Unit (DCU)

In this manuscript, a 4-bit DCU is utilized. The CMOS structure of DCU is illustrated in Fig. 2. The output of DCU is determined as

$$V_{{{\text{out}}}} = \frac{{V_{{{\text{in}}}} }}{{2^{4} }}\left( {A_{1} + 2A_{2} + 2^{2} A_{3} + 2^{3} A_{4} } \right) = KV_{{{\text{in}}}}$$
(3)
Fig.2.
A circuit diagram of a 4-bit D C U. A 1 to 4 each have sets of 4 MOSFET transistors connected in parallel and series and a NOT gate. Transistors M 31 to 38 are connected to V in, M 21, 22, 31, and 41 are connected to V gate, and M 11 to 14 give V out.

4-bit DCU

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where \(A_{1} ,A_{2} ,A_{3}\) and \(A_{4}\) are the bit values of digital control word.

4 Proposed QO

The proposed structure of QO using DC-VDTA is illustrated in Fig. 3. Subsequent by applying KCL at different node, we get the characteristic equation,

$$s^{2} + \frac{s}{{C_{1} }}\left( {\frac{1}{{R_{1} }} - g_{m1} } \right) + \frac{{\beta Ng_{m1} g_{m2} }}{{2^{n} C_{1} C_{2} }} = 0$$
(4)
Fig. 3
A circuit diagram of the proposed Q O with a D C V D T A block at the center that has 4 pins. N and X positive connect to capacitor C 2. P connects to a parallel setup of R 1 and C 1 that is grounded. X negative gives the output.

Proposed QO

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The CO and FO are determined from Eq. (4)

$${\text{CO}}:\quad \frac{1}{{R_{1} }} - g_{m1} \le 0\quad {\text{and}}\quad {\text{FO}}:\quad \omega = \sqrt {\frac{{\beta Ng_{m1} g_{m2} }}{{2^{n} C_{1} C_{2} }}}$$
(5)

The proposed circuit is able to provide the quadrature current signal, and their amplitude ratio is mentioned in Eq. (6)

$$\frac{{I_{C2} \left( {j\omega } \right)}}{{I_{C1} \left( {j\omega } \right)}} = K\frac{{g_{m2} }}{{\omega C_{2} }}\angle - 90^{^\circ } ,\quad \left| {\frac{{I_{C2} \left( {j\omega } \right)}}{{I_{C1} \left( {j\omega } \right)}}} \right| = \sqrt {\frac{{2^{n} g_{m2} }}{{\beta Ng_{m1} }}}$$
(6)

5 Non-ideal and Sensitivity Analysis

A non-ideal analysis of the proposed DC-VDTA is also investigated with considering the parasitic port element. A DCVDTA with parasitic element is shown in the Fig. 4. By considering the parasitic elements, the characteristic equation will be given as

$$\begin{aligned} & s^{2} \left( {C_{1} + C_{p1} } \right)(C_{2} + C_{p2} ) + s\left\{ {\left( {C_{1} + C_{p1} } \right)\frac{1}{{R_{p2} }}} \right. \\ & \quad + \left. {(C_{2} + C_{p2} )\left( {\frac{1}{{R_{1} }} + \frac{1}{{R_{2} }} - g_{m1} } \right)} \right\} + \frac{1}{{R_{1} R_{p2} }} + \frac{1}{{R_{p1} R_{p2} }} \\ & \quad - \frac{{g_{m1} }}{{R_{p2} }} + Kg_{m1} g_{m2} = 0 \\ \end{aligned}$$
(8)
Fig. 4
A circuit diagram for a non-ideal model of a D C V D T A. N and X positive connect to a parallel setup of C 2, C P 2, and R P 2 that is grounded. P and z connect to a parallel setup of R 1, C 1, C P 1, and R P 1 that is grounded. X negative gives I 3.

Non-ideal model of DC-VDTA

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As \(C_{1} \gg C_{p1}\) and \(C_{2} \gg C_{p2}\) then the capacitance \(C_{1}\) and \(C_{2}\) will eliminate the effect of \(C_{p1}\) and \(C_{p2}\) respectively. So, the parasitic capacitance does not affect the functioning of QO, but the parasitic resistance will affect its functioning.

The active and passive sensitivities of proposed oscillator are given as

$$S_{{C_{1} ,C_{2} }}^{\omega } = - 0.5,\quad S_{{g_{m1} ,g_{m2} }}^{\omega } = 0.5$$
(9)

So, the sensitivity values are low and lie within the specified range.

6 Simulation Results

To observe the functionality of proposed QO, the Pspice simulation is carried out using 180nm technology. To design the QO 4-bit DCU is used with the components values are C1 = C2 = 50pF, R1 = 1.7KΩ, VDD = 0.9V, VSS = -0.9V, and for IB1 = IB2 = IB3 = IB4 = 150μA the value of gm1 = gm2 = 611μA/V. The 4-bit DCU will help to generate sixteen different frequency signals. The transient response of designed QO for control words N =1 and 6 are demonstrated in Fig. 5. The steady state characteristic is also been shown in Fig. 6. The quadrature outputs IC1 and IC2 are having a phase shift of 89.3°. The variation in calculated and measured frequency is also shown in Fig. 7 that indicates that the both values are closely related.

Fig. 5
2 line graphs of current versus time. The fluctuating lines for I C 1 and C 2 gradually increase in amplitude and have the highest fluctuations after 30 microseconds in graph a for N equals 1, and after 10 microseconds in graph b for N equals 6.

Steady state response of the QO for a N = 1 b N = 6

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Fig. 6
A line graph of current versus time. The out-of-phase sine waves for I C 1 and I C 2 start from around (100, negative 20) and (100, 40) respectively.

Steady state response

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Fig. 7
A line graph plots frequency in megahertz versus code words N equals 0 to 16. The increasing line starts from the origin, fluctuates till around (4, 4.2), and then has a linear trend to end at around (15, 8.2).

Frequency Deviation

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7 Conclusion

A digitally controlled VDTA (DC-VDTA) and its application as digitally controllable QO have been reported for the first time. The proposed QO requires only one DC-VDTA and three grounded passive elements that make the circuit suitable for fabrication. The 4-bit DCU can generate sixteen different frequencies of quadrature output for different combinations of control word. The FO and CO can be controlled electronically and independently. The FO can also be modulated through the both grounded capacitors. The functioning of the circuit is validated through the Pspice simulations.