Improved Non-isolated DC-DC Boost Converter with High Gain Capability for Renewable Energy Microgrids

Abstract

DC-DC boost converter with high gain plays a major role in renewable energy microgrids. The research on high gain boost converters is increasing rapidly with several types of configurations, to improve their effectiveness and make them more reliable. Despite having many topologies invented, there are certain drawbacks associated with them such as high losses and stress on the switch, high ripple current and switching frequency, configurations with low gain and more number of components. So there is a need to provide the best boost converter topology which is transparent through the aforementioned drawbacks. The proposed work gives the best high gain boost converter topology which is having less no of components and provides high gain, which is in turn suitable for renewable energy applications. The entire simulation work has been carried out with the help of the MATLAB/Simulink environment.

1 Introduction

Due to the emergence of the industrial revolution and rapid population growth, the ease of energy consumption was increased to a greater extent. So there is a need to increase the production of energy by using renewable energy sources such as solar panels, fuel cells etc. But the magnitude of output voltage that is obtained from these solar panels is considerably less, which is not required to produce sufficient energy from microgrids. Here comes the importance of high gain DC-DC boost converters. These high gain converters will boost the magnitude of voltage to desired levels to produce a sufficient amount of energy.

1.1 Problem Statement

The conventional boost converter configuration as shown in Fig. 1 is able to scale up the voltage level 2 times more than that of the input voltage. It comprises a MOSFET, diode, inductor and capacitor. The MOSFET will act like a switch that requires controlled gating pulses for its operation.

Fig. 1

Basic DC-DC boost converter circuit

The working of the conventional boost converter is as follows,

• When the switch is on, the inductor gets charged up with the help of supply voltage. Here the voltage across the inductor ($V_L$) and supply voltage ($V_{in}$) will be the same as they are in parallel.

• When the switch is off, the current flow path will flow through the inductor, diode and capacitor. So according to basic network rules, the voltage measured across the inductor is shown by Eq. 1.

  $$ V_C = V_{out} = V_{in} + V_L $$

  (1)

As the voltage across the inductor ($V_L$) and supplied voltage ($V_{in}$) are equal, Eq. 1 can also be represented as shown in Eq. 2.

$$ V_{out} = V_{in} + V_{in} = 2V_{in} $$

(2)

So as per the input–output relation, the conventional boost converter can scale up 2 times that of the input voltage. The gain of the traditional boost converter is only 2, which is not suitable for renewable energy applications.

1.2 Literature Survey

Several kinds of high gain boost converter topologies already existed in literature [1]. But, there are a few drawbacks associated with them like a higher number of components, high switching frequency and voltage gain for the existed topologies in the literature.

The topology that is demonstrated in [2] has less no of components, but it has a high switching frequency of 40 kHz. It requires a high amount of cost for the topologies having a higher switching frequency. A topology that was shown in [3] has the disadvantage of having a greater number of components and a high switching frequency used in its configuration. Besides, it has a greater advantage of producing a higher voltage magnitude of around 20 times that of input voltage. A topology which is described in [4] has a greater benefit because of having a higher gain of 25, But it also shows its disadvantages of having a high switching frequency of 118 kHz and more components used. The topology which is demonstrated in [5] has the advantage of having a gain of 20 in producing voltage levels. Despite having a higher gain, this topology requires more no of components and a higher switching frequency of 46 kHz for its operation. There exists one topology as depicted in [6] that is not suitable for renewable energy applications, as it takes a greater no of components of about 22 and a higher switching frequency of 100 kHz.

A topology which was shown in [7] will have a weak point of having less gain value of only 2 and a higher switching frequency of 100, Besides, it shows its advantage in having less no of components. The topology which is shown in [8] has the advantage of having less no of components used for its construction and less switching frequency of about 10 kHz. Besides, it can only produce output voltage levels of 2 times more than the input voltage. The topology which is described in [9] can produce an output voltage magnitude which is 30 times more than the input voltage. Although it is having a minimal number of components needed to build switching frequency. A topology which is shown in [10] was chosen as the worst topology because of having a number of components required of almost 33, But it requires less amount switching frequency of 10 kHz. The topology which was demonstrated in [11] has a higher amount of switching frequency of about 200 kHz, which is not advisable for any application. This topology is having a considerable gain value of 10. The topology shown in [12] has the disadvantage of having more number of components and a considerable voltage gain value of 10. The topology shown in [13] has the disadvantage of having less gain of about 9 and more no of components required for its construction.

1.3 Paper Contribution and Organization

The topologies which are having less number of component count have more switching frequency. Subsequently, the topologies which are having more gain value require more no of components to build. So there is a tradeoff between the number of components, gain values and switching frequency. The objective of the proposed work is to develop one unique boost converter topology, which produces a high gain compared with conventional topologies. Further, the proposed topology is best suitable for renewable energy applications. Additionally, the proposed topology was compared with some considerable conventional topologies in terms of total no of components, voltage gain and performance indices.

2 Description of the Proposed Topology

The proposed topology had designed and simulated in Simulink as shown in Fig. 2. The proposed topology consists of five energy storing elements, i.e., two inductors and three capacitors, it also consists of one MOSFET and one resistor used for switching and load purposes respectively. The specifications of the circuit are, the input voltage V_in = 10 V; switching frequency f_s = 10 kHz; the values of passive elements are tabulated below in Table 1.

Fig. 2

Proposed DC-DC boost converter circuit

Table 1 Component specifications

By simulating the circuit, it is observed that the output voltage V_out = 181.8 V, from that it is determined that the gain of the circuit is 18.19 which means the output is approximately 18 times that of the input value.

The output equation of the proposed topology has been derived by linearizing the circuit. When the switch is turned on, the equivalent circuit is shown in Fig. 3. Applying Kirchhoff’s voltage law for the 3 loops, we get,

Fig. 3

Simplified circuit of the proposed topology when the switch is in the ON state

The KVL equation for loop 1 is given by Eq. 3.

$$ V_{in} = I_1 L_2 s + \frac{1}{C_2 s}\left( {I_1 - I_2 } \right) $$

(3)

The KVL equation for loop 2 is given by Eq. 4.

$$ \frac{1}{C_2 s}\left( {I_2 - I_1 } \right) + L_1 s\left( {I_2 - I_3 } \right) + I_2 R_{eq} = 0 $$

(4)

The KVL equation for loop 3 is given by Eq. 5.

$$ \frac{1}{C_3 s}I_3 + L_1 s\left( {I_3 - I_2 } \right) = 0 $$

(5)

By rearranging Eqs. (3)–(5) with respect to current $I_1 ,\,\,I_2 ,\,\,I_3$ the following equations are obtained as shown in Eqs. 6–8.

$$ V_{in} = \left( {L_2 s + \frac{1}{C_2 s}} \right)I_1 - \left( {\frac{1}{C_2 s}} \right)I_2 $$

(6)

$$ - \left( {\frac{1}{C_2 s}} \right)I_1 + \left( {\frac{1}{C_2 s} + L_1 s + R_{eq} } \right)I_2 - \left( {L_1 s} \right)I_3 = 0 $$

(7)

$$ - \left( {L_1 s} \right)I_2 + \left( {\frac{1}{C_3 s} + L_1 s} \right)I_3 = 0 $$

(8)

The matrix representation of Eqs. (6)–(8) is shown in Eq. 9.

$$ V_{in} = \left[ {\begin{array}{*{20}c} {\left( {L_2 s + \frac{1}{C_2 s}} \right)} & { - \frac{1}{C_2 s}} & 0 \\ { - \frac{1}{C_2 s}} & {\frac{1}{C_2 s} + L_1 s + R_{eq} } & { - L_1 s} \\ 0 & { - L_1 s} & {\frac{1}{C_3 s} + L_1 s} \\ \end{array} } \right]\left[ {\begin{array}{*{20}c} {I_1 } \\ {I_2 } \\ {I_3 } \\ \end{array} } \right] $$

(9)

The resultant product $I_2 \times R_{eq}$ will give the output equation of the proposed topology. Here $I_2$ can be found by using the crammers rule as mentioned in Eq. 10.

$$ I_2 = \frac{\Delta_2 }{\Delta } $$

(10)

Here $\Delta$ represents the determinant of the matrix. As per the crammers rule, the value $\Delta_2$ can be found as Eq. 11. Similarly, $\Delta$ can be found as Eq. 12.

$$ \left. \begin{gathered} \Delta_2 = \left| {\begin{array}{*{20}c} {\left( {L_2 s + \frac{1}{C_2 s}} \right)} & {V_{in} } & 0 \\ { - \frac{1}{C_2 s}} & 0 & { - L_1 s} \\ 0 & 0 & {\frac{1}{C_3 s} + L_1 s} \\ \end{array} } \right| \hfill \\ \Rightarrow \Delta_2 = V_{in} \left[ {\begin{array}{*{20}c} { - \frac{1}{C_2 C_3 s^2 }} & {\frac{ - L_1 s}{{C_2 s}}} \\ \end{array} } \right] = V_{in} \frac{{\left[ { - 1 - L_1 C_3 } \right]s}}{C_2 C_3 s^2 } \hfill \\ \end{gathered} \right\} $$

(11)

$$ \left. \begin{aligned} & \Delta = \left| {\begin{array}{*{20}c} {L_2 s + \frac{1}{C_2 s}} & { - \frac{1}{C_2 s}} & 0 \\ { - \frac{1}{C_2 s}} & {\frac{1}{C_2 s} + L_1 s + R_{eq} } & { - L_1 s} \\ 0 & { - L_1 s} & {\frac{1}{C_3 s} + L_1 s} \\ \end{array} } \right| \hfill \\ & \Rightarrow \Delta = \frac{{\left( {R_{eq} L_1 L_2 C_2 C_3 } \right)s^4 + \left[ {L_1 L_2 \left( {C_2 + C_3 } \right)} \right]s^3 + \left( {L_2 C_2 + L_1 C_3 } \right)R_{eq} s^2 + \left( {L_1 + L_2 } \right)s + R_{eq} }}{C_2 C_3 s^2 } \hfill \\ \end{aligned} \right\} $$

(12)

So, $I_2$ can be found by dividing $\Delta_2$ and $\Delta$. The resultant $I_2$ is as Eq. 13.

$$ I_2 = \frac{{V_{in} \left( { - s\left[ {1 + L_1 C_3 } \right]} \right)}}{{\left( {R_{eq} L_1 L_2 C_2 C_3 } \right)s^4 + \left[ {L_1 L_2 \left( {C_2 + C_3 } \right)} \right]s^3 + \left( {L_2 C_2 + L_1 C_3 } \right)R_{eq} s^2 + \left( {L_1 + L_2 } \right)s + R_{eq} }} $$

(13)

Thus, the final output voltage equation of the proposed topology is given as Eq. 14.

$$ V_{out} = \frac{{V_{in} \left( { - s\left[ {1 + L_1 C_3 } \right]} \right)R_{eq} }}{{\left( {R_{eq} L_1 L_2 C_2 C_3 } \right)s^4 + \left[ {L_1 L_2 \left( {C_2 + C_3 } \right)} \right]s^3 + \left( {L_2 C_2 + L_1 C_3 } \right)R_{eq} s^2 + \left( {L_1 + L_2 } \right)s + R_{eq} }} $$

(14)

Table 1 comprises values of the passive components of conventional topologies and proposed topology. Here for the comparison purpose, all the capacitor ratings are taken the same. Inductor ratings of the proposed topology are less compared to ratings of conventional topologies. All three ratings of the proposed topology don’t exceed the ratings of conventional topologies. The design equations for the calculation of inductance and capacitance are given in Eqs. 15 and 16.

$$ L = \frac{{D\left( {1 - D} \right)R}}{2f} $$

(15)

$$ C = \frac{D}{2fR} $$

(16)

3 Simulation Results and Discussion

From Fig. 4, it is found that the settling time is 30 ms and the output voltage is 181.9 V. In the zoom-in graph, it is observed that the change of voltage is slow because of capacitors. It is known that the capacitor doesn’t allow the sudden change in voltage because that saw tooth graph had occurred in the output graph. The voltage of the saw-tooth is fluctuating between 168.7 and 181.8 V. Here maximum voltage is considered as the output of the circuit.

Fig. 4

Output of the proposed topology

3.1 Conventional Versus Proposed Topology Analysis

The simulation models of conventional topologies are shown in Figs. 5 and 6. From Table 2, it is found that the total number of components of the proposed topology is less than conventional topologies. Here, the majority number of switches is one and the number of diodes is very less compared to conventional topologies which leads to a decrease in the cost of the circuit.

Fig. 5

Conventional topology-1 [12]

Fig. 6

Conventional topology-2 [13]

Table 2 Comparison of number of components used in conventional and proposed topologies

Tables 2 and 3 comprise the input voltage (V_in), output voltage (V_out), number of components, duty cycle, switching frequency, and the gain of circuits. Here proposed topology is compared with conventional topologies. The input voltage, switching frequency, and duty cycle are considered the same for all three topologies so that comparison will be good. It is observed that gain is high for the proposed topology compared to the other two topologies, and almost the sum of gains of two conventional topologies is equal to the proposed topology’s gain.

Table 3 Analysis of output responses of conventional and proposed topologies

From Table 4, it is summarized that conventional topology—2 has peak-overshoot at 104 V. So, it is not preferred. There is no peak-overshoot in the output response of conventional topology-1 as shown in Fig. 7 and the proposed topology. Settling time is less for proposed topology, so it is good compared to conventional topologies. Delay time and rise time are high for the proposed topology and low for conventional topology-2 as shown in Fig. 8. The comparative response of conventional, as well as proposed topologies, is given in Fig. 9 for better visualization.

Table 4 Analysis of the transient performance of conventional and proposed topologies

Fig. 7

Output of conventional topology-1

Fig. 8

Output of conventional topology-2

Fig. 9

Comparison of responses produced by conventional and proposed topologies

4 Conclusion

Thus, this paper considers the following factors to look at the best circuit, those are gain, number of components, switching frequency, duty cycle, and number of sources. For the desired circuit following criteria should be followed, the gain should be high, the number of components should be less, and switching frequency should be less. From the summary of Tables 2, 3 and 4, it is observed that the proposed topology satisfies the maximum criteria that are given as follows.

• High gain

• Less number of components

• Less switching frequency

• Less settling time

• No peak-overshoot

• Low cost.