Evaluation of Digital Circuit Methodologies in Nanotechnology Using QCA - Quantum Dot Cellular Automata

Abstract

Quantum dot Cellular Automata (QCA) has more popularity in the near market due to its advantages over CMOS technology such as high device density, low power consumption and high computing efficiency. The major concern in circuits is to achieve improvement in QCA parameters like number of QCA Cells, cells area, total area, delay, energy consumption and single or multilayer layout. In this paper we will discuss about various techniques or methodologies to achieve improvement in these parameters. Different methodologies need to be designed to have optimization, automation and verifications in design. These techniques are primarily based on Logic synthesis, layers, clocking in QCA, feedback in QCA, QCA cell arrangements, use of tools to design the circuits, use of 3 × 3 or 5 × 5 QCA tiles etc. In today’s era, less energy consumption is also a very important parameter. The main objective of this paper is to get the details of these techniques to improve the parameters. QCADesigner 2.0.3 and QCADesigner–E software are used to get the implementations in QCA field.

1 Introduction

International Technology Roadmap for Semiconductors (ITRS) [1] has devised Nano devices like Carbon nanotube transistors (CNT), Single Electron Transistors (SET), Resonant Tunnelling devices (RTD), Quantum dot Cellular Automata (QCA) etc. as shown in Fig. 1. These are used to overcome the limitations of CMOS devices scaling. QCA is the best nanotechnology device among all these Nano devices.

Fig. 1

Nano devices [1]

QCA is efficient, has very high device density and low power consumption. It is transistor less and can operate at Terahertz (THz) range. CMOS technology works on current switching whereas QCA represent binary information on the cells.

QCA is now used to design digital circuits in almost all the fields. Researchers have designed the circuits with different methodologies in QCA. In this paper, these different methodologies are discussed with their method and achievements in terms of various parameters.

In the remainder of this work, in Sect. 2, earlier reported work on QCA methodology is reviewed and compared. Section 3 shows the implementations of different methodologies for different circuits. This paper is one umbrella under which different methods are compared and analyzed. In Sect. 4, the work is concluded.

2 Methodologies

Till now, researchers have proposed different ways to design digital circuits to achieve optimization in terms of circuit area, number of cells, speed and complexity. In this section, these different methodologies are studied, analyzed and compared with standard parameters of interest. Various methodologies used are coplanar, multilayer, novel input technique, Bottom up design approach with special cell arrangements, keeping fixed input cells, inter cellular effect technique, PPDD technique, using 3 input standard MV gate and 5 input MV gate, using only one type of cell, tile based, models based, with simplified Boolean expressions, using different clocking etc. Circuits like NOT gate, XOR gate, the one used in building almost all the complex circuits, multiplexer, full adder, parity generator, latch, RAM etc. are implemented with these methodologies. Tables 1, 2 and 3 shows the comparison of all methods with respect to parameters and circuits implemented.

Table 1 Different methodologies used to implement XOR gate

Table 2 Different methodologies used to implement multiplexer

Table 3 Different methodologies used to implement full adder

Comparative table for the methodologies shows that cell interaction or intercellular effect technique is the best to implement XOR gate and parity generator (4 bit, 8 bit, 16 bit and 32 bit) with low power consumption, less number of cells, less area and increased speed. Novel input technique is the best way to implement 2:1 multiplexer. Many implementations are seen for full adder but using MV5 is the best method with least cells, area and delay as indicated in Table 4.

Table 4 Best method analyzed

3 Implementations

This section shows the implementations of best methodologies for various circuits. QCADesigner tool is used to build the layout of various circuits and to observe the simulation result. Cell interaction method is the best method as per as cell area is concerned. Table 1 clearly indicates that, with the other methodologies the parametric values are high for XOR gate. As a case study the XOR gate implementation with other best methods is as shown in Fig. 2a–c.

Fig. 2

XOR gate layout with the best methodologies a [6], b [3], c [2]

Graphical representation indicates that cell interaction or intercellular effect technique [6] is the best methodology among the all as it shows the optimization in all the parameters with respect to the other methodologies. This methodology can build all other circuits using this XOR gate with best optimization. Cell count is indicated in Fig. 3, device density in Fig. 4 and delay in Fig. 5 for all methodologies considered here for different circuits.

Fig. 3

Cell count

Fig. 4

Device density

Fig. 5

Delay

4 Conclusion

Optimizing key metrics like delay, cell count and cell area will help improving logic computation and information flow at the physical level implementation. Although QCA logic components can be designed with QCA gates, extra delays will be introduced, which can lead to incorrect timing relationships. These timing issues present difficulties for interconnection and feedback which can affect the performance of QCA circuits. Therefore, assigning correct and efficient clocking zones to circuits is a major challenge in QCA circuit design. These all issues lead to design an efficient methodology to optimize all the parameters especially density, speed and less power consumption.