Keywords

1 Introduction

Improvement in VLSI technology is necessary for the betterment of electronic devices. MOSFET device dominated the entire VLSI technology from many years, but now due to further scaling of MOS devices it leads the severe SCEs, subthreshold leakage, more standby power dissipation and reliability variations which drastically affects the circuit performance and reliability of the system (Turi and Delgado-Frias 2017). The main challenge faced by future bulk MOS scaling is process and material technology limitations. Continuous efforts are made by the researchers to expand the silicon scaling results into innovative material and device structures to overcome the limitations of bulk MOSFET. A FinFET is one of these innovations, and FinFET becomes a popular transistor due to its front and back gate structure. The transistor’s current and threshold voltage can monitor by biasing these gates properly which helps to manage the problem of standby power dissipation. Figure 8.1 represents the structure of FinFET device (Gupta et al. 2019). Multi-gate transistors are a considerable option for nanoscale VLSI technology. FinFET gains the limelight among all multi-gate MOSFET devices due to its better control to SCEs, lower leakage, excellent isolation and more driving capability for both low-power and fast speed applications.

Fig. 8.1
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Basic FinFET structure

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Most of FinFETs are double-gate devices with vertical fins in the gate. In FinFET, channels are created on both sides of the fin and at the top end. There are no free carriers available because of the finlike structure, so this particular FinFET structure is the main reason for suppressing SCE in FinFET (Zimpeck et al. 2015). Better subthreshold slope, excellent SCE control, independent gating and less random doping fluctuation are the best qualities of FinFET that makes it more superior to MOS technology (Bagheriye et al. 2018). The front and back gate of FinFET provides better control over the channel which in turn reduces the leakage current and SCE, so FinFET is the suitable device to replace the MOS technology in the future VLSI technology (Taghipour and Asli 2017; Mukhopadhyay et al. 2018). Due to the low leakage power of FinFET, it becomes a very popular choice for memories. Memories are used most commonly in digital systems, and a large amount of power is saved in memories with FinFET devices.

1.1 Scaling Challenges in MOSFET

Aggressive scaling of MOSFET causes various challenges in VLSI technology, and one of the most prominent drawbacks of MOS scaling is SCE. In a deep submicron region, when the channel length of device is less than 100 nm, SCEs start to degrade the circuit performance and are also known as second-order effects. The key SCEs are hot carrier effect, threshold voltage variations, gate-induced barrier lowering, velocity saturation.

Due to short channel length, subthreshold or weak conduction current occurs between the drain and source in MOS transistor when the gate voltage (\(V_{\text{GS}}\)) is less than the threshold voltage (\(V_{\text{T}}\)). This small leakage current is known as subthreshold leakage current and affects the performance of the transistor. Detail of scaling challenges and its impact on CMOS performance is studied in reference (Jacob et al. 2017). Most portable devices, such as mobile devices, laptops and various communication devices, have long downtime and run in standby mode if not in use. But there is a small leakage current flow through the circuit due to short channel length which causes the standby power dissipation. The researcher had suggested various techniques for overcoming the shortcomings of CMOS transistors (Sharma and Pattanaik 2014). Figure 8.2 represents the main scaling challenges in MOS technology.

Fig. 8.2
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Scaling challenges in MOS technology

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Currently, one of the extremely challenging areas of research is to minimize the leakage power consumption, mostly in on-chip devices which are doubling in every two years. It is more challenging to minimize the static leakage power than the dynamic leakage power because, in dynamic power, the leakage power depends on transistors count, their operating status and type without taking into consideration the switching operation. On the other hand, when a transistor is in the OFF state, there are no input applied to a transistor, it has reached a stable state, and a small amount of leakage current flows through the transistor and causes power dissipation (Upasani et al. 2010). There are many advantages of scaling like the compact size of the devices and high speed. Despite this, there are some limitations of scaling in terms of SCEs which cause leakage current hence increasing power dissipation.

Subthreshold leakage current harms the characteristics of the devices and affects the reliability of the devices. PVT variability and reliability effect are major issues in present VLSI technology. One of the most critical and common problems of reliability is negative temperature bias instability (NBTI). NBTI directly challenges the reliability of digital VLSI devices. As a result, the circuit delay exceeds the design specification and there may be timing violations or logic failure (Mahapatra et al. 2013; Khoshavi et al. 2017). Nowadays, electronic devices are facing a problem of PVT variations and it affects the various performance parameters. The electronics industry is moving from MOS transistor to FinFET, but the problem of PVT variations is still present (Sharma and Pattanaik 2014; Yang and Jha 2014).

In this chapter, we are focusing on PVT variations and consider the impact of PVT variability on FinFET devices and various techniques or methodologies adopted by the researcher to mitigate the PVT variability effect.

1.2 FinFET Structure and Operation

The further scaling of MOS transistors is not much profitable for both the research community and the VLSI industry. FinFET is an appropriate transistor to take the position of the MOS transistor. Dr. Chenming Hu has been known as the father of the 3D transistor because he has proposed the concept of FinFET in 1999 (Gupta et al. 2019). FinFET is a type of non-planar or 3D multi-gate transistor in which the channel has a thin vertical fin and the gate is fully enclosed around the channel between the drain and the source. It looks like a fin of fish when viewed so its name has been derived from this fact. FinFET channels are created at the topside and two sidewalls of a fin which provide better control on the channel and give better electrostatic control and electrical characteristics (Zimpeck et al. 2015). High channel doping is required for low leakage current in MOS devices, but this degrades the carrier mobility of a transistor. Gate dielectric with high ON current and good channel control is highly on demand for low-power applications. The gate leakage current through thermal oxide becomes escalated as oxide thickness approaching 2 nm (Rosner 2003).

The working operation and fabrication process of FinFET are almost identical to MOS except for some modifications (Walke et al. 2017; Chen et al. 2018). One of the challenges of manufacturing the FinFET is doping of the drain–source junction in the fin region. Uniformly distributed doping is needed along the fin height and width so that angled implantation is required on the side of the fin. In the case of planar device junction formation, there are various standard techniques for analyzing and monitoring the implantation of dopant on the planar surface, but these methods are not suitable for FinFET junction formation due to the 3D structure of a fin (Pham et al. 2006; Lee et al. 2010). Fin height is the most important parameter for the FinFET fabrication process because it determines the minimum FinFET width (\(W_{\min}\)). A minimum transistor width of two gates FinFET is given below (Gupta et al. 2019):

$$W_{\min} = 2H_{\text{fin}} + T_{\text{fin}}$$
(8.1)

Here, \(H_{\text{fin}}\) is the fin height and \(T_{\text{fin}}\) silicon body thickness. A fin height has more impact on transistor width than the \(T_{\text{fin}}\) component as seen from Eq. (8.1). \(H_{\text{fin}}\) is fixed in a FinFET, so to increase the FinFET width we can create multiple parallel fin structures. The total physical transistor width (\(W_{\text{total}}\)) of a tied FinFET gate with n parallel fins can be calculated as shown in Eq. (8.2) (Gupta et al. 2019)

$$W_{\text{total}} = nW_{ \min } = n\left( {2H_{\text{fin}} + T_{\text{fin}} } \right)$$
(8.2)

FinFET is designed with multiple parallel fins to achieve larger channel widths (Colinge 2008). The number of fins at FinFET should be increased to increase the current through the transistor (Sinha et al. 2012; Tawfik et al. 2007). A multiple fin structure of FinFET achieved superior performance but increases the device degradation due to hot carrier effect. When FinFET has multiple fins, then coupling effect in the steep and silicon fin decreases the conduction of the inversion channel carrier and degrades the FinFET performance (Yeh et al. 2018). Double-gate FinFET structure is more preferable due to this reason because it improves the electrostatic integrity, reduces the SCE and minimizes leakage current (Yang and Jha 2014).

The three types of FinFET structures are: shorted gate (SG) FinFET, independent gate (IG) FinFET and asymmetric gate work function shorted gate (ASG) FinFET. In SG FinFET, two gates at the top are shorted together and provide a large drive current. ASG FinFET is the same as SG FinFET in case of a layout area, but ASG FinFET having a different work function for both the gates. ASG FinFET provides a lower leakage current but degrades around 26% of ON state current (\(I_{\text{ON}}\)). If both FinFET gates are controllable independently, then FinFET is called IG FinFET. IG FinFET has less leakage current than SG FinFET, but it increases the layout area and causes severe degradation in ON state current (Bhattacharya et al. 2015; Yang and Jha 2013).

2 PVT Variations

PVT variations are one of the scaling challenges faced by the FinFET technology, show abnormal power consumption due to PVT variations and accelerate the degradation of the circuits (Zimpeck et al. 2015). Variations are classified into two categories: process variation and environmental variation. Additional environmental variability involves variation in temperature and supply voltage across the circuit. The key source of variation in supply voltage variation and temperature variation is voltage (IR) drop in power grid and switching activity deviation across the chip, respectively. The principal cause of process variation (PV) is variations in the physical parameters of devices that take place during a manufacturing process.

2.1 Process Variations

PV is introduced during the fabrication process due to unavoidable errors. As VLSI technology moves toward the deep submicron regime, integrated circuits (ICs) become more sensitive to PV. Process variation is divided into two parts: non-systematic and systematic. A variation in the electrical characteristics of two transistors with the same length and width is recognized as systematic variations and can be adjusted by detailed layout analysis during the manufacturing process. On the other hand, non-systematic variation is a non-predictable part of process variation, and these variations are an unexplainable component of the fabrication process. Non-systematic variations are further classified into two parts: intra-die variation and inter-die variation. Inter-die variation is due to the lack of manufacturing control and induced by technical constraints. Deviation in some parameter value over nominally equivalent manufactured dies refers to inter-die variation. Inter-die variations may occur on the different wafers, or same wafer or different lots (Ezz-Eldin et al. 2015). Figure 8.3 shows the classification of variations. Among all these variations, voltage, temperature and systematic variations can be evaluated and improved by researchers. On the other hand, non-systematic variations are difficult to identify and become unpredictable parts of variations. Intra-die variation affects the various devices on the same die differentially and is further categorized into correlated and random variation. Correlated variation depends on the location of the devices. This closely spaced device has more similar variations than those located far apart. Etching, layout and lithographic information can be required to design, estimate and reimburse for correlated variation. Random variation is considered statistically independent of all other variation components.

Fig. 8.3
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Classification of variation

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Random variation results from edge roughness of gate line and fluctuation of random dopant. Figure 8.4 shows the main factor of PVT variation. During the manufacturing process lithography phase, process variations are mostly induced and the variability in PVT can be divided into three factors:

Fig. 8.4
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Main factor of PVT variation

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  • Environmental factors: Power supply and temperature fluctuations are the main causes of environmental variations and mainly appeared during the circuit operations.

  • Reliability factors: Mainly caused by a transistor aging and the high electrical field in modern circuits.

  • Physical factors: Variations in geometric and electrical parameters which induce a lag in transistor performance also trigger process variation.

2.2 Supply Voltage Variation

Voltage drops or noisy power sources are the main source of supply voltage variations. Supply voltage variations have a great impact on leakage power, dynamic power and logic gate timing (Yang and Jha 2013). One of the most important parameters of the circuit is supply voltage because it affects the system performance. The gate delay depends upon the saturation current, and saturation current depends upon the supply voltage. FinFET technologies use high-k/metal gate stack to boost gate control over channel region, the main source of statistical variations is metal gate granularity, and this contributes to grain orientations that have different work functions. These imperfections can influence the various parameters of FinFET, and the entire block of cells compromises due to variations in transistor structure. Therefore, circuits also suffer from some electrical deviations (Zimpeck et al. 2018; Ban et al. 2014).

2.3 Temperature Variations

The temperature of the blocks in IC depends on the power consumption of a block itself and on lateral heat transfer; it also depends on adjacent blocks. A temperature variation comes under the environmental variation factor and mainly causes due to deviations in switching activities of the device. Fluctuations in temperature are dictated by the leakage current and timing characteristics. Due to the unpredictable dopant fluctuation and the sub-wavelength lithography, nanodevices are more susceptible to variability effect. PV directly affects the threshold voltage of FinFET varying various aspects of transistor cells (Almeida et al. 2018). PVT variations are inherent, and essential steps must be taken during the early design step. Figure 8.5 presents the geometric parameters of FinFET which include drain, source and gate (Lee and Jha 2014). To reduce leakage current (\(I_{\text{OFF}}\)) and improve ON current (\(I_{\text{ON}}\)), fin engineering is the most essential part during the fabrication process (Yang and Jha 2014). A previous study shows that fin width and gate length have a major impact on \(I_{\text{ON}}\) and \(I_{\text{OFF}}\), but the greatest variance in both currents is due to work function fluctuations (WFFs) that creates a significant deviation in total power that must be considered in the design of VLSI.

Fig. 8.5
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Geometric parameters of FinFET

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PV is inherent in the fabricating processes of semiconductors and impacts on circuit performance and reliability. It is becoming more difficult to determine the circuit performance with the constant change in the circuit elements (logic gates and interconnections). Interconnect variation and gate variation appear to be considering in random variations. Uncertainties in metal line dimensions lead to interconnect variations. A variation in gate process causes change in MOS parameters which create the gates manufactured different from the ones designed. Gate width (\(W_{\text{GATE}}\)), gate oxide thickness (\(T_{\text{OX}}\)), gate length (\(L_{\text{GATE}}\)) and threshold voltage (\(V_{\text{T}}\)) are mostly affected parameters by the process variation during the fabrication process (Zimpeck et al. 2015). PV impact translates into variation in device and interconnects electrical parameters such as delay, throughput and leakage power variation. FinFET is one of the newest transistors in VLSI technology, and many works are going on.

3 Literature Review

Continuous scaling of the MOSFET leads to an increase in aging effect, leakage current and soft error that compels the VLSI technology to move toward the multi-gate devices. FinFET is the best multi-gate device because of its outstanding isolation and high driving capacity for both low-power and high-speed applications. PVT variation is a challenging problem in FinFET and degrades the circuit performance, so researchers have adopted various techniques and methodologies to alleviate this effect. In this part, we are discussing the impact of PVT variations on FinFET devices and various techniques/methodologies adopted by researchers to improve the performance of FinFET devices.

3.1 Impact of PVT Variations on FinFET-Based Memories

Memories are always a big part of VLSI digital technology, and applying the FinFET technology to memories introduces an evolution in digital technology due to a huge amount of power-saving. Static random access memory (SRAM) is one of the commonly used memories in VLSI technology, and it always demanded faster design and lower power consumption. Data stability is the biggest problem in the SRAM cell, and this problem becomes more severe with scaling of MOSFET in the sub-nanometer regime. Intra-die and inter-die variations are the main cause of instability in SRAM, so multi-gate devices like FinFET become a better choice for SRAM cell (Kushwah et al. 2016). The impact of FinFET technology on SRAM cells, back gate biasing strategies and performance of SRAM cell under temperature, voltage and parameter variations can be seen in Turi and Delgado-Frias (2017). Leakage power can be reduced up to 65X in a six-transistor FinFET SRAM cell (Tawfik and Kursun 2008).

Researchers proposed IG FinFET SRAM cells that used back gate biasing and PMOS access transistors to achieve high stability performance (Bagheriye et al. 2018). Designers find that FinFET is more appropriate than MOS in deep sub-micron region especially after 22 nm because of its excellent SCEs, improved sub-threshold slope, independent gating, and less random doping fluctuations. Researchers proposed an architecture-level approach to improve the array robustness, but this type of approach results in area overhead and makes complex circuit design. Researchers also suggested design of FinFET SRAMs based on asymmetric structures like asymmetric drain and source, having different work functions and oxide thickness for the FinFET front and back gate. Those structures are highly sensitive to fluctuations in process parameters. There are various techniques to improve SRAM performance in reference (Bagheriye et al. 2018) and given as:

  • Front and back gates are operating independently as they offer flexibility in design as a substitute for threshold voltage control for improving the cell stability of FinFET SRAM.

  • A write static noise margin (WSNM) and read static noise margin (RSNM) are enhanced by decreasing and increasing the threshold voltage of an access transistor, respectively, using the independent gate.

  • To dynamically increase the RSNM without increasing the area overhead, built-in feedback technique is used in which the back gate of the access transistor is connected to corresponding nodes.

  • In some approaches, the p-channel metal–oxide–semiconductor (PMOS) is used in place of the n-channel metal–oxide–semiconductor (NMOS) to improve circuit stability and reduce the risk of leakage current.

  • To reduce an access time, strain effect is incorporated with PMOS access transistor in the SRAM cell.

  • Schmitt’s trigger-based feedback system was used to increase the RSNM, WSNM and tolerance to PV in the subthreshold region, but these cells suffer from low read current and area overhead in this procedure.

The author proposed two cells in reference (Bagheriye et al. 2018); first cell consumes low power and enhances the read and write margins. The second cell provides high write and read margins with high read current. Aging effect due to BTI influences, PVT variations and single event upset is the main issue in nanometer IC design. Read noise margin is the most sensitive SNM and is deeply affected by PVT variation and aging effect (Almeida et al. 2018). Read operation is performed by a P-type gate and write operation performed with the help of transmission gate to achieve high switching activity in 7T FinFET SRAM. This type of configuration of SRAM provides up to 60.8% of supply voltage reduction (Sneha et al. 2017).

Standard MOS scaling technology driven by higher operating speed, integration density and lower power dissipation has faced many barriers. Now, it is facing a severe variability problem. The researcher introduces a technique for the design of SRAM cell that is aware of variability. The proposed cell’s architecture is identical to that of the regular 6T SRAM cell apart from that the access pass gates are replaced with transmission gates. The impact of variation on most of SRAM cell’s design metrics degrades circuit efficiency. Comparative analysis based on Monte Carlo simulation shows that the proposed design is capable of greatly mitigating the impact of variation (Islam and Hasan 2012). The detailed comparative investigation of CMOS and FinFET-based 10T SRAM cells is given and can be studied in reference (Pal et al. 2014).

On the other hand, content addressable memory (CAM) used for lookup table based application which enables high speed parallel search operations. Researchers evaluate the design space for FinFET CAMs for symmetric and asymmetric gate work functions (Bhattacharya et al. 2015). Researchers proposed diverse designs and conducted their transient and DC analysis for various mismatch conditions using the computer-aided design (CAD) tool with 22-nm FinFET devices. CAMs are often used in signal processing and in wireless sensor network applications requiring very low power consumption and extremely high speed so that this can be accomplished by developing a CAM using 22-nm and 14-nm PMOS access transistors based on the PTM-MG transistor model. From the available literature, we conclude that IG FinFET displays increased speed and lower power consumption (Arulvani and Mohamed Ismail 2018).

3.2 FinFET Standard Cells Under PVT Variability

Researchers evaluate the impact of PVT variations on power off predictive standards and timing at 20-nm FinFET technology node. The main factors in PVT variations are environmental factors, physical factors and reliability factors. Variations in electrical and geometrical parameters also provoke a delay in a transistor’s performances. Fin height, gate length, fin thickness and metal gate work function fluctuations are the main causes of process variability in FinFET devices. Researchers use more than 10,000 Monte Carlo simulations with work function parameters for PVT variability investigation. Work function fluctuations have a huge impact on OFF state leakage current, and it causes a significant deviation on the static power of standard cells (Zimpeck et al. 2015).

3.3 Flip-Flop Performance in FinFET Technology

The impact of aging effect and PVT variations on different flip-flops in FinFET and CMOS technologies and their comparative performance analysis can be seen in reference (Taghipour and Asli 2017). Hot carrier injection (HCI) and bias temperature instability (BTI) mainly affect the heftiness of high-performance FinFET. Researchers acknowledged that temperature and VDD variations are the main causes of power–delay product (PDP) degradation and propagation delay for different FinFET structures.

An average increase of performance is obtained from the following equation (Taghipour and Asli 2017)

$${\text{Average increase}}\left( \% \right) = \frac{{{\text{aged}} - {\text{Fresh}}}}{{{\text{Fresh}}}} \times 100$$
(8.3)

The long-term model can be utilized to estimate the \(V_{\text{T}}\) variations, and then the updated \(V_{\text{T}}\) is applied to the transistor model file to evaluate the BTI and HCI aging mechanism for reliability analysis. Continuous scaling of a transistor increases the consequence of process variations and aging in circuits. The effect of PV and NBTI aging over the years on the WNMs and the consequent statistical occurrence of write failures in several types of flip-flop cells is presented in reference (Khalid et al. 2015). An analysis based on the statistical characterization of WNMs is using transistor-level Monte Carlo simulations to evaluate the write failure probability as a result of an input voltage change in flip-flop cells.

3.4 Impact of Time Zero Variability and BTI on FinFET Devices

Time zero variation or prestress variations of the device are the main unease in scaled technology, and detailed study of time zero variability performance of the device helps to improve the circuit performance. Researchers evaluated that device degradation occurs due to time zero PV and BTI stress conditions and also studied the variations in a threshold voltage of a planar 10-nm FinFET system on chip, 16-nm FinFET and 20-nm FinFET device. The following points are studied in reference (Mukhopadhyay et al. 2018):

  • An impact of BTI and time zero \(V_{\text{T}}\) variations on \(V_{\text{T}}\).

  • Evaluate NBTI and positive bias temperature instability (PBTI), and their statistical performance is compared.

  • SNM degradation in SRAM cell due to bias temperature instability.

  • At last, bit- and chip-level high-temperature operating life (HTOL) test results are studied.

3.5 Impact of PVT Variations on FinFET Under Different Sizing Techniques

Different transistor arrangements can cause variations in gate variability. We can find a most suitable topology which increases the robustness of cells regarding PV. Any obviously occurring variations in the attributes of transistor like length, width and oxide thickness during the fabrication of IC are related to PV issue. The best approach for reducing the PV issue is to utilize the network which has transistors in series and as far as possible to the output (Zimpeck et al. 2018). Researchers investigate the impact of variation on power consumption and performance for various transistor sizing approaches applied to circuits in FinFET technologies and evaluate PVT variations separately. Temperature and voltage variations are united to get an insight into their contributions. Results are beneficial to describe the variability effect in the initial design steps to choose suitable transistor sizing technique for an application (Zimpeck et al. 2016).

3.6 Energy-Efficient Compressor Based on FinFETs

Multiplier is one of the important required arithmetic blocks in digital signal processing (DSP) applications and also the major energy and time-consuming block for an enormous variety of applications. So, we can improve the efficiency of these circuits by introducing FinFET in it. A designer has introduced a new energy-efficient 4:2 compressor that has less transistors, smaller areas and superior energy efficiency. This compressor provides an improvement in terms of energy efficiency and has less area overhead than the previous design (Arasteh et al. 2018).

3.7 Impact of Multiple Parallel Fins on FinFET

The unique structure and geometry of FinFET as compared to CMOS makes FinFET more reliable and efficient than CMOS. 3D fin structure of FinFET contains the current conduction between source and drain. Multiple parallel fins can be fabricated between source and drain that increases the channel width. The number of fins on FinFET shows a great impact on circuit performances and reliability. Multiple parallel fins can be used to increase the total drive current but in this case, FinFET suffers from severe degradation. A multiple parallel fin structure of FinFET reduces the inversion charge by creating charge repulsion between the fins. This increases the coupling effect between fins, and HCI is always an issue in a deep submicron region (Yeh et al. 2018).

3.8 Multicore Power, Area and Timing (McPAT)-PVT: Modeling Framework for FinFET Under PVT Variations

FinFETs have become an appropriate transistor to replace the conventional MOS transistor due to their better scalability, efficiency and a better SCE control. FinFETs have some lithographic, fabrication and environmental limitations which lead to PVT variations in FinFET IC. So, due to these variations, delay and leakage are introduced into the FinFET ICs. McPAT-PVT is an integrated framework that is considered for analysis of delay, power and PVT variations of FinFET devices. This framework consists of FinFET logic, design library and memory cells to represent circuit-level characteristics and PVT variations. Both SG and ASG FinFET-based processors are modeled by McPAT-PVT. ASG mode implementation provides the same performance but, it increases the area and more beneficial with temperature variations (Tang et al. 2015).

3.9 FinFET Performance Under Various Design Strategies

Designers varied the source and drain junction placement, punch-through stop implant and gate work function to investigate the new design approaches for 10-nm FinFET technology to satisfy low power and extremely low power requirements and to know the impact of \(I_{\text{OFF}}\), gate capacitance, transconductance and intrinsic frequency (Walke et al. 2017). Research extraction and analysis of external resistance have become important in modern CMOS technology. By adding some assumptions in shift-and-ratio methods, it can be explored for use in short channel devices and also find application in FinFET devices (Zhang et al. 2018). A transistor with reduced size and fin gate has led to important change and add a set of constructive layout design rules. Additional layers and 3D structure of FinFET changed the parameters of a parasitic element, so a comparative analysis of 28-nm planar and 7-nm FinFET CMOS is performed (Ilin et al. 2018). A FinFET with a modified drain extension exhibits a better analog and radio frequency (RF) behaviors. We can boost the cutoff frequency of power FinFET from 30 to 53 GHz by changing the drain extension from narrow fin to a planar layout. Researchers investigated the analog and radio frequency parameters of power FinFETs with diverse drain extension structures for microwave applications.

Researchers replace the bipolar junction transistor diodes with FinFET diodes in some cases and evaluate the device output without degradation. Minimum voltage headroom and less power dissipation are two benefits of using the FinFET diodes in subthreshold operation (Prilenski and Mukund 2018). New self-aligned double-gate silicon on insulator (SOI) structure FinFET is proposed as a nano-MOS device. This proposed structure suppresses SCE, even with 17-nm gate length, provides a proper \(V_{\text{T }}\) for ultra-thin body and reduces the parasitic resistance (Hisamoto et al. 2000).

The author has explored the FinFET’s best suitability for low-power applications in very short gate-length future technologies (Rosner 2003). This paper shows that the proposed FinFETs offer low-power output for the state-of-the-art bulk MOSFETs, even with relaxed gate oxide thickness. A new method of estimating the leakage is being studied in Gu et al. (2008), and the results show that the effect of the quantization of the width on the estimate of the statistical leakage is important for FinFET devices. This approach can reliably determine the statistical characteristics of the leakage current under process variation.

Designers often try to create an innovative design and structures to remove the disadvantages related to FinFET including gate buckling, fin bottom erosion, structural instability and less uniformity between fin shapes. Inverted T (IT) FinFET is an innovative design that can be used to increase a drive current with limited size (Yu 2002; Mathew 2005). IT FinFET is more beneficial than SOI FinFET because it requires wider fin width and less fin height as compared to SOI FinFET. IT FinFET is a mechanically stable structure and reduces the random dopant fluctuation and fin bottom erosion, but suffers from high OFF state current. Fin width and ultra-thin body height parameters can be used to optimize the performance of the IT FinFET, and outcomes manifest that fin width should be less than 10 nm for better immunity against SCE (Yu et al. 2018).

In the new era of VLSI technology, the compact size of devices is the primary requirement and maintaining the good performance of devices with compact size is one of the biggest challenges for research designers. Nowadays, FinFET is the most promising transistor and it is the most competent device to substitute the MOS transistors because of its outstanding controllability of the SCE, great insulation, high driving efficiency and reduced leakage current for both high-speed and low-power applications. But, some scaling challenges faced by FinFET devices and improvement are required for the betterment of VLSI technology. The impact of PVT variation is mainly on the nanotechnologies and degrades the performance of FinFET, so relevant methods and techniques are needed to improve the FinFET technology.

4 Results and Discussion

With the advancement of technology, further scaling of MOS transistors is a challenging task for research designers. FinFET is one of the best alternatives to be used for the scaling process. The main reason for FinFET’s success is its excellent SCE controllability compared to a conventional planar system. The fin like geometry of FinFETs, where the regions of depletion enter the body region from the gates, indicates that there are no free charge carriers available, making it possible to suppress SCE. Furthermore, FinFET technology dominates because it offers great isolation, less current leakage and higher driving capability.

Nonetheless, FinFET technologies face many scaling challenges. For example, fin engineering (channel length, fine thickness, oxide thickness and balancing height) is important to minimize \(I_{\text{OFF}}\) and maximize \(I_{\text{ON}}\). PVT variation also exacerbates circuit degradation which makes the circuit inadequate for its initial purpose. A PVT variation causes a severe effect on the delay, leakage and performance of FinFET devices. Any variations in temperature affect the leakage current that leads to increases in energy–delay product (EDP) by up to 4X and 7X for full VDD operation and near-threshold voltage schemes, respectively (Turi and Delgado-Frias 2017). Researchers studied the 8T FinFET SRAM cell that reveals there are up to 42% of variations in EDP due to supply voltage variation. Temperature variability influences leakage current and the increase of up to 32X, and from the literature we noticed that a low-power inverter scheme is the highest rated 8T FinFET SRAM scheme (Turi and Delgado-Frias 2017). Fabrication of FinFET is a critical step for improvement in the performance of the device in deep submicron regime. Small variations during fabrication completely alter the circuit behavior, so we can conclude that nanoscale devices are becoming very sensitive to process variations. Figure 8.6 shows nominal PDP outcomes for standard cell gates under the WFF compared to mean values.

Fig. 8.6
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Nominal PDP outcomes for standard cell gates under the WFF compared to mean values

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AND4, half adder and full adder standard cells exhibit more sensitivity due to WFF variations and show deviations of 19.76, 10.33 and 35.36% above the nominal PDP value, respectively. INV, NAND2 and AOI21 standard cells are less sensitive to WFF deviations. Figure 8.7 indicates the differences in power, PDP and timing due to voltage fluctuations (Zimpeck et al. 2015). Supply voltage variations play a very crucial part in the performance of FinFET. Figure 8.7 shows the total power, timing and PDP values for a voltage range from 0.9 to 0.3 V.

Fig. 8.7
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Differences in timing, power and PDP due to voltage fluctuations

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NAND4, AND4 and NOR3 standard cells show about 70% of PDP reduction by using FinFET devices. The main drawback of voltage variations is timing violations. The total power consumption parameter is mainly affected by temperature variations that can increase power consumption 5X higher than the nominal value in case of high temperature (Zimpeck et al. 2015). We can examine that WFF can considerably influence leakage current of the FinFET from the above results.

Diverse transistor arrangements for the similar logic function can reveal the different electrical and physical characteristics under PVT variations. To mitigate the impact of PVT variations, complex cells can be implemented in various transistor arrangements that can provide the most suitable topology for evaluation. Different transistor arrangements show a distinct impact on gate variability and concluded that far topology is best for OAI211 and OAI221 complex gates (Zimpeck et al. 2018). PDP determines the impact of process variability on complex cell by evaluating the delay and power of various circuits under the influence of WFF variations. Close arrangement is better for remaining complex gate. Far topology having three or more inputs provides better performance but causes the power penalty, i.e., increasing the power consumption mean value. Table 8.1 shows the mean and standard deviation of power consumption, worst-case delay and PDP (Zimpeck et al. 2018).

Table 8.1 Mean and standard deviation of the power consumption, worst-case delay and PDP
Full size table

Impact of PVT variations on different transistor sizing techniques is also scrutinized in the previous literature in which transistor sizing techniques like optimized transistor sizing (OTS), logical effort (LE) and minimum transistor sizing (MTS) are largely utilized. LE-based technique cells exhibit the highest deviation in PDP. On the other hand, the OTS-based technique cells represent higher nominal values. Voltage variations mostly influence the OTS worst cases that cause maximum energy consumption. The impact of temperature variations is very less in OTS-based technique cells. LE technique shows the largest deviation. It is also important to consider environmental variation when choosing the appropriate approach for defining the correct transistor sizes for standard cell libraries, considering variability (Zimpeck et al. 2016).

The process variability will introduce a power deviation of up to 100 percent. RSNM shows about 20% variation under PV which is the worst case dramatically reduced cell noise robustness (Almeida et al. 2018). The author introduced FinFET CAM architecture focused on parasitic aware nature in Bhattacharya et al. (2015). All asymmetric gate work function shorted gate (ALL-ASG) bit cell was more superior to all shorted gate (ALL SG) and core ASG bit cells in terms of DC metrics. Leakage power assumes slightly greater significance with decreasing mismatch probability. When the BJT diode is replaced with FinFET diode, it shows the less voltage headroom and power dissipation (Prilenski and Mukund 2018). But, the biggest disadvantage of a FinFET diode is enlarged vulnerability to PV. The traditional method of estimating the leakage will greatly underrate the average leakage current by 43%, while the approach makes less error than 5% (Gu et al. 2008). The PV remains the main source of power and timing deviation in new technologies. CAD tools may play a significant role in assessing the impact of variability and reliability. Various tools like Cadence Virtuoso, Synopsys and ELDO simulator are the best way to implement any design philosophy (Alam 2008).

5 Conclusion

Scaling challenges of MOSFET technology such as SCE, an aging effect and a variability effect are becoming a barrier in the progress of VLSI technology; therefore, an appropriate alternative is the best way for evolution in VLSI technology. FinFET is the best option for substituting MOS technology because of better SCE controllability, lower leakage, perfect isolation and high driving capability. In this chapter, we outline various challenges faced by MOSFET technology and various factors which explicate the superiority of a FinFET as compared to MOS transistor. Researchers adopted various methodologies to mitigate the impact of PVT variations, but the PVT variation is still a dominant factor in FinFET devices, especially in deep submicron regimes. Nowadays, for better performance of FinFET, various techniques are necessitated to mitigate the impact of PVT variations.