Electromagnetic Noises

Abstract

VLSI chips in a practical system always experience interactions with surrounding electromagnetic (EM) environment. EM noise emitted from circuits can interfere with other circuits on the same chip or in another chip. Circuits and systems performance may be unpredictably and dynamically degraded by EM noise through its impacts on power and signal integrity.This chapter discusses the state-of-the-art knowledge and countermeasures associated with such unseen noise problems, covering noise emission, noise immunity, noise mitigation, tolerance, and integrity, all for the noise awareness in the design of dependable VLSI systems.An overview of EM compatibility (EMC) in CMOS digital integrated circuits (ICs) is given in Sect. 4.1, along with simulation and measurements of EM noise in a semiconductor IC chip. EM noise emission is explained as the interaction of dynamic power currents in ICs and parasitic impedance in a chip-package-board combined power delivery network (PDN).Electromagnetic susceptibility (EMS) of IC chips against incoming radio frequency high-power disturbance is discussed in Sect. 4.2. Static random access memory (SRAM) cores are chosen for demonstrating EMS evaluation based on direct power injection (IEC 62132-4). On-chip waveform monitoring provides useful means to analyze the mechanisms in which incoming RF power causes SRAM bit failures.On-chip power supply filtering adaptively suppresses EM noise due to PDN resonance, as a proactive measure for reducing electromagnetic interference (EMI) of IC chips, discussed in Sect. 4.3.The 4b/10b is a dependable line code with error correction ability. Responsive Link, which is a real-time communication link, can control the trade-off among the error correction strength, throughput, and latency, based on the communication environment such as inside a high-power robot operated by extremely high voltage (80 V) and huge current (200 A), by selecting a line code including the 4b/10b, a bit-level error correction code, and a block-level error correction code, as demonstrated in Sect. 4.4.

1 Electromagnetic Compatibility of CMOS ICs

Makoto Nagata, Kobe University

1.1 IC Chip Viewpoints

An electronic system experiences the irradiation of electromagnetic (EM) waves from environments, mostly unintentionally. Vehicles and aircrafts may approach EM sources such as radar stations on their road without knowing their exact entity on a map and be exposed to high-power and high-frequency EM waves. Mobile terminals transmit and receive radio frequency (RF) waves for their communications, while being interfered with other EM waves from other radio sources, each compliant to certain standards that may not be fully compatible with each other. Natural sparkles from phenomena such as lightning, ignition, electrostatic shocks, and others emit broadband EM waves spherically in any directions and interact in some degrees with operations of nearby electronic equipment. For an electronic system to properly and safely operate in the presence of those EM waves, it has to comply with electromagnetic compatibility (EMC) regulations . There are a variety of international standards and regulations in the field of EMC to be followed in a product development for worldwide markets. Designers have concerned EMC standard s set by IEC, ISO, IEEE, FCC, and CISPR. The regulation series of no. 10 (R10) by United Nations Economic Commission for Europe (UNECE) is well known in automotive segment. Those standards influence every building component of an electronic system, from materials, IC chips, packaging and assembly, to software and systems. The reader may be interested in the whole area of EMC and also even in the phenomenon of electrostatic discharge (ESD ) somewhat relevant to the IC chip level EMC as well. Those topics are to be covered in general EMC/ESD text books. We focus on EMC problems of integrated circuit (IC) chip in this chapter, to stay in the viewpoints of the dependability of VLSI systems. The following few sections will discuss the emission and interaction of EM waves on power delivery network s (PDNs) of an IC chip, in close relations with power integrity problems in a chip-package-board unified system. The general knowledge of EMC at the IC level can cover signal integrity problems as well, where signal routing and associated logic elements in a chip directly interact with EM waves. While the chapters are unfortunately limited in contents and spaces, the readers can expand their interests and insights to wider topics of IC chip EMC from modeling and analysis to measurements in state-of-the-art research publications. One of the well-known workshops in the field of IC chip EMC is IEEE EMC Compo [1].

Design for EMC is highly demanded for integrated circuit (IC) chips. An IC chip emits electromagnetic (EM) noise into space and/or receives EM noise from space, through its power supply lanes as illustrated in Fig. 4.1. An IC chip needs to guarantee the sufficiently low level of noise emission during its operation, not to disturb proper operation of surrounding equipment by electromagnetic interference (EMI). It is also requested to carry sufficient immunity against incoming noises from other equipment, not to degrade operating performance or even not to lose its functionality by electromagnetic susceptibility (EMS). The EMC requires the pair of such two-way characteristics to be simultaneously met.

Fig. 4.1

Electromagnetic noise emission and susceptibility of integrated circuit

An electronic system consists of many IC chips and therefore the remedies against EM noise coupling are necessary at the IC chip level, in order to make system operations robust and dependable against electromagnetic environment. Electronic control unit (ECU) as an automotive subsystem has stringent requirements of electromagnetic (EM) noise emission in a vehicle as being below the regulatory limits. Computing facilities like a cluster of servers also need to suppress EM noise from their high-frequency operation as well as large power current consumption. The EM noise of radio frequency (RF) chips may cause fatal interference with wireless communication. EM noise emission is closely related with power supply current of an IC chip, and that is time varying according to the operation of internal circuits and interacts with power line impedance that is frequency dependent.

The techniques to evaluate EMC include measurements and simulation. Regarding EMI, a near-field magnetic probe (equivalently a tiny coil) scans magnetic fields in a whole plane of printed circuit board (PCB), assembled with IC chips and other electronic components. This shows a map of EM radiation (emission) in strengths and also in frequencies as well. A capacitive sensor also complementarily evaluates local electric fields. While for EMS, an RF power can be intentionally applied to any pins of ICs or components on a PCB and then the tolerance (susceptibility) of system operations is evaluated. While those measurements can reveal EMC performance of a product, the simulation techniques are fundamental for the design of IC chips and electronic systems in assembly to comply with EMC standards and regulations.

A simulation technique of dynamic (AC) power supply current at an IC chip level is explained in the following subsections, where silicon examples of the measurements and analysis of EMI will be also given. It should be noted that the topics of EMS will be covered in the next chapter (Sect. 4.2). In addition, EMC suppressions (Sect. 4.3) and EMC solutions (Sect. 4.4) will also follow.

1.2 EMC Evaluation Using a Package-Board-Level Simulation

An IC chip of typically less than 5 mm in each side is assembled in a system board with the scale of a few centimeters, as in an example photo of Fig. 4.2 [2]. The AC components of power supply current are generated by circuits in operation, within a small area of silicon die. In contrast, a closed loop of entire power delivery includes the chip, system board, and power source, and forms a macroscopic antenna. The flow of AC power current essentially creates EM noise emission.

Fig. 4.2

IC chip and PC board [1] (copyright 2011 IEEE)

Co-simulation of the power current of an IC chip and the frequency domain response of on-chip and on-board integrated power delivery network (PDN), namely IC chip-package-board co-simulation , is a key element of system-level power noise analysis [2,3,4]. An equivalent circuit of Fig. 4.3 captures the AC power current consumption in a capacitor charging model [5, 6] and the AC impedance characteristics of the PDN in an S-parameter model. The capacitor charging and S-parameter models represent the active and passive portion of power noise analysis, respectively, and the entire equivalent circuit is simulated with a conventional SPICE simulator.

Fig. 4.3

On-chip and on-board integrated power noise co-simulation model

The equivalent circuit of Fig. 4.3 involves parasitic impedances of on- and off-chip parts of the PDN. The on-chip part includes full-chip power planes of power supply (V_DD) and ground (V_SS). The planes are modeled as resistive mesh networks with the resistance extracted from detailed layout data of the whole of the chip. The parasitic capacitance of an entire chip, C_die, couples the V_DD and V_SS planes. The power pins for connecting to off-chip parts of the PDN are also explicitly included. In addition, a silicon substrate can be involved in the computation of the V_SS resistive network, since substrate currents flow from V_SS lines of a digital circuit to multiple V_SS pins of peripheral I/O rings via p⁺ substrate contacts. These substrate connections in parallel effectively reduce V_SS impedance and also impact on power noise seen on the V_SS network.

The off-chip part attributes to a chip in assembly and a printed circuit board (PCB). A bonding wire is replaced by a series inductance for each connection of V_DD or V_SS pin on the chip and the corresponding metallic land on the PCB. Decoupling capacitor s (decap) are also inserted between V_DD trace and V_SS plane on the PCB, along with equivalent series inductance (ESL) as well as resistance (ESR). The transfer characteristics of PDN traces on a PCB are simulated by a conventional full-wave three-dimensional (3D) solver.

In the capacitor charging model of Fig. 4.4, the group of logic switching operation in a digital circuit that is considered approximately simultaneous, or happens within a narrow time slice, is substituted by a single capacitor charging process. The size of a capacitor is equivalent to the amount of charges to be drawn from an external power source during the corresponding time slice. The time-domain progress of power current is represented by the successive charging of such equivalent capacitors. The distribution of gate toggles is derived from gate-level simulation of the target circuit, including gate and wire delays extracted from the final physical layout. The equivalent capacitor is then calculated by slicing the distribution in every time interval. The time intervals of {t₁, t₂, …, t_n} can be empirically chosen like the 1/10 of a clock period. The amount of charges needs to be pre-characterized for each gate element of a given standard logic cell library.

Fig. 4.4

Capacitor charging (TSDPC) model [1] (copyright 2011 IEEE)

The results of simulations will be presented and compared with experiments in Sect. 4.1.4.

1.3 Test Structure for Power Noise Investigation

A generally applicable method to evaluate power noise emission of a VLSI chip is discussed in this section. The test structure of Fig. 4.5 features on-board AC power current measurements using a near-field magnetic probe , in accordance with IEC61967-1 [7] and IEC69197-6 [8], along with on-chip voltage monitoring on power nodes. A silicon chip fabricated in a 65 nm CMOS process embeds an array of loop shift registers (SR) of Fig. 4.6 as the source of power noise. This circuit primarily consists of a cascade of D-type flip flop (DFF) cells where a series of preregistered bits is sequentially rotated in the loop. It is regarded as a synchronous digital circuit having the shallowest logical depth and operating in a broad range of clock frequencies, F_clk. The power supply voltage is 1.2 V.

Fig. 4.5

Test structure for on-chip and on-board AC power noise measurements

Fig. 4.6

Loop shift register (SR) circuit [1] (copyright 2011 IEEE)

The test chip additionally includes an on-chip waveform monitor (OCM) of Fig. 4.7 to evaluate dynamic voltage variation on power lines in a circuit [9]. The capturer consists of a probing front end circuit (PFE) to sense the voltage variation at the point of probing, and the output voltage of PFE is in-place digitized with the help of on-chip reference voltage and sample timing generators. Power noise waveforms on V_DD and V_SS traces of the SR are acquired by the on-chip measurement. The voltage and timing resolutions can be adaptive and typically of the orders of 100 uV and 100 ps, respectively.

Fig. 4.7

On-chip waveform monitor (OCM) system

1.4 Power Noise Frequency Response

On-chip power noise waveform s are compared between simulations using the method described in Sect. 4.1.1 and measurements in Sect. 4.1.3. The results are exemplified in Fig. 4.8 for a single clock cycle of F_clk in SR operation at 10 MHz, comparing simulation and measurements. Power line traces on the PCB have options whether to include or exclude an on-board decap of C_decap = 1 µF between the chip and an external power source, as also shown in the figure. The co-simulation with the unified PDN and capacitor charging models adequately captures the frequency domain power noise response.

Fig. 4.8

On-chip power noise waveform in V_DD of SR, a without on-board decap and b with on-board decap. Power trace on PCB is also shown [6] (copyright 2012 IEICE)

The frequency response is mainly governed by the power line impedance. The V_DD impedance seen from the power source terminal of the PCB is shown in Figs. 4.9a and 4.10a, for with and without the decap, respectively. The V_DD impedance exhibits a series LCR resonance since the end of the trace is openly terminated with C_die. On the other hand, the V_DD impedance seen from on-chip circuits, or from the point of AC power current consumption, is shown in Figs. 4.9b and 4.10b. The V_DD trace is considered virtually AC grounded at the power source for AC power current, and hence its response seen from on-chip circuits experiences parallel resonance [10]. While the V_DD impedance is measurable with the case of series resonance, the parallel resonance is of prime interest in terms of power noise analysis.

Fig. 4.9

Frequency response of a PDN series impedance seen from power supply terminals and b PDN parallel impedance seen from circuits inside chip, without on-board decap [1] (copyright 2011 IEEE)

Fig. 4.10

Frequency response of a PDN series impedance seen from power supply terminals and b PDN parallel impedance seen from circuits inside chip, with on-board decap [1] (copyright 2011 IEEE)

The frequency components of power noise waveforms are compared in Fig. 4.11 both in simulation and measurements. It is obviously shown that the distribution of frequency components is strongly characterized by the parallel resonance. The frequency components with the significant magnitudes, as well as the width of frequency distribution, are in accordance with the resonance frequency F_res. The first resonance frequency approximately at 120 MHz comes mainly from C_die = 175 pF derived from layout parameters and L_wire of 10 nH from the typical length of bonding wires. The board capacitance, C_brd, is smaller than 5 pF and negligible. The inclusion of 1-µF decap significantly reduces the first resonance, while making the second one at approximately 200 MHz to be noticeable. The demonstrated chip-package-board combined PDN analysis will actualize intentional tuning of F_res for suppressing EM interference at the frequencies of interest.

Fig. 4.11

Frequency components of on-chip power noise with F_clk = 10 MHz, a without on-board decap and b with on-board decap [1] (copyright 2011 IEEE)

The co-simulation also predicts power current flowing on the PCB V_DD traces, which is associated with the measurement results with a near-field magnetic probing. The most significant frequency component of the AC power current is derived as the function of F_clk, as shown in Fig. 4.12. The largest AC power noise is found when the operation frequency is equal to the half F_res. This comes naturally from the fact that a clock distribution network of the SR consumes large portion of power current at every signal transition either in rise or fall direction. The EM noise emission from a digital IC chip can be computed with the combination of power current generation of circuits and antenna propagation through power supply traces.

Fig. 4.12

Most significant frequency component of power noise current flowing on-board V_DD trace by near-field magnetic probing, a without on-board decap and b with on-board decap [1] (copyright 2011 IEEE)

1.5 EMC Awareness in IC Chip Design

Power noise simulation provides the ways to evaluate dynamic power currents consumed by IC chips in time-domain operation and to estimate EM emissions in a frequency domain. This facilitates the design of an electronic system in compliance with EMC regulations. The accuracy of power noise simulation is governed by the underlined techniques to draw active and passive parts of a PDN in completing the design of a whole system, including chip-package-board interaction. There are generally conceived standard modeling technologies like chip power model (CPM) and associated broadband PDN models for this objective, created by and handled in commercially available electronic design automation (EDA) software. The on-chip waveform monitoring technique quantitatively evaluates the correlation between simulation and measurements of power currents and EM interferences in existing designs. This helps to set up a certified analysis flow against EMC problems for future developments.

This section studies mostly on EM noises around resonating frequencies inherent to a PDN with chip-package-board interaction, as the most fundamental cause of EMC problems. On the other hand, the high-frequency EM wave emissions due to clocking and associated synchronous signal transitions can also exist and potentially interfere with radio frequency circuits [11]. This is actively discussed in the research areas of signal and power integrity (not given in this section).

2 Electromagnetic Noise Immunity in Memory Circuits

Makoto Nagata, Kobe University

2.1 Susceptibility of IC Chip to EM Noise

An IC chip is potentially susceptible to EM noise, either internally through direct coupling of EM waves with on-chip circuits or externally by the interactions of EM waves with parasitic antennas on cables. In order to simplify and evaluate such the various origins of susceptibility problems in a consistent way, the world standardized methodology of measuring the susceptibility of an IC chip has been established [12]. The probability of erroneous operations of an IC chip is evaluated in response to incoming conductive radio frequency (RF) power, under the direct power injection (DPI) method. Figure 4.13 depicts the measurement setup. An RF signal at the frequency of F_rf from a signal generator (SG) is amplified (AMP) and then forwarded to a specified pin of an IC chip in a package. The net power, P_net, injected into the die is calculated from forward (P_fwd) and reflect (P_ref) power measured by power meters after a directional coupler, according to (4.2.1). A bias-T network is introduced at the point of injection of RF signal to properly supply DC voltage (e.g., V_DD) to the pin of interest.

Fig. 4.13

Direct RF power injection method [16] (copyright 2011 IEEE)

$$ P_{{\text{net}}} \, = \,P_{{\text{fwd}}} \, - \,P_{{\text{ref}}} $$

(4.2.1)

The IC chip under DPI can assert a special flag bit of “reset” or record the number of erroneous bits in data, by using watch dog or built-in self test (BIST) capability, respectively. The susceptibility of an IC chip is evaluated by the minimum net power in DPI to cause a certain probability of erroneous operations, P_min, as the frequency of F_RF.

In some reports, the larger P_min is measured for the higher F_rf in the medium range of RF frequencies (e.g., up to 500 MHz), suggesting the smaller susceptibility of integrated circuits to the higher frequency incoming noise [13]. The high-power RF with F_rf of 1 GHz or higher can create more complex responses and sometimes lead to catastrophic events, due mostly to transistor-level parasitic capacitive couplings between circuits.

It has been observed that a microprocessor in an electronic control unit (ECU) exhibits frequent unexpected transitions to the “reset” mode under DPI, with increasing P_min for higher F_rf. The variation of the delay time of a logic gate and signal chains also shows the similar response under DPI [14, 15]. On the other hand, this section focuses on the EM susceptibility (EMS) of static random access memory (SRAM) [16,17,18]. Since a binary digital value is carried by analog waveforms and processed in memory circuit operation, the voltage variations due to DPI will impact on digital results through analog response. The measurement-based approach using on-chip waveform monitoring (OCM) in this section will greatly help to probe the EMS of general digital ICs.

2.2 DPI on SRAM Core

The SRAM core is of prime interest in EMC of digitally controlled systems with high reliability, for such as automotive and industrial applications. This is because of its usage as critical data and program storage, and the substantial occupation of silicon areas in a system-on-chip (SoC) die for supporting high-computation capabilities. The design for EMC of SRAMs becomes more prerequisite for SoCs in many-core architectures and using more advanced low-voltage CMOS technologies.

The system diagram of Fig. 4.14 shows how DPI is used for evaluating the susceptibility of an SRAM core against EM noise, in combination with the memory BIST (MBIST) and on-chip waveform monitoring (OCM). The MBIST realizes the on-chip diagnosis of bitwise SRAM write/read operation. The MBIST generates word data with bit patterns like a checker board or alternate lines and writes the data in the SRAM core under test (CUT). Then, the MBIST reads all data out from the CUT and check the correctness of data in a bitwise manner. The write-in and read-out sequences are iterated (with bit patterns reversed in each sequence) and all the erroneous bits are cumulatively stored in the MBIST. Finally, the MBIST calculates the bit error rate (BER) as the average number of erroneous bits divided by the total number of bits. The location of erroneous bits in the memory cell array can also be drawn in an erroneous bit map. The MBIST can be programmed and its data can be accessed by external logic structures in field programmable gate array (FPGA) device.

Fig. 4.14

System diagram of susceptibility evaluation of SRAM core [18] (copyright 2015 IEEE)

When a single error is found in average among the BIST iterations, the BER is calculated to be 7.6e-6 for a 16 k byte SRAM core. The BER is evaluated under the DPI as a function of RF power, RF frequency, SRAM power supply voltage (V_ddm), and SRAM operation frequency (F_clk). Figure 4.15a demonstrates that the BER increases for increasing P_net of RF disturbance. It is also seen that a SRAM is more susceptible for smaller DC supply voltage of V_ddm. In addition to the conventional DPI, the OCM measures the sinusoidal voltage variations induced by the RF signal, at the power supply node of the SRAM core, as exhibited in Fig. 4.15b. The magnitude of voltage variation is derived as V_chip-pp from the on-chip waveform captured for each DPI condition. The minimum instantaneous voltage due to the variation is also measured as V_{ddm_min}. Since transistors in SRAM cells operate under source–drain voltage, it is better to interpret the relationship between the susceptibility of an SRAM core in the DPI with the voltage variables that are only measurable by the OCM. This is the extension of the DPI method toward the understanding of circuit-level interactions with the conductive RF power due to EM coupling. Again in Fig. 4.15a with dual x-axes, the BER monotonically increases for the larger V_chip-pp that is induced by the larger P_net. It is interesting to note that there is a certain threshold of V_chip-pp under which no single-bit failure is found during BIST iterations. This threshold voltage depends intrinsically on the design of an SRAM core and also the technology of transistors used.

Fig. 4.15

Measured BER versus P_net. On-chip voltage variation is also given

2.3 Frequency Response in DPI

The minimum RF power in DPI to cause a single-bit failure during BIST iterations is defined as P_{net_min}. It is measured as the function of F_rf for the 16 k byte SRAM core under operations with different F_clk as given in Fig. 4.16a. The larger P_{net_min} is measured for the higher F_rf. This is consistent with the general trend found in the reported DPI of integrated circuits [13,14,15] as addressed in Sect. 4.2.1. In response to the larger P_{net_min}, the supply voltage of SRAM cells experiences the higher drop of V_{ddm_min,} as measured in Fig. 4.16b by the OCM. The standard supply voltage of 1.5 V was given. The relation of P_{net_min} or V_{ddm_min} on F_rf is almost independent on the F_clk, showing that the EM susceptibility in the SRAM core is irrelevant to the relative phase difference between the RF sinusoids and the SRAM clock signal, or the relative timing difference between the voltage drop and SRAM operations.

Fig. 4.16

Frequency dependency of DPI; a BER versus P_{net_min} and b BER versus V_{ddm_min} [17] (copyright 2015 JSAP)

The V_ddm of SRAM cells is often internally isolated in an SRAM core from the other power domain of V_dd for the peripheral circuits of digital access control (e.g., address decoding) and analog signal processing (e.g., bit line voltage sensing and amplification), as depicted in the simplified power supply network of Fig. 4.17. This is mainly for the enhancement of static operation margins of an SRAM core, by intentionally introducing a slight DC voltage difference between V_ddm and V_dd or even by controlling back-gate voltage of transistors only in SRAM cells. On the other hand, the DPI may introduce the undesirable voltage difference between the supply voltages of SRAM core and SRAM periphery, and bring about the collapse of binary data. Since the power domains involve highly capacitive couplings due naturally to their very dense transistor placements as in Fig. 4.17, the higher frequency of DPI on V_ddm induces sinusoidal voltage variations even similarly on V_dd by the capacitive coupling and results in the reduced relative voltage difference between them. This is one of possible qualitative explanations for the insensitiveness of an SRAM core against the high-frequency DPI. Many other physical mechanisms can be simultaneously present regarding EM noise interactions, and advanced analysis methodologies are needed for thorough and quantitative understandings of EMS. The mitigation techniques will be also derived in conjunction with the design of power delivery network (PDN) in the next section.

Fig. 4.17

Capacitive coupling in SRAM core [16] (copyright 2011 IEEE)

3 Power Noise of IC Chips in Assembly and Its Mitigations

Makoto Nagata, Kobe University

3.1 IC Chips in Assembly

An integrated circuit (IC) chip is normally packaged and mounted on a printed circuit board (PCB) in its practical usage in applications. The IC chip-package-board interaction provides a decisive impact on the overall electromagnetic (EM) response of an IC chip in assembly, as discussed in Sects. 4.1 and 4.2. Here, it will be shown that the system-level power delivery network (PDN) exhibits strongly frequency dependent power line impedance that characterizes power noise seen at locations on a PCB and in an IC chip, and specially induces unacceptably large noise components at the frequencies of resonance. The property of PDN is passive and governs not only EM interference (EMI) but also EM susceptibility (EMS), namely outgoing as well as incoming EM noises in wide frequencies, respectively. This section focuses on an autonomous tuning technique of PDN impedance, potentially mitigating both EMI and EMS problems.

A system-level PDN is intentionally embedded with capacitors between V_DD and V_SS for sustaining power line impedance below a specified level in the frequency range of interest. A large capacitor on the order of µF is placed often around power source terminals on a PCB for suppressing low-frequency power noises. The other capacitors on the order of nF are at the sources of power noise (power current consumptions) within an IC chip for high-frequency ones. As demonstrated in Figs. 4.8, 4.9, and 4.10, such a decoupling capacitor (C_decap) effectively reduces power line impedance only within a certain range of frequency. This limitation comes inevitably from the parasitic effective inductance and resistance in series to the capacitor, L_ESL and R_ESL, respectively. A self-resonance occurs approximately at the frequency of F_res = 1/(2π√L_ESLC_decap) and the power line impedance enlarges for the frequency larger than F_res. A power noise waveform exhibits oscillation at F_res with excitations such as active circuit operations, while decaying with the approximate time constant of L_ESL/2R_ESL after the termination of circuit operation.

It is noted that the power line impedance is fixed after the assembly of an IC chip, and therefore there is a need of post-silicon manufacturing techniques to optimize power line impedance over the frequencies of interest. An IC chip-package-board co-analysis/co-simulation technology has been intensively developed as a tool used in search of remedy for this purpose by the community of IC manufacturers, application system producers, and EDA software vendors. This demands a chip-level equivalent model of PDN and an electrical model of a package lead frame as well, and is still under active discussions for generalization. Another approach is to provide a chip-level adaptability of on-chip PDN parameters for an IC chip in actual operation environment. Design examples will be discussed in this section.

3.2 Power Noise Mitigation by Evading PDN Resonance

A PDN exciter intentionally brings about the resonance in the PDN of interest of an SoC die in assembly, as illustrated in Fig. 4.18. The exciter induces a pulse-like power current in the PDN by transistor switches to connect V_DD and V_SS for a very short period of time. An on-chip waveform monitor (OCM) captures power noise waveforms after the excitation. The waveforms are postprocessed by an on-chip PDN analyzer for deriving electrical characteristics of the PDN.

Fig. 4.18

PDN system having a PDN exciter for in-place analysis of PDN resonance

The system-level construction of an IC chip using the PDN analyzer is given in Fig. 4.19 [9]. There are PDNs with different voltage domains for the SoC core (e.g., 1.2 V) and interface (I/F) core (e.g., 3.3 V) circuits. The SoC and I/F circuits are properly supplied with power while halted or in a reset mode to eliminate naturally continuous excitations in the background. The PDN with parasitic L, C, and R components suffers from oscillatory voltage variation with decaying its amplitude by time after this single excitation, as demonstrated in a typically measured waveform of Fig. 4.20. The analyzer determines the oscillating period of resonance (t_resonance) and the decay constant (t_decay) from the series of timings at maximum or minimum voltage and the decay in voltage (V_decay), respectively. The OCM functionality of Fig. 4.7 is enhanced with an on-chip monitor controller to execute automated sequences of the PDN excitation, waveform acquisition and analysis.

Fig. 4.19

Construction of system-on-chip embedding PDN analyzer and PDN exciter

Fig. 4.20

PDN resonance waveform and characterization [9] (copyright 2011 IEEE)

The periodical PDN excitation leads to intentionally stationary oscillation due to the PDN resonance . The peak-to-peak voltage of the oscillation is drawn against the frequency of excitation, from 50 to 200 MHz, as shown in Fig. 4.21. PDN oscillation exhibits a considerable increase when the excitation frequency matches the integer inverse of the resonance frequency, F_PDN = 1/t_resonance. This provides a scenario for an SoC die to autonomously search the resonating frequencies in its practical usage environment after assembly, with the support of enhanced OCM functionality, and also select the frequency of operation evading from the PDN resonance. The operating frequency of circuits, F_clk, can be chosen in this example such that it does not lie in the vicinity of F_PDN and its integer inverse frequencies, F_PDN/i (i = 1, 2, 3, …). This will avoid the enlargement of power noise due to the PDN resonance. The reduction of F_clk from the nominal operating frequency at 148 to 118 MHz −19%) results in a 55% decrease in the power noise amplitude, as shown in Fig. 4.21 (measured waveforms are also shown). Similarly, with the increase of F_clk to 197 MHz (+30%), the noise amplitude is reduced by 64%. The former is chosen under the constraints of power consumption while the latter under the performance. These frequencies are reasonably located at the mid-point of adjacent pairs of F_PDN/i and F_PDN/(i − 1) and can be computed during the on-chip PDN characterization.

Fig. 4.21

Measured V_pp of power noise in digital circuits versus operating frequency of F_clk [9] (copyright 2011 IEEE)

3.3 Power Noise Mitigation by Suppression of PDN Resonance

The peak height of power noise at the frequency of PDN resonance can be suppressed by a tunable notch filter, given in Fig. 4.22. The filter consists primarily of bonding wire inductance in a package and an on-chip configurable capacitor in series, as shown in Fig. 4.23 [19]. A programmable resister is also included. The capacitor uses the gate capacitance of metal-oxide-semiconductor (MOS) transistors. The number of effective transistors are set by forcing each gate electrode to the high (turn on) or the low (cut off) bias condition, according to the digital codes of C_code for capacitance. The coupled bonding wires effectively increase their inductance, owing to the flow of power supply current. The structure is essentially passive and avoids the increase of power current consumption associated with noise suppression, in contrast to the use of active circuits [20,21,22]. The effect of noise suppression is maximized by searching C_code of the filter in response to V_pp measured by the PDN analyzer. Another code of R_code for resistance is only used for the additional dumping that is needed in power noise waveforms. The power supply noise was on-chip measured as the voltage variation on V_DD at the location of the filter and the associated suppression is demonstrated in Fig. 4.24, achieving 43% reduction of the height of voltage noise peak.

Fig. 4.22

PDN system embedding tunable notch filter for power noise reduction

Fig. 4.23

Construction of tunable notch filter

Fig. 4.24

Measured power noise waveforms [19] (copyright 2014 IEEE)

The power noise mitigation techniques of Sects. 4.3.2 and 4.3.3 are evaluated by on-chip power noise waveforms. They are simultaneously effective for the EM noise on power traces of PCB, since their essential constructions remain to be a passive PDN network.

4 Responsive Link for Noise-Tolerant Real-Time Communications

Nobuyuki Yamasaki, Keio University

Yusuke Kumura, Keio University

Shuma Hagiwara, Keio University

Masayuki Inaba, The University of Tokyo

4.1 Noise-Tolerant Real-Time Communication

Recently, complex distributed control systems such as humanoid robots have appeared in various fields. In order to make the distributed control systems dependable, internode communication with real-time capability and dependability is crucial. Especially, noise tolerance is indispensable, since noise has a huge influence on communication quality. For example, our target system is driven by high voltage (80 V) and high current (200 A) that can generate huge noises. For noise-tolerant real-time communication, we have been researching and developing a communication standard, called Responsive Link [23] that can meet the requirements of real-time capability and noise tolerance. This chapter introduces brief introduction of Responsive Link and shows evaluations of the noise tolerance.

4.2 Responsive Link

A real-time network, guaranteeing communication deadlines, is now an indispensable element in distributed real-time systems. There are many communication standards for various applications, including Ethernet [24], IEEE 1394 [25], and USB [26].

Ethernet is a cheap and popular communication interface used by most PCs. When communication collisions occur, the packets are retransmitted, as CSMA/CD is used. Therefore, it is difficult to bound the worst case communication time.

IEEE 1394 enables isochronous data transfer among computers, peripherals, and consumer electronics products. IEEE 1394 has some problems as a real-time communication in distributed real-time systems. Error correction is not supported at the isochronous data transfer mode. The maximum node number is limited up to 63 nodes. All networks are reset in case of hot plug and play. Network topology is fixed (chain, star, and tree), and the loop topology is not allowed.

USB is widely used to connect peripherals to PCs so that various I/O devices can be easily connected to PCs. USB has also some problems as a real-time communication in distributed real-time systems. The maximum node number is limited up to 127 nodes. Network topology is fixed to the tree structure. The loop topology is not allowed. And the root controller is required.

Therefore, these communication standards are not suitable for distributed real-time systems, and hence new real-time communication standard is required.

Responsive Link is an internode communication standard (ISO/IEC 24740:2008) [27] that accommodates separated communication channels for events and data, preemptive packet overtaking and switching, and error correction for some purposes. Responsive Link is implemented on responsive multithreaded processor (RMT Processor) [28, 29] designed for distributed real-time systems. The detail of RMT processor is described in Chap. 9, Sect. 9.2.

4.2.1 Separation of Communication

There are two types of real-time communication: hard real-time communication and soft real-time communication. On one hand, hard real-time communication requires strict time constraints allowing no delay to deadline. Control systems require this type of communication, putting more emphasis on latency than throughput. On the other hand, soft real-time communication is more tolerant to delay, and requires higher bandwidth. For example, a multimedia system requires this type of communication, putting more emphasis on throughput than latency, because the amount of data processed is large and the latency is not severe in the system. There is a trade-off between throughput and communication delay in real-time communication, and requirements of hard and soft real-time applications including a degree of time constraints are different. Therefore, Responsive Link is designed to support both hard and soft real-time communication by physically separating communication lines: Event link and data link. Because it is difficult to build a hard real-time system by using conventional communication standards that share a single communication line for both data and events, making the estimation of the communication latency of events more difficult.

Communication line for hard real-time communication is called event link. The other communication line for soft real-time communication is called data link. These transmission lines are separated as shown in Fig. 4.25. The specification of Responsive Link connector is as follows:

Fig. 4.25

Interface of Responsive Link

• Tx Data+/Data−, which is a differential signal, transmits data packets.

• Rx Data+/Data−, which is a differential signal, receives data packets.

• Tx Event+/Event−, which is a differential signal, transmits event packets.

• Rx Event+/Event−, which is a differential signal, receives event packets.

The fixed size packet is desirable in order to estimate the latency accurately and make hardware simpler. On one hand, if the packet size becomes larger, the throughput becomes higher. However, the packet latency becomes longer. On the other hand, if the packet size becomes smaller, the packet latency becomes shorter, while the throughput becomes lower, because the overhead relatively increases. Considering this trade-off, on one hand, the packet size used in event link is small 16 bytes in order to shorten the communication latency. On the other hand, data link packet is larger 64 bytes to achieve higher throughput as shown in Fig. 4.26.

Fig. 4.26

Packet format in Responsive Link

4.2.2 Priority-Based Packet Overtaking

In the field of real-time task scheduling, preemptive context switching is required to process real-time tasks. In the same way, preemptive communication, a packet with higher priority overtakes other packets with lower priority, is required so that real-time scheduling algorithms can be applied to real-time communications. Therefore, priority-based packet preemption function is designed and implemented on Responsive Link.

Figure 4.27 shows a 5 by 5 Responsive Link switch. Port 0 is connected to a local device, such as the node processor, and Ports 1–4 are connected to external ports. A packet arriving at an input port without collision is transferred to an output port specified by the routing table. When a collision occurs, i.e., multiple packets request the same output port simultaneously, the packet with the higher priority is transmitted first and other packets are stored temporally in the overtaking buffer. A packet with higher priority overtakes the packets with lower priority at every hop of nodes.

Fig. 4.27

Network switch

The header of an arriving packet is stored in the overtaking buffer. Its output port(s) is/are looked up from the routing table, and each output port finds the packet with the highest priority. If a conflict occurs, packets with lower priority are stored in the overtaking buffer until packets with higher priority to be transmitted. In addition to the overtaking buffer, off-chip backed-up memory is designed and implemented to prevent packet overflow in the overtaking buffer. On one hand, when the entry of an overtaking buffer runs out, the lowest priority packet in the overtaking buffer is saved into the off-chip memory (DRAM) automatically. On the other hand, when the entry of the overtaking buffer becomes available, it restores the saved packets to the overtaking buffer in priority order. With this functionality, preemptive communication, existing real-time scheduling algorithms can be applied to real-time communication.

4.2.3 Priority-Based Routing

End-to-end connection can be established with Responsive Link by setting routing tables of all nodes along the path from a source node to a destination node. Responsive Link can connect up to $2^{32}$ nodes with an arbitrary network topology, and the supported priority level is 256.

Each node has a routing table to control the packet routing and the priority replacement function. Figure 4.28 shows the routing table of a network switch with five inputs and five outputs.

Fig. 4.28

Routing table

In addition to network address, priority bits in the packet are also used to match the routing table as shown in Fig. 4.29. Therefore, different route can be set to the same network address for different priorities. For example, detours and exclusive communication lines can be set. The route with priority “0” is used as the default route for the network address.

Fig. 4.29

Packet routing with priority

In addition, Responsive Link can accelerate and decelerate packets by changing the their priorities. The priority of a packet can be replaced with a new priority level at each node, and the new priority is used at next node. This packet control can be realized by setting the routing table appropriately by software.

4.2.4 Communication Speed and Adaptive Codecs

The link speed can be dynamically changed (800, 400, 200, 100, and 50 Mbaud). The Responsive Link’s communication latency per hop is 0.27 μs (800 Mbaud) to 76.8 μs (50 Mbaud), which satisfies the communication requirement (that is, less than 100 μs) even when several tens of controllers are connected. Responsive Link employs embedded clock serial communication. Also, multiple error detection and correction codes are employed to improve communication dependability. Appropriate code intensity and code rate can be selected as a function of given characteristic of transmission channel [29]. Internode communication is affected by the noise in the system. In order to improve the reliability in communication, Responsive Link supports any pair of ECC and line codes listed in Table 4.1. Responsive Link can dynamically configure any pair of ECC and line codes in response to the given priority and noise parameters. Basically, to configure a pair of ECC and line codes, we need a given environment’s bit error rate, the communication cycle and deadline, and the communication data rate. The software uses these parameters to select the optimal combination that satisfies the time constraints and sufficient noise tolerance.

Table 4.1 Error-Correcting Code (ECC) and line codes

4.3 Noise-Tolerant Real-Time Communication with Responsive Link

4.3.1 Evaluation of Noise-Tolerant Error Correction Code: 4b10b

In order to build a highly dependable distributed system with real-time communication, a data transmission error fatally impacts the system. It is required to guarantee the data to be transferred correctly by using error correction codes. There exists a trade-off of code intensity and throughput. Therefore, the system has to have transmission lines with the appropriate ECC and line code under given circumstances including the noise level and the importance of transferring data. There are several advantages to be able to select various combinations of the ECC and line code and switch the settings depending on the given variable circumstances.

With a conventional line code such as nonreturn-to-zero-inverted (NRZI) and 8b10b, transferred data can be detected as multiple bits error even if the actual data on the line has 1-bit error. Therefore, we designed a new line code with ECC, called 4b10b that has higher noise tolerance by embedding error correction functionality to line code itself. The 4b10b employs embedded clock signaling, DC balancing and error detection and correction. Other codecs do not support all these functions, especially pertaining to error correction. The 4b10b is the first codec (line code) with ECC to fulfill them simultaneously. Each 4-bit data is transformed into 10-bit data using the lookup table as shown in Table 4.2. The 4b10b fulfills embedded clock signaling by not having three consecutive bits of “0” or “1” in encoded 10-bit data and five consecutive bits when 1-bit error occurs. In addition, it maintains the number of “0” and “1” in the 10-bit data to be the same for DC balancing. The hamming distance among every encoded 10-bit data is longer than 3. When decoding, transferred 10-bit data is looked up in the table, and decoded with minimum distance decoding. Error correction is possible because transferred data with 1-bit error can be uniquely determined with minimum distance decoding. Data with 2-bit error cannot be uniquely mapped to the original code, so error correction is not possible, but error detection is possible. Transferred data with more than 2-bit error cannot be detected as error. The 4b10b line code has been standardized at IPSJ as IPSJ-TS 0015:2015 [30].

Table 4.2 4b10b translation table

Responsive Link supports Hamming code, BCH code, and Reed–Solomon code as error correction codes. For line code, NRZI with Bit Stuffing, 8b10b, and 4b10b that supports ECC can be selected.

4.3.2 Evaluation of Noise Tolerance with Responsive Link

In order to evaluate the noise tolerance of Responsive Link, we measured the packet error rate using the transmission lines with noise. Bit errors are defined as a bit inversion, and bit errors are inserted into the transmission packets. We generated random bit errors with the varying rate of error from the range 10⁻⁶ to 10⁻¹. The first 10 packets were transferred as warm-up, which we did not count in the results. And the next transferred 1,024 packets are measured and calculated as actual error.

We evaluated Responsive Link with a noise generator, constructing the environment with noise equivalent to an 80 V and 200 A motor driver. Dependable data communications in the highly stressed environment have been confirmed as shown in Fig. 4.30.

Fig. 4.30

Environment

Figure 4.31 shows the packet error rates of three combinations of codecs. The line code heavily affects the noise tolerance. There is a trade-off between the noise tolerance and coding rate, i.e., effective throughput. In order to take a balance of noise tolerance and throughput, the application can configure an appropriate pair of ECC and line codes according to the given system environment. HAM4b10b means a combination of Hamming error correction code and 4b10b line code, HAM8b10b means a combination of Hamming error correction code and 8b10b line code, and HAMNRZI means a combination of Hamming error correction code and NRZI line code. HAM4b10b with the largest ECC size has the lowest packet error rate in all codes. However, the throughput of HAM4b10b is the lowest due to the largest ECC size. Therefore, application developers can select and use these error correction codes and line codes with considering a trade-off between throughput and noise tolerance.

Fig. 4.31

Bit error rate

4.3.3 Noise Tolerance with Ferrite Core

Now the reinforcement technology to improve noise tolerance in Responsive Link is introduced. A ferrite core, which is a magnetic core, can help noise-tolerant real-time communication in Responsive Link. Figures 4.32 and 4.33 show examples of communication failure/success without/with a ferrite core. The yellow and purple waves are the differential signals of an event link measured by the single-end probe, which are noisy. Figures 4.32 and 4.33 measure communication signals at single edge trigger mode and at continuous auto run mode respectively. The blue wave is the same signal measured by the differential probe, which seems to be stable. In Fig. 4.32, the signal voltage sometimes becomes negative (under 0 V) by noise, and hence the communication becomes failure despite the differential communication line. In contrast, in Fig. 4.33, the signal voltage is always positive (over 0 V), and hence the communication is successful, thanks to the ferrite core.

Fig. 4.32

Communication failure without ferrite core

Fig. 4.33

Communication success with ferrite core