Circuit Analyses with Nullors

Abstract

This chapter describes the nullor-based modelling of active devices from the circuit level of abstraction. After a brief overview on the nullor concept and its properties, the modelling of active devices not only at the voltage-mode but also at the current-mode and the mixed-mode of operation from two-port and four-terminal network point of view are described in details. The circuit analysis with nullors and the topological approach for transfer function generation by two-graph tree enumeration as well are presented. The generalized topological formula with homogeneous parameters is proved for all the circuit functions, and a simple representation of the four types of controlled sources by admittances is proposed, that allows a uniform treatment of the entire circuit in terms of admittances. In order to implement the procedure, the rules to automatically generate the two graphs and to enumerate the common spanning trees are presented. Some simplifications in the circuit and in the two graph structure before tree generation and a graph representation on levels, improve the efficiency of the tree enumeration procedure. The original approach, in which each edge is labelled with an admittance term, could handle only one type of active element, namely VCCS (voltage controlled current source), but the method was further developed by many researchers for general linear circuits to include virtually all active elements. Some techniques to convert the CCVSs (current controlled voltage sources), VCVSs (voltage controlled voltage sources) and CCCSs (current controlled current sources) in equivalent schemes containing only VCCSs together with admittances and the inductance modelling proposed in the literature are discussed.

1 Introduction

According to the symbolic analysis principles, the Nodal Analysis Method (NAM) is restrictive because the admittance matrix must contain only the elements compatible with the Nodal Analysis (NA). The problem can be easily resolved through the Modified Nodal Analysis Method (MNAM), adding a row and a column for each element which is not compatible with the classic Nodal Analysis Method [1,2,3,4,5,6,7]. One of the problems generated by this kind of approach is related to the size of the admittance matrix. This matrix will become bigger, according to the structure of the circuit and types of its elements.

Regarding the models to be used in the analogue circuit analysis, the requirement of a high accuracy could lead to complicated calculations and then compact models are preferred mainly for the use of much more simple equations [3,4,5,6,7]. These models are more effective for the optimization of design and simulation time during the analysis process. From this point of view, the nullors proved already their efficiency in the active devices modelling. In the models based on nullors, the parasitic elements can be included to analyze their contribution to the analogue circuit response. All the four controlled sources can also be represented with equivalent circuits using nullor elements. Consequently, the nullors are very useful for the analogue circuits modelling because the circuit topology can be described using only two-terminal components like resistors, capacitors, nullators, norators, independent and controlled sources. Considering that the model should be developed in the simplest manner and the accuracy of the circuit behaviour simulation must be in acceptable limits, this chapter will show the problems related to the small-signal models of the active devices modelled with nullors.

The nullator is an ideal circuit with two terminals (Table 2.1a), which is characterized by null values for the current and voltage at the terminals. It has two equations: i = 0, v = 0.

Table 1 The behaviour of the nullators, norators and nullors

The norator is an ideal circuit with two terminals (Table 1b), which is characterized by random values for the current (i) and voltage (v) at the terminals. In other words, the norator does not have any equation. The current and the voltage values of this element are affected only by the external circuit connected to its terminals.

These two circuit elements can be used only in norator-nullator pairs called nullors (Table 1c), which has the number of equations equal to the number of gates. The nullor can be considered as an idealized operational amplifier, which has at the input gate null voltage and current and at the output gate an undetermined voltage and current (obtained by multiplying the null inputs by an infinite factor gain). In Fig. 1d, e is presented the symbol for the current (voltage) mirror.

Fig. 1

a Nullator symbol; b Norator symbol; c Nullor symbol; d Current mirror; e Voltage mirror

Techniques for the analysis of linear/linearized circuit have been performed using the nullator and norator as theoretical active devices, [6,7,8,9,10,11,12,13,14]. Tellegen was the first who presented the ideal operational amplifier theory and later, in 1964, Carlin considered nullators and norators as single active devices in the circuit analysis—called nullor [5]. He thought that these active devices cannot be built physically. Tellegen also took in consideration that these devices must be seen only as mathematical models without any physical support. Table 1 presents the behaviour of the nullators, norators and nullors from the point of view of the voltage, respectively of the current, in G^v—the voltage graph and, respectively Gⁱ—the current graph, [1,2,3,4,5,6,7,8,9].

The input port of the nullor is modelled by the nullator which is characterized by two equations:

$$ v_{ 1} = v_{ 2} = {\text{arbitrary}},\,i_{ 1} = i_{ 2} = 0. $$

(1)

So, the nullator is simultaneously an open-circuit in Gⁱ current graph and a short-circuit in G^v voltage graph. The output port of the nullor is modelled by the norator where both, the voltage and the current have arbitrary values:

$$ v_{ 1} \ne v_{ 2} = {\text{arbitrary}},\,\,i_{ 1} = i_{ 2} = {\text{arbitrary}} $$

(2)

With these properties the nullor is a two-port element accepted as a universal active element [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16, 30,31,32,33,34]. This concept means that the nullor along with capacitors and resistors can be used to design a maximum number of functions with the minimum number of active devices. If a suitable set of linear and nonlinear passive elements is available, then no active element other than nullors are needed to implement any linear or nonlinear circuit function. So nullators, norators, resistances, along with capacitances can synthesize a complete set of linear or linearized equations.

2 Nullor Equivalences

From the beginning, the nullor circuit has been considered very efficient for the analog circuit analysis, modelling and synthesis. Therefore, there are many records regarding methods and algorithms based on nullor circuits, used for the active devices analysis and modelling [19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34]. Because any analog network can be modelled with nullators, norators and impedances, it is useful to mention the equivalence between some connections. These are shown in Fig. 2. For instance, in Fig. 2a, a current cannot flow from a to b since the current through the nullator is zero, so a series connection of the nullator and norator is equivalent to an open-circuit. In Fig. 2b, the current can flow from a to b through the norator, also the voltage across a and b becomes zero according to the property of the nullator, so a parallel connection of the nullator and norator is equivalent to a short-circuit. The remaining connections have equivalences according to the nullator and norator i−v characteristics.

Fig. 2

Nullator and norator equivalences

In another approach, the nullors along with grounded resistors can be manipulated in order to obtain inverting properties, features that the nullator and the norator cannot model by themselves [30, 31]. The main purpose of the introduction of the inverting properties is that the behaviour of some active devices involves inverting the voltage and current input-signals. In this sense, the Current-Mirror (CM) and the Voltage-Mirror (VM), both as active devices, can perform this task and their behaviour also should be modelled with nullors, [30,31,32,33,34]. Thus, by manipulating the nullor along with grounded resistors, the behaviour of a CM or of a VM, both with ideal unity-gain can easily be obtained, as shown in Fig. 3, [1].

Fig. 3

Nullor and grounded resistor-based VM (a) and CM (b)

Therefore, by analyzing the equivalent circuits, one can see that the VM, shown in Fig. 3a, is characterized by:

$$ v_{ 2} = \, - v_{ 1} = {\text{ arbitrary}}, \,i_{ 1} = i_{ 2} = \, 0. $$

(3)

and the CM, shown in Fig. 2b, is characterized by:

$$ v_{2} \ne v_{1} = \, \text{arbitrary},\,i_{1} = i_{2} = \, \text{arbitrary} $$

(4)

At the end, the inverting behaviour of the nullator and norator is achieved. In [24, 31, 32], the nullor—based models of the VM and CM include parasitic elements. In the same manner as for the nullor, equivalences between the combinations of nullators, norators, CMs, VMs and impedances can be obtained. Note, however, that if v₁ or v₂ terminal from Fig. 3a is grounded and by applying the equivalences shown in Fig. 1, the VM is reduced to a nullator. In the same manner, if any terminal in Fig. 3b is grounded by applying the equivalences shown in Fig. 2, then a norator is obtained.

3 Loop Current Method for Circuits with Nullors

As it is well-known, the loop current method is based on introducing the loop currents as intermediary quantities which satisfy the first Kirchhoff’s current law (KCL) and which can be determined by applying the Kirchhoff’s voltage law (KVL) on the independent loops of the electric circuit.

Taking into account the definition of the nullator as a circuit element through which the current does not flow, it is useful and recommended to choose loop currents such that they do not flow through the branches that contain nullators. In order to respect such a condition, the branches containing the nullators should be eliminated by introducing an open-circuit between the terminals at which a nullator is connected. This leads to a decrease of the number of independent loops (l_i) with the nullator number (n _n )

$$ l_{i} = b - n + 1 - n_{n} , $$

(5)

where: b—is the number of the circuit branches and n—is the number of the circuit nodes.

Applying KVL on the independent loops l_i a system of independent equations results from which we further can determine the loop currents.

The branch currents are expressed as an algebraic sum of the loop currents that flow through the respective branch.

If the electric circuit contains current sources, the branches which contain such sources cannot belong to a tree; a single loop current will be chosen to flow through such branch. The loop current value will be given by the source current.

In order that the system of l_i equations does not contain as unknowns the norator voltages, the l_i independent loops must not contain branches with norators. The norator branches are replaced by open-circuits while the branches with nullators are kept.

The loop current equations corresponding to a number of l_i loops become:

$$ \sum\limits_{j = 1}^{{l_{i} }} {\left( {\sum\limits_{{h \in \left[ {l_{j} } \right] \cap \left[ {l_{k} } \right]}} {R_{h} } } \right)I_{{l_{j} }} } = \sum\limits_{{h \in \left[ {l_{k} } \right]}} {E_{h} } , $$

(6)

where: $I_{{l_{j} }}$—is the loop current corresponding to the l _j loop and $E_{h}$—is the e.m.f of b _h branch.

If we consider the current and voltage graphs with their loop-branch incidence matrices ${\mathbf{B}}^{i}$ and ${\mathbf{B}}^{v}$(see Table 1), then the matrix form of the loop current equations, [7, 9,10,11,12,13,14], can be written as follows:

$$ \left( {B^{v} R_{b} \left( {B^{i} } \right)^{\,t} } \right)I_{b}^{i} = B^{v} \left( {E_{b} + R_{b} J_{b} } \right), $$

(7)

where, for example, ${\mathbf{I}}_{b}^{i}$ (R _b ) is the loop current vector in the current graph Gⁱ (the diagonal matrix of the branch resistances).

Example 1

See (Figs. 4 and 5).

Fig. 4

Initial circuit to be analyzed using loop current method

Fig. 5

Choosing of the loop currents

The loop current equations are obtained by applying the KVL on the independent loops from the voltage graph (Fig. 6) and taking the currents from attached to the loops from the current graph (Fig. 5). Proceeding in this manner, it results the following system of Eqs. (8a) and (8b)

Fig. 6

Loops for KVL writing

$$ \left\{ \begin{aligned} & R_{3} \cdot I_{{l_{1} }} + R_{5} \cdot I_{{l_{1} }} + R_{4} \cdot I_{{l_{1} }} - R_{5} \cdot I_{{l_{2} }} = 0 \, \\ & R_{5} \cdot I_{{l_{2} }} + R_{2} \cdot I_{{l_{2} }} - R_{5} \cdot I_{{l_{1} }} = - E_{2} \, \\ \end{aligned} \right.. $$

(8a, b)

From Eq. 8b it results:

$$ I_{{l_{2} }} = \frac{{ - E_{2} + J_{1} \cdot R_{5} }}{{R_{2} + R_{5} }}. $$

(9)

From Eq. 8a it results:

$$ I_{{l_{3} }} = \frac{{ - J_{1} \cdot \left( {R_{3} + R_{5} } \right) + R_{5} \cdot \left( {\frac{{ - E_{2} + J_{1} \cdot R_{5} }}{{R_{2} + R_{5} }}} \right)}}{{R_{4} }}. $$

(10)

4 Nodal Analysis Method for Circuits with Nullors

The unknown variables of this method are represented by the n − 1 electric potentials corresponding to the circuit nodes, excepting the nth node whose potential is the reference potential and it is considered to be zero. These unknowns satisfy KVL for any circuit loop. The computation of these unknowns is based on KCL written in n − 1 nodes and on the generalized Ohm’s law to express each branch current depending on the node potentials.

The equations of the node potentials for the circuits containing nullators will have a different form taking into account that the voltage at the nullator terminals is equal to zero, which results in a decrease of the number of the unknown potentials (Fig. 7).

Fig. 7

The equations of the node potentials for the branches containing nullators

If the circuit contains norators, the norator currents should not be present in the system of equations. This is why we choose sections that do not include the branches with norators.

$$ \sum\limits_{j = 1}^{N - 1} {\left( {\sum\limits_{{h \in \left[ {l_{j} } \right] \cap \left[ {l_{k} } \right]}} {G_{h} } } \right)V_{j} } = - \sum\limits_{{h \in \left[ {l_{k} } \right]}} {\left( {J_{h} + \frac{{E_{h} }}{{R_{h} }}} \right)} . $$

(11)

Considering the current and voltage graphs with their reduced node-branch incidence matrices ${\mathbf{A}}^{i}$ and ${\mathbf{B}}^{v}$(see Table 1) the matrix form of the nodal equations, [7, 9,10,11,12,13,14], is:

$$ \left( {{\mathbf{A}}^{i} {\mathbf{G}}_{b} \left( {{\mathbf{A}}^{v} } \right)^{{\,{\text{t}}}} } \right){\mathbf{V}}_{n - 1}^{v} = - {\mathbf{A}}^{i} \left( {{\mathbf{G}}_{b} {\mathbf{E}}_{b} + {\mathbf{J}}_{b} } \right), $$

(12)

where, for example, ${\mathbf{V}}_{n - 1}^{v}$ (G _b ) is the potential vector of the n − 1 independent nodes from the voltage graph G^v (the diagonal matrix of the branch conductances).

Example 2

The nodal analysis method for the circuits containing nullors can be applied as follows: KCT is written in the independent nodes of the current graph and there are used the potentials associated to the n − 1 independent nodes from the voltage graph. Applying the Nodal analysis method, we obtain the following Eqs. (13)–(18) (Fig. 8):

Fig. 8

Initial circuit to be analyzed using Nodal Analysis Method

Appling the KCL in the node (n₁) it results:

$$ \frac{{V_{1} }}{{R_{3} }} = J_{1} . $$

(13)

According to the KCL on the cut-set (S₂) to obtain:

$$ \frac{{V_{2} }}{{R_{5} }} + \frac{{V_{2} }}{{R_{2} }} = - J_{1} - \frac{{E_{2} }}{{R_{2} }}. $$

(14)

From Eq. (13) it results:

$$ V_{1} = R_{3} \cdot J_{1} . $$

(15)

From (14) we can obtain:

$$ V_{2} = \frac{{R_{5} \cdot R_{2} \cdot \left( { - J_{1} - \frac{{E_{2} }}{{R_{2} }}} \right)}}{{R_{2} + R_{5} }} , $$

(16)

$$ I_{4} = \frac{{V_{2} - V_{1} }}{{R_{4} }} = \frac{{\frac{{R_{5} \cdot R_{2} \cdot \left( { - J_{1} - \frac{{E_{2} }}{{R_{2} }}} \right)}}{{R_{2} + R_{5} }} - R_{3} J_{1} }}{{R_{4} }} , $$

(17)

$$ I_{2} = \frac{{V_{2} - V_{4} + E_{2} }}{{R_{2} }} = \frac{{\frac{{R_{5} \cdot R_{2} \cdot \left( { - J_{1} - \frac{{E_{2} }}{{R_{2} }}} \right)}}{{R_{2} + R_{5} }} + E_{2} }}{{R_{2} }} . $$

(18)

The values obtained for $I_{2}$ and $I_{4}$ are the same as those obtained by using the loop method.

5 The Generalized Topological Formula for Transfer Function Generation by Two-Graph Tree Enumeration

5.1 Introduction

One of the most important approaches for nonreciprocal circuit analysis is the two-graph tree enumeration method, mainly due to Mayeda and Seshu [16]. The original approach, in which each edge is labelled with an admittance term, could handle only one type of active element, namely VCCS, but the method was further developed by many researchers for general linear circuits to include virtually all active elements. In [17] some techniques to convert the CCVSs, VCVSs and CCCSs in equivalent schemes containing only VCCSs and admittances are introduced, and some techniques to model an inductance proposed in the literature are discussed. The resulted models have a bigger number of branches in the two graphs and some supplementary nodes are introduced in the original circuit. The method based on a two-graph representation using a unity gyrator to model the non-admittance components was implemented [18] in order to obtain symbolic network function expressions in other terms than admittances. The price paid by all these approaches consists in the increase of the circuit complexity leading to a bigger number of common spanning trees.

Topological formulas for transfer functions of active networks using tree enumeration method have been derived firstly by Mayeda and Seshu, but their procedure for determining the sign factor is tedious. In [15] the main results in this direction up to that date are presented, and similar formulas are obtained while modelling all the controlled sources by equivalent schemes containing only two terminal elements and VCCSs. A sorting scheme is preferred to obtain symbolic network functions from the node determinant of an augmented network.

Based on the original concepts of the two-graph tree enumeration method a modelling technique of the four types of controlled sources has been elaborated and a topological formula with homogeneous parameters for the transfer admittance has been proved using the nodal approach [7]. Some innovative approaches to symbolic generation of the transfer functions have been developed: an algorithm using systematic loop opening and closing, a diakoptic approach, and a procedure based on graph decomposition on levels [7,8,9,10,11,12,13,14].

In this chapter, a set of rules for generating and using the two graphs is stated, and the generalization of the topological formula to generate all network functions is proved. These rules are applicable to a linear circuit containing: all four types of linear controlled sources, resistors, inductors, capacitors, nullors (for ideal opamps operating in the linear mode), and any multi-terminal or multiport circuit element having an equivalent scheme made up only by two-terminal elements and controlled sources. The generalized topological formula with homogeneous parameters that we propose to generate the transfer functions, can handle our models for the four types of controlled sources in a very efficient manner. Performing some reductions in the structure of the two graphs and representing them on levels we obtain an important improvement of the common tree enumeration process.

In Sect. 5.2 of this chapter we obtain the equivalent schemas in admittances that model in the two graphs the four types of controlled sources starting from the functional schemas with nullors. This representation makes possible the proof of the generalized topological formula with homogeneous parameters, valid for any transfer function of a lumped, linear and time-invariant circuit. Section 5.3 is dedicated to this proof. It is shown that the numerators of all the four types of transfer functions are identical and the treatment of the input/output ports according to the transfer function to be generated is given.

Section 5.4 is dedicated to a very efficient algorithm for tree enumeration in a graph represented on levels, which was implemented for network function generation, and Sect. 5.5 describes an efficient algorithm for sign factor generation. In Sect. 5.6 the rules for automatic generation of the network functions are introduced, and some techniques to increase the efficiency of the common spanning tree enumeration are discussed. The entire procedure of network function generation including simplification after generation is illustrated in Sect. 5.7.

5.2 Controlled Source Modelling in the Two Graphs

Consider two-port containing only linear passive two-terminal elements (resistors, capacitors, and inductors). It is well known that any circuit function can be written as a ratio of admittance polynomials using Kirchhoff’s topological formula. Each monomial in these polynomials corresponds to the admittance value of a tree. This property leads to a circuit graph whose edges have the admittances as their weights.

Kirchhoff’s type topological formulas have been developed by Mayeda and Seshu [16] for circuits containing linear passive two-terminal elements and voltage controlled current sources (VCCS) only. In these formulas each monomial corresponds to a common tree in the current graph Gⁱ and the voltage graph G^v in which each passive element is represented by an edge having the admittance as its weight; a VCCS is modelled by an edge with the same weight (the control admittance) but with different positions in the two graphs: the position of the controlling branch in Gⁱ and the position of the controlled branch in G^v. Gⁱ is used to write the Kirchhoff’s current law while G^v is used for the Kirchhoff’s voltage law. The constitutive equations of all circuit elements are written as relationships between the Gⁱ currents and G^v voltages.

Consider now a circuit containing two terminal elements and control sources of any type. In order to extend the abovementioned formulas to circuits with passive two-terminal elements and any type of controlled sources we build equivalent schemes of these sources using nullators and norators (nullors). A nullor equivalent scheme of a controlled source leads to its G^v and Gⁱ representations considering the following properties: from the current point of view the nullator is an open-circuit while the norator is a short-circuit, and from the voltage point of view the nullator is a short-circuit while the norator is an open-circuit.

Starting from the equivalent schemes with nullors in Fig. 9, the two graph models of the controlled sources using only two terminal admittances can be built as it is shown in Fig. 9. The parameters associated with the controlled and the controlling branches are presented in Table 3. The subscript C is used for the controlling branch and the subscript c for the controlled one.

Fig. 9

Controlled source modelling in the two graphs

As it is shown in Fig. 9 the four types of controlled sources are modelled in the two graphs as follows:

• CCVS is modelled by a branch having the transfer impedance subscript identical with the controlled branch $Z_{c} = Z_{cC}$, having as parameter $Y_{c} = 1/Z_{cC}$, and which takes distinct positions in the two graphs:

  • In Gⁱ it is connected to the controlling port, and it is oriented like the controlling current, the controlled branch being short-circuited;

  • In G^v this branch is connected to the controlled port, having the same direction with the voltage across this branch, the controlling branch being short-circuited.

In this way, a CCVS leads to a node contraction in each graph: in Gⁱ the nodes of the controlled branch coincide, while in G^v the nodes of the controlling branch coincide. In order to keep the numbering of nodes in natural order (that is especially useful in tree enumeration and in the sign factor computation), we reduce by one all node numbers greater than the number of the eliminated node.

For programming needs we keep in Gⁱ the node towards the voltage across the controlled branch is oriented (c’’), the other node number (c’) being allocated to the new node introduced to identify the controlling branch.

• VCCS is modelled by a branch having the transfer admittance subscript identical with the controlled branch $Y_{c} = Y_{cC}$, and which takes distinct positions in the two graphs:

  • In Gⁱ it is connected to the controlled port, and it is oriented like the controlled current, the controlling branch being open;

  • In G^v this branch is connected to the controlling port, having the same direction with the controlling voltage, the controlled branch being open.

This controlled source does not modify the number of the two graph nodes.

• A VCVS is equivalent with a VCCS $\left( {J_{m} = I_{m} = Y_{C} V_{C} } \right)$, in cascade with a CCVS with negative trans-impedance ($E_{c} = \left( { - Z_{c} } \right) \cdot \left( { - I_{m} } \right)$), and it is modelled

  • In G^v by two branches having the controlled branch number respectively that of the controlling branch, and the parameters presented in the Table 2; they are connected to the controlled branch, respectively to the controlling one, having the direction of the voltage across the controlled source, and respectively of the controlling voltage;

    Table 2 Controlled source equations

  • In Gⁱ the two branches are connected in series, having the nodes m’ and m” that are supplementary nodes. In order to keep the current graph node numbering, the number of the node m” will be that towards the voltage across the controlled branch is oriented (c”≡ m”); the number of the eliminated node (c’) will be attached to the other one (c’≡ m’). The controlled branch is oriented from c” to c’, and the controlling one from c’ to c”.

• A CCCS is equivalent with a CCVS connected in cascade with a VCCS, being modelled

  • In Gⁱ by two branches having the controlled branch number and respectively those of the controlling branch, and the parameters presented in the Table 2; these branches are connected to the controlled port, respectively to the controlling one, having the direction of the controlled current, respectively of the controlling one;

  • In G^v the two branches are connected in parallel and they have two common nodes, namely the node in which the controlled current goes in (c”) and the other one having the number of the node eliminated by short-circuiting of the controlling branch in G^v (C’). The two branches have the same direction in respect of their terminals.

Remarks

• 1. The other circuit elements (resistors, uncoupled inductors, capacitors) keep in the two graphs the same position as in the initial circuit, and are represented by their admittances.

• 2. The magnetic couplings are modelled by inductors and CCVSs [10].

• 3. The above modelling technique of the four controlled sources leads to two directed graphs having admittance branches only.

• 4. The two graphs have the same number of nodes, branches and loops. They differ only by the location of the controlling and controlled branches of the four types of controlled sources.

• 5. Because any branch contraction in the two graphs causes the elimination of one node, the number of nodes in Gⁱ and G^v is smaller than in the initial circuit with the number of CCVSs: $n_{{G^{i} }} = n_{{G^{v} }} = n - n_{CCVS}$.

In Table 3 is given a comparison with some reported techniques taking into account the number of branches used to model the circuit elements in both graphs and the supplementary node number.

Table 3 Comparison with some reported techniques

5.3 Generalized Topological Formula for Network Function Generation

Let us consider a linear nonreciprocal circuit (LNC) with null initial (i.c.) state and without independent sources and its associated model for operational calculus (Laplace). If we add to the input port an independent current source (Fig. 10), we can define the transfer impedance

Fig. 10

The LNC transfer impedance definition

$$ Z_{oi} \mathop = \limits^{d} \frac{{V_{o} }}{{J_{i} }}\left| \begin{aligned} \hfill \\ I_{o} = 0 \hfill \\ \end{aligned} \right. . $$

(19)

The nodal equations of the circuit take the matrix form:

$$ {\mathbf{Y}}_{n - 1} {\mathbf{V}}_{n - 1} = J_{i} , $$

(20)

where J _i can be expressed as

$$ J_{i} = Y\left( {V_{{o^{\prime } }} - V_{{o^{\prime \prime } }} } \right) , $$

(21)

with

$$ Y\mathop = \limits^{d} \frac{1}{{Z_{oi} }} . $$

(22)

The Eq. (21) is equivalent to the substitution of J _i by a VCCS. Substituting Eq. (21) in (20) and rearranging we obtain:

$$ {\mathbf{Y}}_{n - 1}^{'} {\mathbf{V}}_{n - 1} = 0 . $$

(23)

Consider the current and voltage graphs with their reduced node-branch incidence matrices ${\mathbf{A}}^{i}$ and ${\mathbf{A}}^{v}$.

Writing the Kirchhoff’s current law in the current graph we obtain:

$$ {\mathbf{A}}^{i} {\mathbf{I}}_{b}^{i} = 0 , $$

(24)

where the branch currents can be expressed as:

$$ {\mathbf{I}}_{b}^{i} = {\mathbf{Y}}_{b} {\mathbf{V}}_{b}^{v} . $$

(25)

The branch voltages in the voltage graph are:

$$ {\mathbf{V}}_{b}^{v} = ({\mathbf{A}}^{v} )^{\text{t}} {\mathbf{V}}_{n - 1}^{v} . $$

(26)

Substituting (26) in (25) and the last one in (24) we obtain:

$$ {\mathbf{A}}^{i} {\mathbf{Y}}_{b} ({\mathbf{A}}^{v} )^{\text{t}} {\mathbf{V}}_{n - 1}^{v} = 0 . $$

(27)

If we denote

$$ {\mathbf{A}}^{i} {\mathbf{Y}}_{b} ({\mathbf{A}}^{v} )^{\text{t}} = {\mathbf{Y}}_{n - 1}^{'} , $$

(28)

we obtain (23).

Because the system (27) contains linear dependent equations it follows:

$$ \det ({\mathbf{A}}^{i} {\mathbf{Y}}_{b} ({\mathbf{A}}^{v} )^{\text{t}} )= 0 . $$

(29)

Y _b being a symmetrical matrix, applying Binet-Cauchy theorem [6, 7] it results:

$$ \det ({\mathbf{A}}^{i} {\mathbf{Y}}_{b} ({\mathbf{A}}^{v} )^{\text{t}} )= \sum\limits_{k = 1}^{{n_{c} }} {\Delta_{k}^{i} \Delta_{k}^{v} P_{k} } , $$

(30)

where:$\Delta_{k}^{i} {\text{ and }}\Delta_{k}^{v}$ are determinants of order n − 1, made up with elements of Aⁱ and (A^v)^t matrices, taking the k-th group of n − 1 columns of Aⁱ and respectively n − 1 rows of (A^v)^t; P _k is the product of the operational branch admittances of Aⁱ columns, respectively of (A^v)^t rows that make up the k-th group; $n_{c} = C_{b}^{n - 1}$.

Because $\Delta_{k}^{i} {\text{ and }}\Delta_{k}^{v}$ are nonzero if and only if the k-th groups of branches corresponding to the n − 1 columns (rows) of Aⁱ ((A^v)^t) form trees in Gⁱ (G^v) [7], (30) may be written as:

$$ \det ({\mathbf{A}}^{i} {\mathbf{Y}}_{b} ({\mathbf{A}}^{v} )^{\text{t}} )= \sum\limits_{k = 1}^{{t_{c} }} {\Delta_{k}^{i} \Delta_{k}^{v} P_{k} } = \sum\limits_{k = 1}^{{t_{c} }} {\varepsilon_{k} P_{k} } = 0, $$

(31)

where: t _c is the total number of common trees of Gⁱ and G^v; P _k is the operational admittance product of the common tree T _k branches; ε _k represents the sign factor of the pair k of common trees.

In the expression (31) there are two kinds of terms: terms that contain the admittance Y, and the others that do not contain it, so that it follows:

$$ \det ({\mathbf{Y}}_{n - 1}^{'} )= \sum\limits_{k = 1}^{{t_{c} }} {\varepsilon_{k} P_{k} } = YT_{1} (s )+ T_{p} (s )= 0 , $$

(32)

where:

$$ T_{1} (s) = \sum\limits_{{k \in (T_{1c} )}} {\varepsilon_{k} t_{k} } , $$

(33)

$$ T_{p} \left( s \right) = \sum\limits_{{k \in (T_{pc} )}} {\varepsilon_{k} t_{k} } , $$

(34)

and $\varepsilon_{k} = \pm 1$—is the sign factor for each common spanning tree of the pairs ($G_{1}^{i}$,$G_{1}^{v}$), respectively ($G_{p}^{i}$,$G_{p}^{v}$), where $G_{1}^{i}$ ($G_{1}^{v}$) is the current (voltage) graph containing a unit weight branch at the input (output) port, and $G_{p}^{i}$ ($G_{p}^{v}$) represents the current (voltage) graph in which the input/output ports are in short-circuit or open according to the generated network function (see Table 4); $T_{1c} (T_{pc} )$ is the set of the common spanning trees of $G_{1}^{i}$,$G_{1}^{v}$ ($G_{p}^{i}$,$G_{p}^{v}$); $t_{k}$ is the product term equal to the product of branch admittances of the common spanning tree k.

Table 4 Treatment of the input/output ports

From Eq. (32) we obtain:

$$ Y = - \frac{{T_{p} \left( s \right)}}{{T_{1} \left( s \right)}}. $$

(35)

According to (22) it results that

$$ Z_{oi} = - \frac{{T_{1} \left( s \right)}}{{T_{p} \left( s \right)}}. $$

(36)

In the following we shall prove that, according to this approach, any transfer function of a lumped, linear, and time-invariant circuit, can be expressed in the form:

$$ F_{oi} = - \frac{{T_{1} \left( s \right)}}{{T_{p} \left( s \right)}}, $$

(37)

all the four transfer functions having the same numerator, the denominator being different depending on the way the input and the output ports of the circuit are treated. From the above it results that the problem of generating all product terms in the irreducible expression of the transfer function is converted to the problem of finding all common spanning trees of the two graphs.

Let us consider a two-port circuit, containing any linear multi-terminal circuit elements that have an equivalent scheme made up only by two-terminal circuit elements and controlled sources. Modelling the controlled sources in the two graphs by two terminal circuit elements as in Fig. 9 allows a uniform treatment in admittances of the entire linear nonreciprocal circuit (LNC).

• 1. Transfer impedance

Using the circuit represented in Fig. 11, we define its transfer impedance as

Fig. 11

The general scheme for transfer impedance definition

$$ Z_{oi}^{'} = \frac{{V_{o}^{'} }}{{J_{i} }}, $$

(38)

from which we can obtain the LNC transfer impedance:

$$ Z_{oi} = \mathop {\lim }\limits_{\begin{subarray}{l} Y_{i} \to 0 \\ Yo \to 0 \end{subarray} } Z_{oi}^{'} = - \frac{{T_{1} \left( s \right)}}{{T_{p} \left( s \right)}} , $$

(39)

where:

• T₁ is the sum of the algebraic values of the common trees in the graphs that contain the unity branch at the input (in Gⁱ) respectively at the output (in G^v);

• T _p is the sum of the algebraic values of the common trees in Gⁱ and G^v obtained by opening the input and output ports.

• 2. Transfer admittance

The transfer admittance of the circuit in Fig. 12 is:

Fig. 12

The general scheme for transfer admittance definition

$$ Y_{oi}^{'} = \frac{{I_{o}^{'} }}{{E_{i} }} = \frac{{Y_{o} V_{o}^{'} }}{{J_{i} /Y_{i} }} = Y_{i} Y_{o} Z_{oi}^{'} , $$

(40)

and those of the LNC results as:

$$ Y_{oi} = \mathop {\lim }\limits_{\begin{subarray}{l} Y_{i} \to \infty \\ Yo \to \infty \end{subarray} } Y_{oi}^{'} = \mathop {\lim }\limits_{\begin{subarray}{l} Y_{i} \to \infty \\ Yo \to \infty \end{subarray} } Y_{i} Y_{o} Z_{oi}^{'} . $$

(41)

Using the generalized Feussner formula for two branches we obtain:

$$ \begin{aligned} Y_{{oi}} = & \mathop {\lim }\limits_{\begin{subarray}{l} Y_{i} \to \infty \\ Yo \to \infty \end{subarray} } Y_{i} Y_{o} Z_{{oi}}^{'} = \\ = & - \mathop {\lim }\limits_{\begin{subarray}{l} Y_{i} \to \infty \\ Yo \to \infty \end{subarray} } Y_{i} Y_{o} \frac{{T_{1} }}{{Y_{i} Y_{o} T_{{Y_{{i,sc}} Y_{{o,sc}} }}^{'} + Y_{i} T_{{Y_{{i,sc}} Y_{{o,op}} }}^{'} + Y_{o} T_{{Y_{{i,op}} Y_{{o,sc}} }}^{'} + T_{{Y_{{i,op}} Y_{{o,op}} }}^{'} }} = \\ {\text{ }} = & - \frac{{T_{1} }}{{T_{{Y_{{i,sc}} Y_{{o,sc}} }}^{'} }} = - \frac{{T_{1} }}{{T_{p}^{Y} }}, \\ \end{aligned} $$

(42)

where: T₁ is the same as in the case of Z _oi , and $T_{p}^{Y} = T_{{Y_{i,sc} Y_{o,sc} }}^{'}$ is the sum of the algebraic values of the trees that are common to the Gⁱ and G^v obtained by short-circuiting the input and output ports.

• 3. Voltage Gain

  Using the circuit in Fig. 13 we define the voltage gain as:

  Fig. 13

  

  The general scheme for voltage gain definition

  $$ A_{oi}^{'} = \frac{{V_{o}^{'} }}{{E_{i} }} = \frac{{V_{o}^{'} }}{{J_{i} /Y_{i} }} = \frac{{Y_{i} V_{o}^{'} }}{{J_{i} }} = Y_{i} Z_{oi}^{'} , $$

  (43)

  from which we obtain the LNC transfer function

  $$ A_{oi} = \mathop {\lim }\limits_{\begin{subarray}{l} Y_{i} \to \infty \\ Yo \to 0 \end{subarray} } A_{oi}^{'} = \mathop {\lim }\limits_{\begin{subarray}{l} Y_{i} \to \infty \\ Yo \to 0 \end{subarray} } Y_{i} Z_{oi}^{'} . $$

  (44)

  Applying the generalized Feussner formula we obtain:

  $$ \begin{aligned} A_{oi} = & \mathop {\lim }\limits_{\begin{subarray}{l} Y_{i} \to \infty \\ Yo \to 0 \end{subarray} } Y_{i} Z_{oi}^{'} = \\ = & - \mathop {\lim }\limits_{\begin{subarray}{l} Y_{i} \to \infty \\ Yo \to 0 \end{subarray} } Y_{i} \frac{{T_{1} }}{{Y_{i} Y_{o} T_{{Y_{i,sc} Y_{o,sc} }}^{'} + Y_{i} T_{{Y_{i,sc} Y_{o,op} }}^{'} + Y_{o} T_{{Y_{i,op} Y_{o,sc} }}^{'} + T_{{Y_{i,op} Y_{o,op} }}^{'} }} = \\ \, = & - \frac{{T_{1} }}{{T_{{Y_{i,sc} Y_{o,op} }}^{'} }} = - \frac{{T_{1} }}{{T_{p}^{A} }}, \\ \end{aligned} $$

  (45)

  where: T₁ is the same as in the case of Z _oi and Y _oi , and $T_{p}^{A}$ is the sum of the algebraic values of the trees that are common to the Gⁱ and G^v obtained by short-circuiting the input port and opening the output port.

• 4. Current gain

  For the circuit in Fig. 14 the current gain is:

  Fig. 14

  

  The general scheme for current gain definition

  $$ B_{oi}^{'} = \frac{{I_{o}^{'} }}{{J_{i} }} = \frac{{Y_{o} V_{o}^{'} }}{{J_{i} }} = Y_{o} Z_{oi}^{'} , $$

  (46)

  and for the LNC we obtain

  $$ B_{oi} = \mathop {\lim }\limits_{\begin{subarray}{l} Y_{i} \to 0 \\ Y_{o} \to \infty \end{subarray} } B_{oi}^{'} = \mathop {\lim }\limits_{\begin{subarray}{l} Y_{i} \to 0 \\ Y_{o} \to \infty \end{subarray} } Y_{o} Z_{oi}^{'} , $$

  (47)

  that means

  $$ \begin{aligned} B_{oi} = & \mathop {\lim }\limits_{\begin{subarray}{l} Y_{i} \to 0 \\ Yo \to \infty \end{subarray} } Y_{o} Z_{oi}^{'} = \\ = & - \mathop {\lim }\limits_{\begin{subarray}{l} Y_{i} \to 0 \\ Yo \to \infty \end{subarray} } Y_{o} \frac{{T_{1} }}{{Y_{i} Y_{o} T_{{Y_{i,sc} Y_{o,sc} }}^{'} + Y_{i} T_{{Y_{i,sc} Y_{o,op} }}^{'} + Y_{o} T_{{Y_{i,op} Y_{o,sc} }}^{'} + T_{{Y_{i,op} Y_{o,op} }}^{'} }} = \\ \, = & - \frac{{T_{1} }}{{T_{{Y_{i,op} Y_{o,sc} }}^{'} }} = - \frac{{T_{1} }}{{T_{p}^{B} }}, \\ \end{aligned} $$

  (48)

  where: T₁ is the same as in the above three cases, and $T_{p}^{B}$ is the sum of the algebraic values of the trees that are common to the Gⁱ and G^v obtained by opening the input port and short-circuiting the output port.

From the above analysis, we can conclude that to obtain all the transfer functions the input/output ports must be treated as in Table 4.

For the automatic generation of the graphs $G_{1}^{i} {\text{ and }}G_{1}^{v}$ the input gate of the analyzed circuit is connected to a current source that is controlled by the output gate voltage, which has the transfer admittance equal to the unit [27]. According to the Sect. 5.2 it will be represented in the two graphs as in Fig. 15.

Fig. 15

Current and voltage graphs that contain the unit branch

5.4 Algorithm for Tree Enumeration in a Graph Represented on Levels

We have proved that the network functions generation by the topological method of tree enumeration, in the case of nonreciprocal circuits, means the generation of all common spanning trees. Since the number of graph trees increases rapidly with the graph size, a highly efficient algorithm is needed. This problem was widely studied and several algorithms of varying efficiency have been proposed in the literature. Ones of the well-known are Minty’s algorithm which has the complexity O(b + n+bt), and the algorithm due to Gabow and Myers having the complexity O(b + n+nt), where b is the number of branches, n is the number of graph nodes, and t is the number of spanning trees.

The most used is, however, Char’s algorithm, that some studies [23] show it to be superior to the other ones. This algorithm generates for the beginning an initial spanning tree which needs O(b + n) operations, and starting from this one it enumerates all the spanning trees of the graph. During this enumeration, the algorithm generates also certain sequences which are not trees, called non-tree sequences. The original algorithm has the complexity O(b + n+n(t + t₀)), where t₀ is the number of non-tree sequences.

An implementation, called MOD-CHAR, of Char’s spanning tree enumeration algorithm, introduces several heuristics for the selection of the initial spanning tree and for decreasing the number of the non-tree sequences. With these improvements for almost all graphs, the complexity of MOD-CHAR is O(nt) [21,22,23]. It seems that for large dense graphs the complexity of MOD-CHAR algorithm is O(t), being superior to Char’s original algorithm, while for sparse graphs, it seems that Char’s original implementation is superior to MOD-CHAR [22].

In the following we present an efficient algorithm for the enumeration of all the common spanning trees based on a representation on levels of the two graphs, and on a sequential computation (by substituting a branch in the previous common spanning tree), which has the complexity O(t) for all kinds of graphs [13].

Let us consider the connected graph represented in Fig. 16a, and described on levels as in Fig. 16b, where:

Fig. 16

Graph representation on levels

n, b, l—represent the number of nodes, branches, and levels, respectively;

b[i] = (xi, y _i )—is the branch i, connected between the nodes x _i and y _i ; the node set is ordered so that

• level (x _i ) ≤ level (y _i );

• ∀ 0 ≤ i ≤ b − 1, level (x _i ) ≤ level (x _i +1) and level (y _i ) ≤ level (y _i +1);

niv[j] is the first node of level j, with 0 ≤ j ≤ l;

bet[k] is the first branch which connects the levels k and k + 1, where 0 ≤ k≤ l − 1;

inter[m] is the first branch which connects two nodes from the level m, where 1 ≤ m ≤ l − 1;

The algorithm for tree enumeration is the following:

Remarks

• 1. The representation of any graph in level form is equivalent with node sorting. If a heap-sort procedure is used, the time complexity is O(blgb + nlgn) while using an array technique it will be O(2b + 2n) [12].

• 2. The algorithm does not generate any non-tree sequence.

• 3. Any branch that obeys the algorithm rules, when is introduced in the sequence, leads to a tree.

• 4. The time complexity of the tree enumeration algorithm is proportional to the number of trees, O(kt), where k is, statistically, about 1, when the time allocated for the level decomposition of the graph is neglected.

• 5. The space complexity is O(n + n²), when the necessary of memory for preserving the graph structure (which is insignificant) is neglected.

Testing the algorithm for many graphs, to make a comparison with Char’s algorithm, we obtained the results presented in Table 5, and in Fig. 17.

Table 5 Comparison between the proposed algorithm and Char’s algorithm

Fig. 17

Comparison with Char’s algorithm

We can see that the efficiency of our algorithm rises rapidly with the number of trees.

5.5 Algorithm for Sequential Generation of the Sign Factor

For all the terms of the numerator and of the denominator the sign factor must be computed. The sign of the tree admittance product can be found using Mayeda and Seshu’s algorithm [8] or performing a depth-first or breadth-first traversal on both the Gⁱ and G^v trees [2]. In [10, 11] an original method for the sign factor determination is presented. The tree admittance product sign $\varepsilon_{k}$ is defined as:

$$ \varepsilon_{k} = M_{{T_{k}^{i} }} \cdot M_{{T_{k}^{v} }} , $$

(49)

where $M_{{T_{k}^{i} }} ,M_{{T_{k}^{v} }}$ are major determinants from the branch-node incidence matrices Aⁱ and A^v corresponding to the common spanning trees $T_{k}^{i}$ and $T_{k}^{v}$, respectively. To describe the current (voltage) spanning tree $T_{k}^{i}$ ($T_{k}^{v}$) we use a matrix with two rows and n − 1 columns (n being the node number of the graph)—called the current (voltage) tree description matrix CTDM (VTDM). Each column of this matrix contains the initial node and the final node of the tree branch corresponding to this column. For example, the tree description matrix (TDM) corresponding to the spanning tree shown in Fig. 18 has the following form:

Fig. 18

Algorithm of the sign factor determination

$$ {\text{TDM}} = \left[ {\begin{array}{*{20}l} 1 \hfill & 2 \hfill & 4 \hfill & 4 \hfill & 6 \hfill & 7 \hfill & 5 \hfill & 6 \hfill \\ 2 \hfill & 4 \hfill & 3 \hfill & 6 \hfill & 7 \hfill & 5 \hfill & 8 \hfill & 9 \hfill \\ \end{array} } \right]. $$

(50)

The determinants $M_{{T_{k}^{i} }} {\text{ and }}M_{{T_{k}^{v} }}$ are computed by performing simple operations on the rows of the tree description matrices. In Fig. 18 is described the computing algorithm of the determinant $M_{T}$ corresponding to the spanning tree $T = \left\{ {b_{1} ,b_{2} ,b_{3} ,b_{4} ,b_{5} ,b_{6} ,b_{7} ,b_{8} } \right\}$.

Let B, N be two finite sets B, N ⊂ N. The directed graph is, by definition, the triplet $G = \left( {B,N,f} \right)$, in which $f:B \to N \times N$. Let $x = \left( {x_{1} ,x_{2} } \right)$ be an element of the set N × N. We define:

$$ p_{1} :N \times N \to N,\quad p_{1} \left( x \right) = x_{1} ;\quad p_{2} :N \times N \to N,\quad p_{2} \left( x \right) = x_{2} , $$

(51)

the projections of an element in N × N. Let $T = \left\{ {b_{1} ,b_{2} , \ldots ,b_{n - 1} } \right\}$, with $b_{j} \in B,\;1 \le j \le n - 1$, be a spanning tree and let

$$ {\mathbf{P}} = \left[ \begin{aligned} p_{1} \left( {f\left( {b_{1} } \right)} \right)\; \, p_{1} \left( {f\left( {b_{2} } \right)} \right)\; \ldots \;p_{1} \left( {f\left( {b_{n - 1} } \right)} \right) \hfill \\ p_{2} \left( {f\left( {b_{1} } \right)} \right)\; \, p_{2} \left( {f\left( {b_{2} } \right)} \right)\; \ldots \;p_{2} \left( {f\left( {b_{n - 1} } \right)} \right) \hfill \\ \end{aligned} \right], $$

(52)

be the matrix built with the rows 1 and 2 of TDM corresponding to the spanning tree T.

The algorithm for the determinant $M_{T}$ calculation has the following steps:

• 1. In the matrix P, we assign zero value to the node with the greatest index (e.g. n₉ in Fig. 18). In this way, we obtain a matrix which is denoted by P₀;

• 2. We are looking for the node which exists only once in the matrix P₀, beginning with the node having the smallest index. Let this be $n_{j} = p_{k} \left( {b_{j} } \right)$, with k = 1 or k = 2 (e.g. n₁ in Fig. 18);

• 3. We develop the determinant $M_{T}$ on the row corresponding to the node n _j , namely

  $$ M_{T} = \left( { - 1} \right)^{{n_{j} + j}} M_{T}^{j} , $$

  (53)

  if k = 1, and

  $$ M_{T} = \left( { - 1} \right)^{{n_{j} + j + 1}} M_{T}^{j} , $$

  (54)

  if k = 2, where j is the column of the matrix P₀ corresponding to the node n _j , and $M_{T}^{j}$ represents the determinant obtained from $M_{T}$ after the elimination of the row n _j and of the column j;

• 4. If the node number n _j , found in step 2, is less than the greatest node number in P₀ (if $n_{j} < n - 1$), then all elements of P₀ having the values greater than n _j are reduced by a unit, and all columns of the matrix P₀, which are on the right side of the column j, change the places with a column to the left side. Thus, we obtain a matrix P _m , $m \leftarrow m + 1$ (initially $m \leftarrow 0$), having the column number less than P₀ with a unit;

• 5. If $n_{j} \ge 1$ and if the column number of the matrix P _m is greater than one, go to step 2, where the matrix P _m takes the place of the matrix P₀. If the $n_{j} = 1$ and if the matrix P _m has a single column, the determinant $M_{T}^{j}$ is developed on the row corresponding to the node n₁ and go to step 6;

• 6. Check up if the exponent of $\left( { - 1} \right)$ is an even or odd number.

In order to reduce the time needed to generate the circuit functions, a very fast algorithm for calculating the sign factor was developed and implemented. It is based on sequential computation, because knowing the sign of a term we can find the sign of the following by performing simple elementary operations (permutations) in a vector with n elements, representing the number of the graph nodes. These permutations aim to preserve the summations between lines of the reduced node-branch incidence matrix, without having to store it in the memory.

The algorithm pseudocode has the following structure:

5.6 Automatic Generation of the Transfer Functions

As it has been shown in Sect. 5.6, in order to compute a transfer function, we have to use two pairs of graphs: $\left( {G_{1}^{i} ,G_{1}^{v} } \right)$, for the numerator product terms, and $\left( {G_{p}^{i} ,G_{p}^{v} } \right)$ (in accordance with Table 4), for the denominator product terms.

For the automatic generation of $\left( {G_{1}^{i} ,G_{1}^{v} } \right)$, we must connect at the input port of the circuit a VCCS having as controlling variable the output voltage, the transfer admittance being 1. For this source, the controlled branch number is 1, while the controlling branch number is 2 (Fig. 19, LNC—Linear Nonreciprocal Circuit).

Fig. 19

Automatic generation of $\left( {G_{1}^{i} ,G_{1}^{v} } \right)$ and $\left( {G_{p}^{i} ,G_{p}^{v} } \right)$

For the automatic generation of $\left( {G_{p}^{i} ,G_{p}^{v} } \right)$ we must connect at the input/output ports some ideal independent current sources having null currents and the last branch numbers: b − 1, respectively b (Fig. 19).

The algorithm for transfer impedance $Z_{oi}$ generation involves the following steps:

• 1. Gyrator circuits, voltage or current inverters, magnetic couplings, operational amplifiers and, in general, the multipole or multiport circuit elements contained in the analyzed circuit are replaced by equivalent schemes consisting of bipolar circuit elements and controlled sources only;

• 2. Controlled sources are simulated by passive two terminals elements that have distinct positions in Gⁱ and G^v graphs (see Table 4);

• 3. Graphs $G_{1}^{i} {\text{ and }}G_{1}^{v}$ are generated (Figs. 15a and b). In $G_{1}^{i}$ the branch with the unit weight connects the input port terminals, having the same sense as the sense of the input variable corresponding to the transfer function to be generated and the output port is open. In $G_{1}^{v}$, the branch with unit weight connects the output port terminals in the same sense as the sense of the output variable corresponding to the transfer function to be generated, the input port being open;

• 4. Graphs $G_{p}^{i} {\text{ and }}G_{p}^{v}$ are generated. In these graphs, the entry-exit ports are treated as in Table 4;

• 5. Determine the array of trees common to the graphs $G_{1}^{i} {\text{ and }}G_{1}^{v}$ that contains the branch with the unit weight

  $$ A_{1c} = A_{1}^{i} \cap A_{1}^{v} $$

  (55)

  where $A_{1}^{i} \, \left( {A_{1}^{v} } \right)$ is the array of the trees that contain the branch with the unit weight in the graph $G_{1}^{i} \, \left( {G_{1}^{v} } \right)$;

• 6. Determine the array of trees common to the graphs $G_{p}^{i} {\text{ and }}G_{p}^{v}$

  $$ A_{pc} = A_{p}^{i} \cap A_{p}^{v} , $$

  (56)

  with $A_{p}^{i} \, \left( {A_{p}^{v} } \right)$, the array of the trees from the graph $G_{p}^{i} \, \left( {G_{p}^{v} } \right)$;

• 7. For each pair of common trees k, generated at steps P5 or P6, the sign factor $\varepsilon_{k}$ is calculated with one of the algorithms described in Sect. 5;

• 8. Calculate the algebraic sum of tree values $\varepsilon_{k} P_{k}$ for the A_1c set and then for the set A _pc , P _k being the product of the weights (of operational admittances) of the common tree k branches;

• 9. With formula (37) calculate the transfer impedance $Z_{oi}$;

If the numerator and the denominator of the relation (37) are multiplied by the product of the operational impedances of all branches of the circuit, it results:

$$ Z_{ei} = - \frac{{C_{1} }}{{C_{p} }}, $$

(57)

where:

$$ C_{1} = \sum\limits_{{k \in C_{1c} }} {\varepsilon_{k} P_{ck} } , $$

(58)

is the algebraic sum of the values (in impedances) of the co-trees common to the graphs $G_{1}^{i} {\text{ and }}G_{1}^{v}$ corresponding to the common trees that contain the branch with the unit weight and:

$$ C_{p} = \sum\limits_{{k \in C_{pc} }} {\varepsilon_{k} P_{ck} ,} $$

(59)

is the algebraic sum of the values (in impedances) of the co-trees common to the graphs $G_{p}^{i} {\text{ and }}G_{p}^{v}$.

It is easily to show [14, 21] that formula (55) can be used to generate any circuit function corresponding to the input-output ports treated as in Table 4.

Therefore

$$ F_{oi} = - \frac{{C_{1} }}{{C_{p} }}, $$

(60)

where the function F _oi may be: the transfer impedance (either input or output), the transfer admittance (either input or output), the voltage transfer (gain) factor or the current transfer (gain) factor.

The algorithm for generating any of the above mentioned circuit functions is identical to the one presented for the transfer impedance $Z_{oi}$, the only difference being the treatment of the input-output ports (Table 4). To define input impedance (admittance), the input-output structure of the port is defined in Fig. 20a, b) by using a passive linear circuit (PLC). Analog is defined also the input-output structure of the two-port circuit for the calculation of the output impedance (the output admittance).

Fig. 20

The input-output structure of the two-port circuit for the calculation of the input impedance (a) and input admittance (b)

Before generating the transfer function in symbolic form, by tree enumeration in the two graphs, we must do some simplifications either in the circuit or in the structure of the two graphs called approximation-before-computation (ABC).

Firstly, for each parameter x, we perform a numerical computation of the transfer function sensitivity in the frequency range of interest.

This information could give us the reason to eliminate some branches either by element removal or by contraction of its terminal nodes that simplify the circuit structure. In order to control the accuracy of the computational process, we have to evaluate the errors in the transfer function magnitude and in the transfer function argument due to these operations in the frequency range of interest. Once the circuit structure was simplified, we can generate the two pairs of graphs: $\left( {G_{1}^{i} ,G_{1}^{v} } \right)$ and $\left( {G_{p}^{i} ,G_{p}^{v} } \right)$. In order to simplify the generation of all their common spanning trees, we perform some operations in the structure of these graphs, namely:

• Contraction of the unity weight branches;

• Substitution of the parallel branches in these graphs by an equivalent branch having the admittance equal to the sum of the parallel admittances;

• Contraction of all branches having a node of degree one.

After the generation of the spanning trees in the reduced graphs, we must add successively all the branches eliminated in the first step. This procedure increases the enumeration efficiency of the common spanning tree in the two pairs of graphs—$\left( {G_{1}^{i} ,G_{1}^{v} } \right)$, and $\left( {G_{p}^{i} ,G_{p}^{v} } \right)$.

To obtain the symbolic transfer function in a form to be easily interpreted, two approximation strategies are possible: approximation-during-computation (ADC) that produces the approximate expression without knowledge of the exact symbolic expression, and approximation-after-computation (AAC) that firstly generates the exact symbolic expression and operating on it produces an approximated one. The simplified form can be obtained because only a small number of the terms in the irreducible expanded expression of the transfer function have an important contribution in the numerator or in the denominator value. Of course, the most efficient method is to generate only the significant common trees (whose tree admittance value is not negligible) in an ADC process. To this end the common spanning trees must be generated in decreasing order of magnitude until the generated set is a good approximation of the exact network function value. Also, the generation of the common spanning trees in decreasing order of magnitude must be performed for each frequency of interest. Some techniques for ADC were reported [16, 23,24,25,26], based on a sensitivity simplification scheme, a 2-, respectively 3-matroid-intersection algorithm and on the determinant decision diagram (DDD) representation of the system determinant. Although it is not easy to compare the implementations of these algorithms because of the different simplification before generation performed, and because of the different error criteria, it seems [24] that ADC based on DDD yields better results concerning the time needed to generate a term in comparison with the other techniques.

In this chapter, an AAC procedure to obtain a network function in reduced symbolic form is adopted. To this end the numerator and the denominator expressions must be ordered in the decreasing order of the complex frequency powers. The coefficients of each complex frequency power must be ordered in the decreasing order of their values as well, and then the terms with the smallest value will be eliminated one by one if the magnitude and phase errors are kept within imposed limits in the frequency range of interest.

A very fast program for the network function generation in reduced symbolic form has been obtained by implementing the modelling technique of the controlled sources associated with the generalized topological formula and with the algorithm for common tree enumeration and sign factor computation.

5.7 Description of the Software Application SATE—Symbolic Analisys by Trees Enumeration

The symbolic generation algorithm of circuit functions for analogue linear and/or nonlinear (piecewise-linear approximation) circuits described in Sect. 5.6 have been implemented in a program called SATE—Simbolic Analysis by Tree Enumeration [28]. Starting from the description of the circuit through a netlist input file (cir. file extension), SATE generates symbolically, partial symbolically or numerically form any circuit function with respect to the user-specified input/output ports for the linear and/or non-linear (piecewise-linear approximation around a point of operation) electrical circuits.

The input data for the software application are:

• nnode, nb, pulsation

where: nnode—is the number of circuit nodes, nb—is the branch number, and pulsation (angular frequency) is the pulsation value.

Follows a set of nb lines describing the branches of the circuit. The circuit elements are assigned as type numbers: 1—for resistors; 2—for capacitors; 3—for inductors; 8—for controlled sources e _c (i _C ); 9—for controlled sources j _c (v _C ); 10—for controlled sources e _c (v _C ); 11—for controlled sources j _c (i _C ) and 12—for the description of input-output ports.

For RLC circuit passive elements, the description statement has the form:

• element_type parameter_real_value initial_node final_node

For a controlled source, the description statement has the following structure:

• source_type parameter_real_value parameter_imaginary_value initial_node_c final_node_c initial_node_C final_node_C

where

initial_node_c final_node_c (initial_node_C final_node_C) represent the initial and final nodes for the controlled branch (controlling branch).

The last line of the input file describes the input/output ports and it has the following format:

• 12 initial_node_i final_node_i initial_node_o final_node_o

Remarks

• 1. The program gives to the branches numbers from 0 to b;

• 2. The last numbered branch, corresponding to the last line in the input file list, represents the branch weighting 1 in the current graph $G_{1}^{i}$ and in the voltage graph $G_{1}^{v}$;

• 3. In the case of the current-controlled sources, e _c (i _C ) and j _c (i _C ), the controlling ports are simulated by resistors with a very low resistance value (<10⁻⁸Ω);

• 4. In the case of the homogeneous controlled sources (e(v) and j(i)), the program assigns two branches to each source (in the following sequence: the controlled branch, the controlling branch), taking into account the modelling of these sources in the current graph or the voltage graph [20, 27]. Parameters corresponding to the two branches are assigned as follows:

  $A_{j\_k} = \frac{{Y_{k} }}{{Y_{j} }}$, where Y _k  = 1 S and $Y_{j} = \frac{1}{{A_{j\_k} }}$, for the source e _c (v _C ),

  $B_{j\_k} = \frac{{Y_{j} }}{{Y_{k} }}$, where Y _k  = 1 S and $Y_{j} = B_{j\_k}$, for the source j _c (i _C );

• 5. Magnetically coupled inductors are simulated by current-controlled voltage sources [20, 27, 28].

The main program compute.bat coordinates the entire process of generating the circuit function by successively calling the following subprograms:

• cv_graph.exe—it determines the current and voltage graphs;

• tree.exe—it generates the trees common to the two graphs;

• comp_fix.exe—it calculates the numerator and denominator terms of the circuit function;

• getfunc.exe—it factories the numerator and denominator expressions according to the chosen parameter;

• draw.exe—it draws the amplitude–frequency and phase–frequency characteristics of the generated circuit function.

The SATE program command line is:

compute input_file_name x

where:

• input_file_name—is the input file name with the extension cir (on the call the file extension is not written)

• and x represents the type of the circuit function that will be generated, as follows:

  • 1—the transfer impedance $Z_{ei} \left( s \right)$;

  • 2—the transfer admittance $Y_{ei} \left( s \right)$;

  • 3—the voltage transfer (gain) factor $A_{ei} \left( s \right)$;

  • 4—the current transfer (gain) factor $B_{ei} \left( s \right)$.

The SATE program generates the following output files:

• file_name.gr1—it contains the required information about the current graph;

• file_name.gr(x + 1)—it contains the required information about the voltage graph;

• file_name.ar1—it symbolically displays the numerator of the circuit function (A₁ from formula (19));

• file_name.ar(x + 1)—it symbolically displays the denominator of the circuit function (A _p from formula (19));

• a file containing numeric information about the value of the circuit function: the real part, the imaginary part, the module and the argument.

6 Examples

Example 3

Let us consider the linear circuit with lumped parameters represented in Fig. 21a. We want to determine the operational transfer admittance $Y_{oi}$ from the input port i’–i” to the output port o’–o”, assuming that all the other parameters of the circuit are known.

Fig. 21

A linear circuit and its pairs of graphs $G_{1}^{i} {\text{ and }}G_{1}^{v}$, respectively $G_{p}^{i} {\text{ and }}G_{p}^{v} `$

In Fig. 21, additional sources were also represented J₁ = 1.V₂, J₁₃ = 0A and J₁₄ = 0A, which aim to facilitate the automatic generation of graphs $G_{1}^{i} , { }G_{1}^{v}$ (source J₁ = 1.V₂) and $G_{p}^{i} , { }G_{p}^{v}$ (sources J₁₃ = 0A and J₁₄ = 0A). The numbering of additional sources was done as indicated above.

In Fig. 21b–e the graphs $G_{1}^{i}$ and $G_{1}^{v}$ ($G_{p}^{i}$ and $G_{p}^{v}$) are represented. The loops resulting by connecting in short-circuit of certain pairs of nodes in the graphs $G_{1}^{i} ,G_{1}^{v} ,G_{p}^{i}$ and $G_{p}^{v}$ have not been drawn in Fig. 21b–e (the branches of these loops cannot belong to the trees of these graphs).

The set of trees common to the graphs $G_{1}^{i} {\text{ and }}G_{1}^{v}$ (Figs. 21b and c), which contains the branch $1_{i} {\text{ in }}G_{1}^{i} {\text{ and, respectively, branch }}1_{o} {\text{ in }}G_{1}^{v} \,$ is:

$$ A_{1c} = \left\{ {\left( {1_{i} ,6,9,12 ;1_{o} ,6,9,12} \right),\left( {1_{i} ,4,10,11 ;1_{o} ,4,10,11} \right)} \right\}. $$

(61)

The set of trees common to the graphs $G_{p}^{i} {\text{ and }}G_{p}^{v}$ (Figs. 21d and e) has the following structure:

$$ A_{pc} = \left\{ {\left( {9,12} \right) ;\left( {10,12} \right)} \right\} , $$

(62)

Applying the above algorithm we obtain:

$$ Y_{oi} = \frac{{G_{6} G_{9} G_{12} + G_{4} G_{10} G_{11} }}{{\left( {G_{9} + G_{10} } \right)G_{12} }} $$

(63)

or

$$ Y_{oi} = \frac{{R_{4} R_{10} R_{11} + R_{6} R_{9} R_{12} }}{{R_{4} R_{6} R_{11} \left( {R_{9} + R_{10} } \right)}}. $$

(64)

Expressions (61) and (62) have been compared with those obtained with the programs TFSYG—Transfer Function SYmbolic Generation and CSAP—Circuit Symbolic Analysis Program, [28, 29], and it has been observed that these are identical.

Remarks

• 1. The trees common to the graphs $G_{1}^{i} {\text{ and }}G_{1}^{v}$, that contain the common branch of weight 1, are identical with the trees common to the graphs $G_{{1,1_{i,sc} }}^{i} {\text{ and }}G_{{1,1_{o,sc} }}^{v}$, obtained from the graphs $G_{1}^{i} {\text{ and }}G_{1}^{v}$, in which the branches 1 _i and 1 _o are short-circuited.

• 2. In the case of the nonlinear circuits, any of the four transfer functions of the circuit can be calculated with formula (35) or (58), at every time moment t_n+1 = t _n  + 1, by making the circuit passive and by linearization around the operating point at this time moment.

Example 4

Let be the small signal equivalent circuit of a three-stage CMOS transistor amplifier, represented in Fig. 22. The voltage transfer (gain) factor has to be generated symbolically, in relation to the input-output ports, 1–5 and 4–5, respectively.

Fig. 22

Equivalent scheme of a small signal amplifier

Using the algorithm based on the graph decomposition on levels, respectively of the SATE (Symbolic Analysis by Tree Enumeration) software [14, 21], we can proceed as follows:

• 1. The input file, ex2.cir, has to be edited with the following structure:

  • 5 13 314.00000000000000E + 0001 (nodes number, branches number, pulsation)

  • 1 1000.0 1 5 (branch type, parameter value, initial node, final node)

  • 9 0.001 0.0 2 5 1 5 (9-source j(u), real value, imaginary value, initial node, final node for the controlled variable, initial node, final node for the controlling variable)

  • 1 1000.0 2 5

  • 2 0.1e−08 2 5

  • 9 0.001 0.0 3 5 2 5

  • 1 1000.0 3 5

  • 2 0.1e−08 3 5

  • 9 0.001 0.0 4 5 3 5

  • 1 20000.0 4 5

  • 2 0.1e−08 4 5

  • 2 0.1e−08 2 4

  • 2 0.1e−08 3 4

  • 12 1 5 4 5 (input and output ports)

• 1. After SATE program running, the following results are obtained:

Terms of the circuit function counter
Sign factor	The value of common trees (in admittances)
1	$C_{7} C_{11} G_{2\_1} s^{2}$
1	$G_{2\_1} G_{5\_3} G_{8\_6}$
−1	$C_{12} G_{5\_3} G_{2\_1} s$
1	$C_{11} C_{12} G_{2\_1} s^{2}$
1	$C_{11} G_{6} G_{2\_1} s$

Terms of the circuit function denominator
Sign factor	The value of common trees (in admittances)	Sign factor	The value of common trees (in admittances)
1	$C_{11} G_{3} G_{6} s$	1	$C_{7} C_{10} C_{11} s^{3}$
1	$C_{4} C_{11} G_{6} s^{2}$	1	$C_{7} C_{12} G_{3} s^{2}$
1	$G_{3} G_{6} G_{9}$	1	$C_{4} C_{7} C_{12} s^{3}$
1	$C_{4} G_{6} G_{9} s$	1	$C_{7} C_{11} C_{12} s^{3}$
1	$C_{11} G_{6} G_{9} s$	−1	$G_{5\_3} G_{8\_6} C_{11} s$
1	$C_{10} G_{3} G_{6} s$	1	$C_{11} C_{12} G_{5\_3} s^{2}$
1	$C_{4} C_{10} G_{6} s^{2}$	1	$C_{11} C_{12} G_{3} s^{2}$
1	$C_{10} C_{11} G_{6} s^{2}$	1	$C_{4} C_{11} C_{12} s^{3}$
1	$C_{12} G_{3} G_{6} s$	1	$C_{12} G_{3} G_{8\_6} s$
1	$C_{4} C_{12} G_{6} s^{2}$	1	$C_{4} C_{12} G_{8\_6} s^{2}$
1	$C_{11} C_{11} G_{6} s^{2}$	1	$C_{11} C_{12} G_{8\_6} s^{2}$
1	$C_{4} C_{7} G_{3} s^{2}$	1	$C_{12} G_{3} G_{9} s$
1	$C_{4} C_{7} C_{11} s^{3}$	1	$C_{4} C_{12} G_{9} s^{2}$
1	$C_{7} G_{3} G_{9} s$	1	$C_{11} C_{12} G_{9} s^{2}$
1	$C_{4} C_{7} G_{9} s^{2}$	1	$C_{10} C_{12} G_{3} s^{2}$
1	$C_{7} C_{11} G_{9} s^{2}$	1	$C_{4} C_{10} C_{12} s^{3}$
1	$C_{7} C_{10} G_{3} s^{2}$	1	$C_{10} C_{11} C_{12} s^{3}$
1	$C_{4} C_{7} C_{10} s^{3}$

If

$$ G_{1} = G_{3} = G_{6} = G , { }C_{4} = C_{7} = C_{10} = C_{11} = C_{12} = C , { }G_{2\_1} = G_{5\_3} = G_{8\_6} = G_{m} $$

then the voltage transfer gain becomes:

$$ A_{oi} = - \frac{{G_{m} \left[ {C^{2} s^{2} + C\left( {G - G_{m} } \right)s + G_{m}^{2} } \right]}}{{8C^{3} s^{3} + C^{2} \left( {3G_{m} + 10G + 4G_{9} } \right)s^{2} + C\left( {GG_{m} + 3G^{2} + 4G_{m}^{{}} G_{9} - G_{m}^{2} } \right)s + G^{2} G_{9} }} $$

The sensitivity of the voltage transfer gain in relation to the parameter G _m , $S_{{G_{m} }}^{{A_{0i} }} = \frac{{\partial A_{0i} }}{{\partial G_{m} }} \cdot \frac{{G_{m} }}{{A_{oi} }},$ has the expression:

For the numeric values C = 1 nF, G = 0.001 S, G _m  = 0.001 S, G₉ = 0.00005 S and replacing s with $j\omega$, the voltage gain expression $A_{ei} \left( {j\omega } \right)$ becomes:

$$ A_{oi} \left( {j\omega } \right) = - \frac{{125000 \cdot \left( {\omega^{2} - 0.1 \cdot 10^{13} } \right)}}{{j\omega^{3} + 0.165 \cdot 10^{7} \omega^{2} - 4 \cdot 10^{11} j\omega - 625.10^{13} }}. $$

Figure 23 shows the Bode diagram, and Fig. 24 presents the distribution of poles and zeros in the complex plane.

Fig. 23

Bode diagram for Aoi

Fig. 24

Pole and zero locations of small signal amplifier

For the above numeric values, the output file provides the following data about the required circuit function:

Real part: +1.999243e + 01	Imaginary part: 4.022459e + 01
Module: 1.999648e + 01	Argument: 3.121475e + 00

Example 5

The circuit in Fig. 25a, contains two operational amplifiers and passive circuit elements R, C. This circuit operates in a permanent harmonic regime as a capacitance multiplier with respect to the input terminals (4−5). By replacing the operational amplifiers with the equivalent scheme of Fig. 25b, the equivalent circuit represented in Fig. 25c, is obtained. The complex input impedance $\underline{Z}_{ii} \left( \omega \right)$ (with respect to the input terminals 4−7) has to be calculated with SATE.

Fig. 25

Capacitance multiplier

For the case when the resistances $R_{5} = R_{7} = 0 \, \varOmega ; { }R_{4} = R_{6} = 1{\text{ Meg}}$; C₃ = 10 pF (node 6 becomes 1, node 5 becomes 3, node 7 becomes 5, and the resistance R₆ becomes R₅) and the voltage gains $a_{8\_4} = a_{9\_6} = 2 \cdot 10^{5}$, the input file required by the SATE software, ex3.cir, has the following structure:

• 5 8 314.0

• 1 100.0 1 2

• 1 1e + 05 2 3

• 2 1e−11 3 4

• 1 1e + 06 4 1

• 1 1e + 06 5 2

• 10 2e + 05 0.0 5 1 4 1

• 10 2e + 05 0.0 5 3 5 2

• 12 4 5 4 5

For homogeneous controlled sources $\left( {e_{c} \left( {v_{C} } \right){\text{ and }}j_{c} \left( {i_{C} } \right)} \right)$, the program assigns two branches to each source (in this sequence: the controlled branch, the controlling branch). For the considered circuit, in the above simplified situation, where e₈ becomes e₆ with the controlling branch l₇ and e₉ becomes e₈ with the controlling branch l₉, the corresponding voltage gains have the expressions:

where: G₇ = 1 S and G₉ = 1 S, and $G_{6} = G_{8} = 1/2 \cdot 10^{5}$ S.

Results from the output file are as follows:

Terms of the circuit function numerator		Terms of the circuit function denominator
Sign factor	The value of common trees (in admittances)	Sign factor	The value of common trees (in admittances)
1	$G_{1} G_{6} G_{8}$	−1	$j\omega C_{3} G_{5} G_{6} G_{8}$
1	$G_{1} G_{7} G_{8}$	−1	$j\omega C_{3} G_{5} G_{7} G_{8}$
1	$G_{2} G_{6} G_{8}$	−1	$G_{4} G_{5} G_{6} G_{8}$
1	$G_{2} G_{6} G_{9}$	−1	$G_{1} j\omega C_{3} G_{6} G_{8}$
1	$G_{2} G_{7} G_{8}$	−1	$G_{1} j\omega C_{3} G_{7} G_{8}$
1	$G_{2} G_{7} G_{9}$	−1	$G_{1} j\omega C_{3} G_{7} G_{9}$
1	$G_{5} G_{6} G_{8}$	−1	$G_{1} G_{4} G_{6} G_{8}$
1	$G_{5} G_{7} G_{8}$	−1	$G_{2} j\omega C_{3} G_{6} G_{8}$
		−1	$G_{2} j\omega C_{3} G_{6} G_{9}$
		−1	$G_{2} j\omega C_{3} G_{7} G_{8}$
		−1	$G_{2} j\omega C_{3} G_{7} G_{9}$
		−1	$G_{2} G_{4} G_{6} G_{8}$
		−1	$G_{2} G_{4} G_{6} G_{9}$

For the numeric values, the output file of the program provides the following data about the required circuit function:

Real part: 5.010559e−001	Imaginary part: −3.165607e + 005
Module: 3.165607e + 005	Argument: −1.570795e + 000

If the two operational amplifiers are considered identical ($a_{6\_7} = a_{8\_9} = A$) and the resistances $R_{4} = R_{6} \to \infty$, while $R_{5} , \, R_{7} = 0 \, \varOmega$, then the input complex impedance expression becomes

$$ Z_{ii} \left( \omega \right) = \frac{{\left( {1 + A} \right) \cdot \left[ {A\left( {G_{1} + G_{2} } \right) + G_{2} } \right]\left( {G_{2} } \right)}}{{j\omega C_{3} \left[ {A^{2} \left( {G_{1} + G_{2} } \right) + A\left( {G_{1} + 2G_{2} } \right) + G_{1} + G_{2} } \right]}} $$

Assuming that the operational amplifiers are ideal $\left( {A \to \infty } \right)$ we obtain:

$$ \underline{Z}_{ii} \left( \omega \right) = \frac{{G_{2} }}{{j\omega C_{3} \left( {G_{1} + G_{2} } \right)}} = \frac{1}{{j\omega C_{3} \left( {1 + \frac{{R_{2} }}{{R_{1} }}} \right)}}. $$

The input impedance sensitivity, in respect of the conductance G₁, has the expression:

$$ S_{{G_{1} }}^{{\underline{Z}_{ii} \left( \omega \right)}} = - \frac{{G_{1} }}{{G_{1} + G_{2} }}. $$

From the last expression of the complex input impedance an equivalent capacity results as:

$$ C_{e} = C_{3} \left( {1 + \frac{{R_{2} }}{{R_{1} }}} \right) = 10.10^{ - 12} \left( {1 + \frac{{10^{5} }}{{10^{2} }}} \right) = 10.01.10^{ - 9} {\text{ F}} = 10.01{\text{ nF}} . $$

This capacitance is about a thousand times greater than capacity C₃. This circuit is used in integrated circuits technology to achieve high capacities. Due to miniaturization, integrated circuit technology usually produces capacitors with low capacities. The multiplication effect of the capacity is called the Miller effect for capacities [20, 27].

Example 6

The circuit containing all the types of controlled sources shown in Fig. 26, has the graphs $\left( {G_{1}^{i} , \, G_{1}^{v} } \right)$ shown in Fig. 27a and b. By performing the contractions presented in paragraph 6, we obtain the reduced graphs $\left( {G_{1r}^{i} , \, G_{1r}^{v} } \right)$ shown in Fig. 27c and d.

Fig. 26

A circuit containing all types of controlled sources

Fig. 27

The complete graphs $\left( {G_{1}^{i} , \, G_{1}^{v} } \right)$ and the reduced ones $\left( {G_{1r}^{i} , \, G_{1r}^{v} } \right)$

After operating the simplifications, the number of spanning trees in the two reduced graphs becomes much smaller. If we make similar simplifications in the graphs $\left( {G_{p}^{i} , \, G_{p}^{v} } \right)$, shown in Fig. 28a and b, we get the reduced graphs $\left( {G_{pr}^{i} , \, G_{pr}^{v} } \right)$ from Fig. 28c and d. The results of these simplifications are shown in Table 6. The number of trees in a graph has been calculated as it is presented in [20, 27].

Fig. 28

The complete graphs $\left( {G_{p}^{i} ,G_{p}^{v} } \right)$ and the reduced ones $\left( {G_{pr}^{i} ,G_{pr}^{v} } \right)$

Table 6 The results of the simplification procedure

We can observe a significant reduction in the number of trees in this simplification phase.

The command equations of the controlled sources are as follows:

$$ \begin{aligned} j_{1} & = 1 \cdot v_{2} , { }e_{12} = a_{12,13} v_{13} = R_{12} G_{13} v_{13} = \frac{{G_{13} }}{{G_{12} }}v_{13} , \\ j_{14} & = b_{14,15} i_{15} = G_{14} R_{15} i_{15} = \frac{{G_{14} }}{{G_{15} }}{\text{i}}_{ 1 5} , { }e_{16} = R_{16} i_{17} = \frac{1}{{G_{16} }}i_{15} . \\ \end{aligned} $$

The above simplifications do not affect the accuracy of the calculation, because they are operated in the graphs structure, which simplifies it, maintaining their equivalence.

If we consider C₃ = C₄ = C₅ = C₆ = C; G₇ = G₈ = G₉ = G, then the voltage gain factor Aoi has the following expression:

For the numeric values of the parameters

$$ \begin{aligned} C = { 1}.0{\text{e}}0 4 {\text{ F}};G = \, 0.000 1 {\text{ S}};G_{ 10} = \, 0.000 2 {\text{ S}};G_{ 1 6} = \, 0.000 1 {\text{ S}}; \hfill \\ G_{ 1 4} = { 2}.0{\text{ S}};G_{ 1 5} = { 1}.0{\text{ S}};G_{ 1 3} = { 4}.0{\text{ S and G}}_{ 1 2} = 1.0{\text{ S}}. \hfill \\ \end{aligned} $$

Figure 29 shows the Bode diagram, and Fig. 30 presents the distribution of poles and zeros in the complex plane.

Fig. 29

Bode diagram for A_oi

Fig. 30

Pole and zero locations of small signal amplifier

Example 7

The analog circuit shown in Fig. 31 contains all four types of linear controlled sources. The graph pairs $\left( {G_{1}^{i} ,G_{1}^{v} } \right)$, and $\left( {G_{p}^{i} ,G_{p}^{v} } \right)$, generated according to the rules presented in Sect. 5, are given in Figs. 32 and 33, respectively.

Fig. 31

Circuit diagram

Fig. 32

$\left( {G_{1}^{i} ,G_{1}^{v} } \right)$ graphs

Fig. 33

$\left( {G_{p}^{i} ,G_{p}^{v} } \right)$ graphs

At the beginning, we generate the voltage gain A _{oi_ex} (s), and we evaluate it at the nominal parameter values, keeping only the complex frequency s as a symbol. Then we compute the transfer function sensitivity A_{oi_ex} (s, x) in respect of each parameter x. The analysis is performed considering an initial sampling in the frequency range of interest and checking the error in some intermediate points. The circuit elements that have a small value of the relative sensitivity in this frequency range can be eliminated. To this end both zero-admittance (element removal) and a zero-impedance (contraction of the terminal nodes) can be used. The value of the voltage gain in which some nodes/branches have been contracted/eliminated, A _{oi ap} (s), is computed.

The magnitude and phase errors are given by:

$$ \varepsilon_{{\left| {A_{oi} } \right|}} = \frac{{\left| {A_{oi\_ex} \left( {j\omega } \right)} \right| - \left| {A_{oi\_ap} \left( {j\omega } \right)} \right|}}{{\left| {A_{oi\_ex} \left( {j\omega } \right)} \right|}} , $$

(65)

$$ \Delta \phi_{{A_{oi} }} = \frac{{\arg \left( {A_{oi\_ex} \left( {j\omega } \right)} \right) - \arg \left( {A_{oi\_ap} \left( {j\omega } \right)} \right)}}{{\arg \left( {A_{oi\_ex} \left( {j\omega } \right)} \right)}} . $$

(66)

For the circuit in Fig. 31 we find that only the capacitor C₂₂ can be eliminated by contraction of its nodes, because the voltage gain sensitivity is small in the frequency range of interest, as it is shown in Fig. 34. In Fig. 35 the error variations in the same frequency range of the transfer function magnitude and of the transfer function phase are represented.

Fig. 34

Sensitivity magnitude function of C₂₂ and frequency f

Fig. 35

Errors in voltage gain magnitude and in voltage gain phase

After the capacitor C₂₂ removal, and applying the above procedure we obtain the reduced graphs $\left( {G_{1r}^{i} ,G_{1r}^{v} } \right)$ and $\left( {G_{p}^{i} ,G_{p}^{v} } \right)$. The tree number reduction of these graphs is shown in Table 7.

Table 7 Tree number reduction of the graphs from Figs. 32 and 33

If the representation of the inductors and controlled sources based on the unity gyrator model [3, 4], is used, the number of trees in the current graph increases at least at 2821968 (612 times bigger than with our models). The running time to enumerate these trees on an AMD XP 2700, 2.16 GHz, 512 MB of RAM is presented by comparison in Table 8.

Table 8 Comparison of running time for enumerating the trees corresponding to the graphs from Figs. 32 and 33

The next step is to generate the numerator and the denominator expressions of the transfer function in the decreasing order of the complex frequency powers, and the coefficients of each complex frequency power in the decreasing order of their values. In this way we can eliminate one by one, the terms with the smallest values, if an error criteria for the magnitude and phase is verified over the frequency range.

The numerator of the voltage gain for the analog circuit in Fig. 31 has the following full symbolic expression:

and the denominator contains 387 terms.

According to the above procedure of elimination we obtain finally a reduction in the transfer function denominator from 387 to 31 terms.

In Fig. 36 the exact magnitude curve (502 terms in the denominator), that without C₂₂ (387 terms in the denominator), and the approximated magnitude (31 terms in the denominator) are represented, and in Fig. 37 we can see the phase variation in the three cases. The maximum error of the transfer function magnitude is 1.6%.

Fig. 36

Variation of the voltage gain magnitude in the frequency range

Fig. 37

Phase variation in the frequency range

A new method to formulate the system of equations in order to compute fully-symbolic small-signal characteristics of analog circuits by applying standard NA and/or loop current method has been presented.

7 Conclusions

By modelling electronic devices with equivalent circuits containing nullors and by associating to the analyzed circuit two graphs: one corresponding to the current one—Gⁱ, necessary to formulate the KCL, and one corresponding to the voltage one—G^v, necessary to formulate the KVL, the nodal equations and the loop current equations can be formulated very simple for any non-reciprocal circuit. The two graphs have the same number of branches, nodes and independent loops, but they differ by their different positions they occupy in the two graphs, by the branches used to simulate the controlled sources and, in general, by the branches corresponding to the equivalent circuits containing nullors used to model the electronic devices. The characteristics of the branches are written using the voltages from the voltage graph and the currents from the current graph.

In this chapter, we propose a simple modelling procedure of the controlled sources in the two graphs. The equivalent circuits based on the functional schemes with nullors model both the controlling port and the controlled one by admittances placed in different positions in the two graphs. The two graphs obtained in this way have the same number of branches, nodes, and loops. A new method to formulate the system of equations in order to compute fully-symbolic small-signal characteristics of analog circuits by applying standard NA and/or loop current method has been presented.

A set of rules for generating and using the two graphs is stated, and the generalization of the topological formula to generate all network functions is proved. These rules are applicable to a linear circuit containing: all four types of linear controlled sources, resistors, inductors, capacitors, nullors (for ideal opamps operating in the linear mode), and any multi-terminal or multiport circuit element having an equivalent scheme made up only by two-terminal elements and controlled sources.

The models with nullors for all active electronic devices are more effective for the optimization of design and simulation time during the analysis process. From this point of view, the nullors proved already their efficiency in the active devices modelling. In the models based on nullors, the parasitic elements can be included to analyze their contribution to the analog circuit response. All the four controlled sources can also be represented with equivalent circuits using nullor elements. Consequently, the nullors are very useful for the analog circuits modelling because the circuit topology can be described using only two-terminal components like resistors, capacitors, nullators, norators, independent and controlled sources. Considering that the model should be developed in the simplest manner and the accuracy of the circuit behaviour simulation must be in acceptable limits, this chapter will show the problems related to the small-signal models of the active devices modelled with nullors.

Unlike other similar approaches our approach does not introduce supplementary branches and nodes with respect to initial circuit. Moreover, the number of nodes in the two graphs is smaller than in the initial circuit with the number of CCVS. Modelling the controlled sources by admittances allows an efficient generation of the network functions via the generalized topological formula with homogeneous parameters. This formula works for linear nonreciprocal networks containing any type of controlled sources. The rules for the automated generation of the two graph pairs using the controlled source models proposed in this chapter and a representation on levels of the graphs were implemented in a very fast program for the symbolic transfer function computation.

The generalized topological formula can generate any network function in a full symbolic form for very large-scale analog circuits because the numerator and the denominator terms are generated one by one and stored as lists. This gives the superiority of the topological approach in contrast to the determinant method that cannot provide a full symbolic form because of the symbolic manipulator that cannot solve huge systems of algebraic equations.

The list form in which the numerator and the denominator are obtained also allows performing the simplification after generation in a simple manner.

Examples have been introduced to show the usefulness of the nullor-based models and the potential of the proposed approach for the analysis and design of the analog linear/nonlinear circuits.

From two-port and four-terminal network point of view, all the proposed models have been generated by taking into account the impedance levels associated to the input-output terminals along with the gain-equations of the active devices. As one can see throughout the chapter, the nullor-based models are not complex and they can quickly be included into symbolic analyzers. Further, nullor-based active device models by including parasitic elements, has also been introduced. Furthermore, a novel method to formulate the system of equations in order to compute fully-symbolic small-signal characteristics of analog circuits by applying only standard NA has been presented. Thus, by using the relationships of nullators and norators and by manipulating their data-structures, the admittance matrix can quickly be constructed, avoiding waste of CPU-time and memory in the formulation process. Examples have been introduced to show the usefulness of the nullor-based models and the potentiality of the proposed formulation method