Keywords

1 Introduction

Capacitive sensors are solid-state devices that reveal and quantify variations of physical, chemical or biological parameters the change of a capacitor. They are typically formed by two metal parallel plates separated by an insulator layer [1] and can be employed in applications as accelerometers [2], position sensors [3], pressure sensors [4] etc., where capacitance values can range from less than 1 pF up to hundreds of pF or even to nF. Their interfaces are based on the conversion of the capacitive value and variation into a voltage, a frequency (or period), a phase, etc. [5,6,7].

Differential (or ratiometric) sensors are a sub-set of these capacitive sensors employed to reduce resolution problems related to low capacitive variations and common mode disturbs. They have suitable applications in hair flow motion, accelerometers, position or rotation detection, force, etc. Figure 1 shows a simple schematization of a ratiometric capacitive sensor consisting in a three plates capacitive system with two fixed plates. The simplest differential sensing element is the capacitive AC half-bridge where two capacitors change their value in a complementary way under a stimulus; unfortunately, this topology shows a reduced and not constant sensitivity.

Fig. 1
figure 1

Differential capacitance sensor structure

In the literature, some analog interfaces for the ratiometric capacitive sensing have been proposed, based mainly on operational amplifiers [7,8,9,10,11], while current-mode interfaces are typically related to other sensor interfaces [12,13,14,15,16,17]. In this paper we propose two current conveyor-based interfaces performing a capacitive-to-voltage conversion, showing good and constant values of sensitivity and resolution.

2 The Current-Mode Interfaces

Considering Fig. 1, if the distance between the electrodes is changing, C 1 and C 2 have the following variations:

$$C_{1,2} = \frac{{C_{0} }}{2}\frac{1}{{\left( {1 \mp x} \right)}}$$
(1)

being C 0 the total capacitance of the transducer [9], from which measurand x can be expressed as independent from C 0 value as follows:

$$x = \frac{{C_{1} - C_{2} }}{{C_{1} + C_{2} }}$$
(2)

Figure 2 shows the first proposed interface (employing a current source as input signal), based on second generation current-conveyors (CCIIs).

Fig. 2
figure 2

The first proposed interface (C 1 and C 2 form the differential capacitive sensors)

From the properties of the ideal CCII (V X  = V Y , I X  = I Z for the CCII+ and I X  = −I Z for the CCII−) [12], a straightforward analysis gives:

$$V_{out,pp} \left( x \right) = R_{L}^{{\prime }} \,I_{IN,pp} \cdot \left[ {\frac{{C_{o} }}{{C_{o} + C_{3} }}x + \frac{{C_{3} }}{{C_{o} + C_{3} }}} \right]$$
(3)

being R L ′ the parallel impedance between the load resistance R L (see Fig. 2) and the impedance parasitic component at CCII Z node at working frequency (R Z ) and I IN,pp the peak-to-peak value of the input current.

The second interface here proposed (Fig. 3) shows an input stage employing a CCII-based voltage-to-current converter [12]; in this manner, the voltage input signal can be more easily injected through a standard laboratory waveform generator.

Fig. 3
figure 3

The second proposed interface (C 1 and C 2 form the differential capacitive sensors) including the voltage to current converter as input stage

In this case, Eq. (3) becomes:

$$V_{out,pp} \left( x \right) = R_{L}^{{\prime }} \,\frac{{V_{IN,pp} }}{{R_{1}^{{\prime }} }} \cdot \left[ {\frac{{C_{o} }}{{C_{o} + C_{3} }}x + \frac{{C_{3} }}{{C_{o} + C_{3} }}} \right]$$
(4)

being R L ′ the parallel impedance between the load resistance R L and the impedance parasitic component at CCII Z node at working frequency (R Z ), R 1′ the series impedance between the resistance R 1 and the impedance parasitic component at CCII X node at working frequency (R X ) and V IN,PP the peak-to-peak value of the input voltage.

3 Results

For experimental measurements we have employed AD844 component as CCII+, while CCII− is implemented through a cascade of two AD844 devices [12]. The following nominal values have been considered: working frequency = 10 kHz and R L  = 60 kΩ; concerning the input signal amplitude, we chose I IN,pp  = 1 mA for the first interface and V IN,pp  = 1 V, R 1 = 1 kΩ for the second one. Furthermore, having considered AD844 parasitic components at the working frequency (R X  = 50 Ω, R Z  = 3 MΩ), we have obtained R 1′ = 1.05 kΩ and R L ′ = 57.629 kΩ. We have considered a ratiometric capacitance sensing application, having a base-line value C O of 800 pF and a 10% maximum relative variation (x). The transducer behavior has been emulated, in the experimental phase, by two capacitors. The value of C 3 has been set to 100 pF.

Starting from parallel plate capacitor model, we considered a possible capacitive variation related to a change in the initial distance between the capacitor plates, d o :

$$C_{1,2} = \frac{\varepsilon A}{{(d_{0} \mp \Delta d)}}$$
(5)

The ratiometric equation becomes:

$$x = \frac{{C_{1} - C_{2} }}{{C_{1} + C_{2} }} = \frac{\Delta d}{{d_{0} }}$$
(6)

Concerning the first solution (shown in Fig. 2), we have performed only simulations that have been compared with the theory. Figure 4 shows the theoretical and simulated output voltages versus x parameter. The output range has been optimized, for the considered x variation, in the most part of the supply range. The relative percentage error is always lower, in absolute value, than 0.1%, so the proposed interface shows a good accuracy.

Fig. 4
figure 4

First interface: output voltage (theoretical, simulated) versus x

Having considered a MEMS application (d0 = 3 μm), the sensitivity is constant and valued about S = 8.54 V/μm. Sensitivity definition has been expressed according to [17]. Having evaluated a 576 nV output voltage noise, we have a resolution in terms of distance variation of about 674 pm, i.e., as capacitive value, of 89.85 fF (that is about −79 dB).

Concerning the second solution (Fig. 3), Fig. 5 shows the output voltage versus the measurand x. Theoretical, simulated (through Orcad-Spice software) and experimental results (averaged on 10 different measurements) are in a good agreement. Uncertainty on the experimental data has been expressed through the standard deviation: it is lower than 0.025 for the whole measurements. The relative percentage error has been calculated for the averaged experimental data is lower than 0.2% between simulations and theory and than 3% between theory and measurements.

Fig. 5
figure 5

 Second interface: output voltage (theoretical, simulated, measured) versus x

Then, having considered d0 = 3 μm, sensitivity value for the second interface is constant and valued about 8.13 V/μm. Having evaluated a 662 nV output voltage noise, we have a resolution of about 814 pm for the above mentioned case. This spatial resolution value corresponds to a capacitance resolution of 108.5 fF (that is about −77 dB). A suitable ADC [18] has been utilized for better reading of the output voltage.

A comparison of the main characteristics of the presented interfaces, with respect to those reported in the literature, is here presented in Table 1. We underline the fact that the works reported in [6, 10] are related to a single ended capacitive sensor (despite the second one is showing a differential output and its approach is also applicable to ratiometric sensors). The here proposed circuits show better values of sensitivity and resolution (in dB), also being constant for each operating point.

Table 1 .

4 Conclusions

We have shown two novel current-mode analog interfaces for revealing and measuring ratiometric capacitive sensors. Experimental measurements have been performed on a discrete element board, employed through a commercial CCII (AD844). Both of our proposed architectures have shown a good agreement with the theoretical expectations. Sensitivity and resolution (showing constant values for each considered working point) have been determined in a practical case, showing satisfactory values.