1 Introduction

Solid-state electronics develop enormously every year, thanks not only to circuit design innovation, but also to the development of better technologies. All this allows to constantly reduce power consumption of electronic systems, while keeping the other performance metrics almost unchanged. In this scenario, energy harvesting is becoming more and more interesting as it allows to reduce the cost of an application by avoiding a periodic replacement of the batteries or by reducing their size, or even allowing the implementation of battery-less systems. There are many environmental energy sources that can be exploited for these purposes (e.g. light, temperature gradient, mechanical vibrations, electromagnetic). The choice of the best source of energy clearly depends on the application. Usually the most abundant form of energy is chosen, even if there are exceptions due to system size and shape.

The focus of this chapter is in the field of industrial machines and vehicle monitoring, in which the sensing electronic systems are positioned usually in inaccessible places (the moving parts), where the cabling can be expensive or almost impossible. The most abundant form of energy in the moving parts of machines is clearly mechanical and so vibrational harvesters are chosen in these systems. There are many types of vibrational harvesters: piezoelectric, electrostatic, magnetic. This chapter will focus on the interfacing of electrostatic harvesters. Basically, these devices are charged capacitors with one plate fixed (or just connected to a bigger inertial mass) and the other moving because of the environmental accelerations. In [1], a circuit capable to both bias the variable capacitor and extract power from its movement is proposed. A drawback of this design is that part of the power extracted is used for the polarization of the capacitor. Additionally, this design strategy limits the capacitor polarization voltages to the maximum voltage ratings of the chosen IC manufacturing technology, which most of the times is lower than the polarization voltage for the harvester itself. A solution for scavenging more efficiently energy from the environmental vibrations consists in building a partially isolated structure, in which the variable capacitor is pre-charged with a certain potential and then isolated from the outside world. In this case, the charged electrode is called electret and the harvesters fabricated in this way are denoted as electret-based electrostatic energy harvesters. Recently, this type of harvesters attracted quite some attention, thanks to their capability to generate a large amount of power, even at low accelerations [2]. Unfortunately, these harvesters have extremely large internal impedances, making challenging the design of interfacing circuits for efficient power extraction. In particular, those circuits need to be at the same time ultra-low-power and resistant to several tens of Volts applied on their inputs. In [3] an interfacing circuit working with an input voltage range between 5 and 60 V has been proposed. The main disadvantage of that circuit was mainly the power consumption, as it was not working under 25 μW of available power.

2 Open-Loop Inductive Buck Converter at Low AvailablePowers

Considering the large voltage ranges required by the applications, the best choice is an inductive converter. As shown in Fig. 18.1a, the basic structure of an inductive DC-DC buck converter is consisting of a switch connected to the input and a diode (implemented with passives or, more often, with active circuits). Given the low available power in energy harvesting applications, the converter should be used in Discontinuous Conduction Mode (DCM), meaning that during the period T there will be some time in which the inductor current will be constant and equal to zero. This is particularly efficient at low power levels because many control circuits can be turned off when there is no conduction of current to the load. A typical waveform in DCM is shown in Fig. 18.1b. Assuming that the input voltage of the converter is almost constant (the input capacitor has to be large enough), we can easily calculate the input resistance of the converter if operating in open-loop (as charger and not as voltage regulator) by calculating the ratio of the input voltage over the average inductor current flowing during the TON time (when the switch is ON).

Fig. 18.1
figure 1

Basic implementation of a DC-DC buck converter (a) and inductor current in discontinuous conduction mode (b)

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In particular, we get the following expression:

$$ {R}_{IN}=\frac{2LT{V}_{IN}}{T_{ON}^2\left({V}_{IN}-{V}_{OUT}\right)} $$
(18.1)

Note that, for energy harvesting purposes, the input resistance needs to match the source resistance of the harvester RS. This means that a Maximum Power Point Tracking (MPPT) algorithm needs to be implemented in order to achieve power matching. So, in a Pulse Frequency Modulation (PFM) scheme, the period T would have to be modified according to the following law:

$$ T=\frac{R_S{T}_{ON}^2\left({V}_{IN}-{V}_{OUT}\right)}{2L{V}_{IN}} $$
(18.2)

As it can be easily recognized, if the input voltage gets close to the output voltage, the period T needs to be decreased by the MPPT algorithm in order to efficiently extract power from the harvester. Assuming that most of the control circuit consumption happens during the conduction time and considering that the conduction time is TON*VIN/VOUT, the total power consumption is then given by:

$$ {P}_{CTRL}={P}_Q+{k}_1\frac{T_{ON}}{T}\frac{V_{IN}}{V_{OUT}}+\frac{k_2}{T} $$
(18.3)

where PQ is the quiescent power, k1 is a constant equal to the power consumed by the blocks turned ON during the conduction phase and k2 a constant equal to the energy dynamic losses due to the switching operations. By substituting (18.2) in (18.3), we obtain:

$$ {P}_{CTRL}={P}_Q+\left(\frac{k_1{T}_{ON}{V}_{IN}}{V_{OUT}}+{k}_2\right)\frac{2{V}_{IN}L}{\left({V}_{IN}-{V}_{OUT}\right){T}_{ON}^2{R}_S} $$
(18.4)

Calculating the limit of (18.4) for VIN tending to VOUT, we get that PCTRL tends to infinite. So, when the available power from the harvester decreases, the control power increases, reducing dramatically the converter efficiency. A similar reasoning can be applied to PWM schemes. In this case, the control power results:

$$ {P}_{CTRL}={P}_Q+\frac{k_1{V}_{IN}}{V_{OUT}T}\sqrt{\frac{2{V}_{IN} TL}{R_S\left({V}_{IN}-{V}_{OUT}\right)}}+\frac{k_2}{T} $$
(18.5)

It can be appreciated that also in PWM schemes the control power tends to go to infinity when the available power tends to zero. Equations (18.4) and (18.5) represent a problem that needs to be solved in order to lower significantly the power consumption of electrostatic harvester interfaces.

3 Hybrid Modulation Scheme

Both PFM and PWM modulation schemes have the characteristic of varying only one parameter: TON or T. However, from equation (18.1) we can see that the period T is proportional to TON 2. This means that, while maintaining resistance matching, the period T could be increased of α2 if TON is increased of a factor α. Of course, TON is not a parameter that we can freely choose, because it defines the peak current in the inductor IP. Since, for a given power train, an optimal peak current for maximizing energy efficiency exists, TON cannot be increased ad libitum in order to reduce the operating frequency. A good compromise is easily found and consists in fixing the peak current in the inductor to a value close to its optimal value. This means that TON is chosen at each period in order to keep the peak current constant and then the period T can be calculated:

$$ T=\frac{R_S{I}_P^2L}{2{V}_{IN}\left({V}_{IN}-{V}_{OUT}\right)}\vspace*{-3pt} $$
(18.6)

In this case, the period tends to infinity for input voltages close to the output voltage. To verify that this approach solves the problem, we can calculate the power dissipation of the control circuits:

$$ {P}_{CTRL}={P}_Q+\frac{2{V}_{IN}\left({V}_{IN}-{V}_{OUT}\right)}{I_P^2L{R}_S}\left[\frac{k_1{V}_{IN}L{I}_P}{V_{OUT}\left({V}_{IN}-{V}_{OUT}\right)}+{k}_2\right]\vspace*{-3pt} $$
(18.7)

The limit of PCTRL for VIN tending to VOUT is then equal to:

$$ \underset{V_{IN}\to \kern0.62em {V}_{OUT}}{ \lim }{P}_{CTRL}={P}_Q+\frac{2{V}_{IN}^2{k}_1}{I_P{R}_S{V}_{OUT}}\vspace*{-3pt} $$
(18.8)

Notice that now the control power tends to PQ when the available power (VIN 2/4RS) tends to zero.

3.1 Proposed Implementation

The design architecture needs then to generate the proper period T at each cycle, following equation (18.6). Given the relative complexity of equation (18.6), it may seem hard to do it in a simple way. In reality, the problem can be solved pretty easily by using the system shown in Fig. 18.2a.

Fig. 18.2
figure 2

Proposed implementation of the timing control circuit (a) and its waveform (b)

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Assuming now that the conversion period starts when the capacitor voltage VC becomes lower than a certain reference VREF, we get:

$$ T=\frac{{\displaystyle \underset{0}{\overset{T_{ON}}{\int }}{I}_{UP}(t)dt}}{I_{DOWN}}\vspace*{-3pt} $$
(18.9)

Imposing that (18.9) needs to be equal to (18.2), we get that IUP needs to be a scaled copy of the inductor current and IDOWN a current proportional to the input voltage:

$$ \left\{\begin{array}{c}\hfill {I}_{UP}=\frac{i_L}{N}=\frac{\left({V}_{IN}-{V}_{OUT}\right)}{NL}t\hfill \\ {}\hfill {I}_{DOWN}={k}_{MPPT}{V}_{IN}\kern2.86em \hfill \end{array}\right.\vspace*{-3pt} $$
(18.10)

where N is the scaling factor of the inductor current copy and kMPPT is a factor used by the MPPT algorithm in order to change the input resistance of the converter. In particular the input resistance will result equal to 1/(N*kMPPT). Finally, note that, for fixed values of input and output voltages, IUP increases linearly in time during the interval of time TON and IDOWN is constant. Therefore, the capacitor voltage VC will behave like depicted in Fig. 18.2b.

3.2 Circuit Implementation

The proposed system architecture is shown in Fig. 18.3, with the integrated blocks highlighted in grey and the die photo on top. Excluding harvester, rectifier and load, there are 4 external components: 2 decoupling capacitors (CIN = 100 nF and COUT larger than 10 μF), 1 inductor (L = 10 mH) and 2 resistors (RDC = 10 GΩ and RBIAS = 100 MΩ).

Fig. 18.3
figure 3

Proposed system architecture and die photo

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The resistors RBIAS and RDC are used respectively for defining a bias current of about 10 nA and for providing a basic bias current in start-up conditions. In particular, this start-up bias current is used by a level shifter which shorts the input to the output. All the control mechanisms are based on inductor current sensing. In particular, the sensed copy of the inductor current is used for the timing control, the peak current control and also for the MPPT algorithm, which has to calculate the output power variation. Additionally, in order to allow battery-less operation, the system includes also a shunt regulator and a smart load activation circuit, which connects the load to the output and allows the load to request to be disconnected after it has performed all its operations.

Figure 18.4 shows the circuit implementation of the timing control block. The copy of the inductor current ILC1 is mirrored into transistor MP2 and integrated by the capacitor C. Simultaneously, the inductor current is also mirrored by MP7, with the aim to perform the peak current control and define the ON-time TON with the voltage VPLN. As indicated in the previous sub-section, the down current has to be proportional to the input voltage VIN. In order to avoid additional external components, the input voltage is sensed in an indirect way: the inductor current (proportional to VIN-VOUT) is mirrored by MP3 and summed to another current IP4 proportional just to VOUT. The resulting diode voltage of MN4 is then sampled and used to bias a current DAC, which receives as input the MPPT settings b0-b15.

Fig. 18.4
figure 4

Proposed timing control block

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3.3 Measurements

The chip has been fabricated in 0.25 μm BCD technology, and in particular using a flavor with 60 V-tolerant MOSFETs. The characterization has been carried out for various values of source resistance, between 500 kΩ and 25 MΩ. The MPPT efficiency (input power over available power) and the end-to-end efficiency (output power over available power) are shown respectively in Figs. 18.5 and 18.6.

Fig. 18.5
figure 5

MPPT efficiency as function of available power

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Fig. 18.6
figure 6

End-to-end efficiency as function of available power

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Focusing on the left side of the previous figures (around 1 μW available power), the MPPT efficiency is less than 50 %, while the end-to-end efficiency is larger than 10 %. This means that the total power dissipation in this condition is lower than 500 nW, demonstrating the impact of the adopted hybrid modulation scheme. At higher power levels, the MPPT efficiency and end-to-end efficiency reach up to 99 % and 85 %, respectively. As shown in Table 18.1, this work is at state-of-art level even if compared with uncomplete designs (e.g. without MPPT, start-up circuits or load regulation) or not capable to interface high input voltages. In fact, [4] and [5] have no cold-start, only [6] implements an MPPT algorithm but dissipates much more power.

Table 18.1 Comparison with state-of-art designs
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4 Conclusions

We have presented an electrostatic harvester interface, based on an ultra-low-power and high-voltage inductive DC-DC converter. Thanks to the proposed modulation scheme, the quiescent current of the converter is lower than 500 nW. The minimum operational available power is 1 μW and the maximum input voltage is 60 V. The chip is fully autonomous and includes start-up, shunt regulation and maximum power point tracking. The converter is capable of tracking source resistance variations between 0.5 MΩ and 25 MΩ.