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Retargetable Compilation

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Handbook of Computer Architecture

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Abstract

Compilers are essential tools to implement application software, coded in high-level programming languages, on programmable processors. Compiler construction has been an established engineering discipline for several decades. This has resulted in the availability of common technologies and tool infrastructure for compiler engineers. However, to cope with ever-increasing computational demands of electronic system applications, processor architectures have evolved drastically since the early days of compiler engineering. This continues to bring new challenges for compiler developers.

Today’s systems-on-chip can contain a significant number of processor cores. Their architectures exhibit higher amounts of parallelism and specialization. An important requirement, driven by new generations of embedded electronic applications, is that processor architectures are tuned for the needs of their application domain, resulting in so-called application-specific processors or ASIPs.

The impact on compilers is multifold. Compilers must be able to exploit the features of highly specialized architectures. For each new architecture, a compiler must become available in very short time. Processor architectures and compilers should be codeveloped so that early compilation of application code can provide feedback to drive architectural decisions.

Retargetable compilers adapt automatically to the architecture of a processor, based on a user-defined processor model. Retargetable compilation received initial attention from compiler researchers in the 1990s, and recently saw renewed interest and adoption as a technology that addresses several of the challenges of today’s and tomorrow’s embedded electronic applications. This chapter discusses concepts, challenges, and solutions in the domain of retargetable compilation. First, retargetable compilation is positioned in a broader historical perspective of compiler technology development. Next, specific requirements for retargetable compilers are formulated, stemming from the wide architectural scope of contemporary application-specific processors. Finally, models, techniques, and optimization algorithms for retargetable compilers are reviewed.

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Acknowledgments

The authors express their appreciation to the reviewers and to their colleague Sven Wuytack for their constructive feedback on this chapter.

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Authors and Affiliations

  1. Synopsys, Leuven, Belgium

    Gert Goossens, Dirk Lanneer, Johan Van Praet & Werner Geurts

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  1. Gert Goossens
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  2. Dirk Lanneer
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  3. Johan Van Praet
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  4. Werner Geurts
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Corresponding author

Correspondence to Gert Goossens .

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Editors and Affiliations

  1. Sch of Computer Science & Engineering, Nanyang Technological University, Singapore, Singapore

    Anupam Chattopadhyay

Section Editor information

  1. Center for Advancing Electronics Dresden, TU Dresden, Dresden, Germany

    Jeronimo Castrillon

  2. Pleasanton, CA, USA

    Grant Martin M.Math

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Goossens, G., Lanneer, D., Van Praet, J., Geurts, W. (2022). Retargetable Compilation. In: Chattopadhyay, A. (eds) Handbook of Computer Architecture. Springer, Singapore. https://doi.org/10.1007/978-981-15-6401-7_67-1

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  • DOI: https://doi.org/10.1007/978-981-15-6401-7_67-1

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