Interconnect Macromodelling and Approximation of Matrix Exponent V.G. KurbatovM.N. Oreshina OriginalPaper Pages: 5 - 19
Common-Mode Response Overlapping vs. Shaping in Rail-to-Rail Op-Amp Input Stages J. Francisco Duque-CarrilloJuan M. CarrilloJosé L. Ausín OriginalPaper Pages: 21 - 29
A Wide Bandwidth Isolation Amplifier Design Using Current Conveyors An Sang Hou OriginalPaper Pages: 31 - 38
A Rank Encoder: Adaptive Analog to Digital Conversion Exploiting Time Domain Spike Signal Processing Philipp HäfligerElin Jørgensen Aasebø OriginalPaper Pages: 39 - 51
A Square-Root Domain Differentiator Circuit Spiridon VlassisCostas Psychalinos OriginalPaper Pages: 53 - 59
A Balanced Capacitive Threshold-Logic Gate Javier López-GarcíaJosé Fernández-RamosAlfonso Gago-Bohórquez OriginalPaper Pages: 61 - 69
Very Low Voltage MOS Translinear Loops Based on Flipped Voltage Followers Antonio J. López-MartínAlfonso CarlosenaJaime Ramirez-Angulo OriginalPaper Pages: 71 - 74
A New CMOS Rail-to-Rail Low Distortion Balanced Output Transconductor Mohamed A. YoussefAhmed M. Soliman OriginalPaper Pages: 75 - 82
Novel Canonic Current Mode DDCC Based SRCO Synthesized Using a Genetic Algorithm Varun Aggarwal OriginalPaper Pages: 83 - 85
SITO High Output Impedance Transadmittance Filter Using FTFNs N.A. ShahS.Z. IqbalB. Parveen OriginalPaper Pages: 87 - 89
New Wide Band Low Power CMOS Current Conveyors Wessam S. HassaneinInas A. AwadAhmed M. Soliman OriginalPaper Pages: 91 - 97
A Four Quadrant Analog Multiplier Employing Single CDBA Ali Ümit Keskin OriginalPaper Pages: 99 - 101
A CAD-Based Investigation of Clock-Skew Hazards in Pipelined NORA Dynamic Logic Circuits Fei Yuan OriginalPaper Pages: 103 - 108