Reduced Order Modeling for RLC Interconnect Tree Using Hurwitz Polynomial Xiao-Dong YangChung-Kuan ChengRobert Carragher OriginalPaper Pages: 193 - 208
The Effect of Signal Activity on Propagation Delay of CMOS Logic Gates Driving Coupled On-Chip Interconnections Kevin T. TangEby G. Friedman OriginalPaper Pages: 209 - 224
Power Supply Design Parameters for Switching-Noise Control in Deep-Submicron Circuits Design Flows M. GrazianoG. MaseraM. Zamboni OriginalPaper Pages: 225 - 248
Incorporating Voltage Fluctuations of the Power Distribution Network into the Transient Analysis of CMOS Logic Gates Kevin T. TangEby G. Friedman OriginalPaper Pages: 249 - 259