1 Introduction

Compared to the homogeneous networks, the sensor nodes of heterogeneous wireless sensor network have different ability in terms of their sensing range and computing capability. Also, the deployment and topology control are more complex in heterogeneous sensor networks because it uses much energy during the communication process rather than carrying out computational work. Apart from these, the usage of battery in the sensor nodes put significant constraint on the availability of energy level. Thus quick drain in the sensor nodes energy level, degrades the lifetime of the network. In addition to this, the clock frequencies would scale along with technology in the latest processors. Therefore, the primary criterion that could be considered among different cores is the energy level dissipation.

The sensor nodes sense data and communicates it with neighboring sensor nodes over wireless links, transmitting it through the gateway, which can operate independently or connect to a host system where the data can be collected, processed, analyzed and displayed using software. Currently, wireless sensor networks are used with various applications that are not limited to defence, smart spaces, environmental, medical, entertainment, military, transportation, etc. The ability to deploy large numbers of tiny sensors, assembling and configuring themselves for a specified application ranging from real-time tracking, shows the power of wireless sensor networks over various computing environments.

In [1], the surveillance system has to alert the authorities in real time on detecting an intruder. In [2], there are resource constraints in any sensor platforms in terms of energy consumption. Although, unanswered challenges still existing and the designers related with tradeoff between communication cost and computation cost, is having tremendous progress in sensor design. The first and second generation scalar motes were based on less efficient 8-bit microcontrollers, designed to function simple arithmetic and logical operations with less amount of energy. For simple processing approaches such as periodic sensing of some values, microcontroller with limited instruction set is essential. However, several study proved that the single core architecture less efficient in its processing speed and consumption of energy. Therefore to optimize power consumptions multicore architecture calculates the energy consumed on receiving k bits of data. Thus replacing single core and computing sensed data within the node processor to reduce the redundancy of packet information including the communication cost. Also, scheduling plays a crucial role in minimizing the delay between the nodes, as it works with low frequency.

2 Related Works

In [1], the design of wireless sensor networks for various applications embedded with multi-core is specified. The authors have evaluated the performance of the considered multicore architecture. In [3], have successfully designed the multicore processor for industrial applications and in [4] a survey on task scheduling for multicore systems. The author presented the adaptive multicore scheduling on the multicore processors are very efficient. In [5], considering the applications using accelerator based architecture, the author describes the power consumption nature and the cost of computation in WSN. Based on [6] the energy for communication and sending packets is the same and is calculated as:

$$E_{rs} \left( {k,d} \right) = \left\{ {\begin{array}{*{20}l} {kE_{exec} + k\varepsilon_{min - exp} d^{2} :} \hfill & {d < d_{0} } \hfill \\ {kE_{exec} + k\varepsilon_{two - zxy - exp} d^{4} :} \hfill & {d > d_{0} } \hfill \\ \end{array} } \right.$$

Also, the energy consumed on receiving k bits of data is as follows [7]:

$$E_{rx} \left( k \right) = E_{rx - exec} \left( k \right) = kE_{exec}$$

Based on this concept, it is identified that the sensing subsystems energy consumption is greater when compared to the rest of the sensing nodes as a result of many different factors [8]. The authors state that transducers require higher resources to perform sampling task. For example, the multimedia, chemical and biological sensors require huge power [9]. Most of the energy-efficient data acquisition techniques exclusively aim on decreasing the number of communications.

Considering that the energy consumed by sensor is negligible when compared to radio energy and most of the data-acquisition techniques rely on this and must be concentrated to improvise energy efficiency. By the introduction of mobility characteristics, it has reduced many problems related to network connectivity. Usually, nodes that are closer to the sink will have energy depletion problem even after applying energy conservation techniques as they always relay more packets [10]. If the designated mobile device voluntarily takes the responsibility of data collection, the traffic flow can be altered. Thus without facing the limitation on multi hop traversal, all the other ordinary nodes wait to route the messages based on proximity. Thereby, the ordinary nodes save energy and there is a uniformed distribution of energy consumption across all nodes while data communication. In [11] the entropy based redundant elimination can accurately reflect the correlation of link failures and their efficiency validated through LLL methods. In [12] allows the exploration of the optimal transmission path in wireless sensor networks using the elite ants algorithm. In [13] it has proved that the network lifetime is longer in case of ECS when compared to the other baseline algorithms. In [14] the stated algorithm optimizes the problem using game theory and an exact potential game is proposed. In [15] the corrupted packet undergoes low density parity check, uses the relay node before the packet transmission is herewith proved (Fig. 1).

Fig. 1
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Processor ports

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3 Methodology

CESingle-core WSN Architecture (CESWSN): The proposed (CESWSN) CESingle-core Wireless Sensor Network Architecture maximizes the performance while execution and increases the energy efficiency within the given constraints. The proposed CESWSN architecture satisfies the computational requirements over wide range of wireless sensor applications and the architecture heterogeneity is sub-summed. This is depicted in Fig. 2. The proposed architecture is hierarchical it comprises numerous clusters and a sink node. The cluster is the group of sensor nodes communicating with each other within the range. Assuming that, the architecture consists of multiple processor cores and executes the same instruction set; achieve different performance for the given set of application. During the execution, the operating system identifies single core or multicore, thereby meeting the objective. For a wider set of applications the best core will often not be the best for a specified function. In addition, the demand for any single application may vary across various phases, as the processor’s power condition changes.

Fig. 2
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CEMulti-core wireless sensor network architecture (CEMWSN)

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The experiments explore in examining single application considering possible changing conditions. However, on considering multiple simulating applications with several function objectives with potential to adapt changing applications, it is believed that real systems will switch to cores on adapting changing environmental conditions and executing for greater opportunities. Therefore, the processors with static workload if considered, the results indicate that it is sufficient for significant gains. Otherwise, a larger set of cores provide greater benefits. Compared to larger wireless sensor networks, the small networks sense data faster. Cluster with cluster head consists of several child nodes that pre-processes and transmits the data to the cluster head node. The biggest drawback here is, the child nodes cannot do complex processing of large sized images. This is overcome in the proposed architecture. Cluster head with multi-core processor fuses the data received from child nodes transmitsit to the sink mode. The energy and bandwidth here is efficient by sending all the collected data from cluster head to the sink mode limiting the bandwidth.

The proposed processor is a 32-bit architecture, utilizing lesser time for processing and supporting suitable instructions for sensor networks. The design of soft-core multicycle architecture suitable for sensor networks is the main objective. This multicycle architecture allows using the processor’s functional units more than once per instruction execution cycle. Therefore, the multicycle architecture can helps to reduce the amount of required hardware for the soft-core processor design, which is very important for reducing the execution time of the application program. The proposed sensor node architecture provides smaller processor soft core area and that will reduce the space on the chip to integrate other functional units needed for the processing of the sensor network applications. The proposed sensor network node soft core architecture shown in Fig. 3 it includes the memory unit, working registers and the ALU unit (Fig. 4).

Fig. 3
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CESingle-core wireless sensor network architecture (CESWSN)

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Fig. 4
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Design of CEMulti-core PROCESSOR

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3.1 Instruction Formats

CEMulti-core Wireless Sensor Network Architecture (CEMWSN): Figs. 5 and 6 depicts our proposed hierarchical architecture that sub-sums the integration of numerous single-core (Tables 1, 2, 3).

Fig. 5
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Proposed—fetching unit

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Fig. 6
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Proposed—fetching unit

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Table 1 Arithmetic instruction
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Table 2 Immediate instruction
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Table 3 Jump instruction
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Emerging Wireless Sensor Networks adopt a plethora which inturn made the humans more helpful in the requirements. Despite from sensors wireless sensor networks essentially included embedded processor, communication unit combined with limited power supply. Unassured challenges still remain for example trade-off between communication cost and computational cost, having tremendous program in sensor design; accumulate information to a base node which in turn is not sufficient for sensor devices having image sensors and smart cameras. Intensive information hungry applications made the single core architecture as less efficient interms of power and speed. In order to optimize power consumption, multicore can replace single core with in a SOC implementation provides efficient embedded wireless sensor networks. CEMulti-core architecture is energy saving over traditional embedded wireless sensor networks in 2 ways (Figs. 7, 8, 9, 10).

Fig. 7
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MIPS

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Fig. 8
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Scheduler MIPS integrated output

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Fig. 9
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Multi-core processor

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Fig. 10
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Multi-core processor

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It is very difficult and expensive on adding the cores or threads of lower clock rates as the processors clock rate today is 8.429 GHz. Also, the done wave transmitted is measured in hertz. The CEMulti-core processor process the data accordingly the instructions are provided. Here three processor cores are designed and it can be connected to the common instruction memory. The data can be processed and it will be noted as a CEMulti-core architecture for various applications. Reduction in energy consumption and increasing the processing of different data are the objectives of the system. There are 3 cores in the processor so that the processing time can be thrice as that of the single core processor. This CEMulti-core processor can be incorporated with the processing of Image, data from the temperature, LDR sensors and it can be processed with in the multicore processor simultaneously. Every particular CEMWSNs execution time and energy consumption values are noted. The power consumption is less when compared to the MCWSN’s. Since the evolution of processor era, it is very significant in move from the single core processor to the multicore processor.

In general WSN (Wireless Sensor Node) at present can consume the more amount of power in the CMOS. The survey stated that the in the near future due to this power consumption in the large servers and the dissipation can make the city prone to various environmental hazards. Many multicore processors used for wireless sensor node in the present day scenario are power consuming. Thus the main focus on the power consumption reduction in the multicore processor for wireless sensor node in various applications have made the WSN to be used effectively. Here the CEMWSN’s are designed using the Basys 2 board and the power consumption can be calculated for both the CESWSN’s as well as the CEMWSN’s.

The CEMmulticore processor designed can execute the instructions in parallel manner so that the execution time can be increased.

$$\frac{{{\text{Execution}}\;{\text{time}}_{\text{MCWSN}} }}{{{\text{Execution}}\;{\text{time}}_{\text{CEMWSN}} }} =\upeta$$

Performance of CEMWSN is

$${\eta = }\frac{{{\text{Performance}}_{\text{CEMWSN}} }}{{{\text{Performance}}_{\text{MCWSN}} }}$$

This signifies that here the number of rate completed is high and parallelism exploited to increase ILP

$$\begin{aligned} {\text{for}}\;\left( {{\text{k}} = 0;{\text{k}} < = 999;{\text{k}} = {\text{k}} + 1;} \right) \hfill \\ {\text{Assuming}}\;{\text{k}} = = {\text{i}}, \hfill \\ {\text{X}}\left[ {\text{i}} \right] = {\text{X}}\left[ {\text{i}} \right] + {\text{Y}}\left[ {\text{i}} \right]; \hfill \\ \end{aligned}$$

The speculation mean given by

$$geom = \sqrt[n]{{\mathop \prod \limits_{i - 1}^{n} x_{i} }}$$

The iterations can overlap with other and the speedup of the proposed finds to be high as:

$${\text{Speedup}} = \frac{{{\text{Exec}}.\;{\text{time}}_{MCWSN} }}{{{\text{Exec}}.\;{\text{time}}_{\text{CEMWSN}} }} = \frac{1}{{\left( {1 - {\text{Fraction}}_{\text{enhanced}} } \right) + \frac{{{\text{Fraction}}_{\text{enhanced}} }}{{{\text{Speedup}}_{\text{enhanced}} }}}}$$

Circuits on switching to different states, dissipate the capacitive loads dynamically as they charge and discharge. The load capacitance varies based on the size. The sum of voltage supplied and the voltage swing indicates the entire load capacitance, which is proportional to the energy generated. At times, the switching circuits may undergo short circuits due to the pull-up and pull-down in the devices. The controller reschedules the memory requests using front end engine. The commands are generated by the logic in transaction processing. Further the physical interfaces, data signals and addresses enable communication between off-chip to memory and vice versa. The clock signals generated by the fractional dividers and the clock distribution network route the clock signals. The mapping of the clock network model with clock distribution is understandable from the circuitry.

The assumed power and area in creating a core has the greater sequential performance and is scaled up based on Amdahl’s law. Here Sp is the ratio of time spent in serial port, N as the No. of processors.

$$Scaled\;Speedup = N + \left( {1 - N} \right)*S_{P}$$

Thus the efficiency speed up can be calculated using:

$$Speed\;up = \frac{1}{{S + \frac{1 - S}{n} + 1 + \left( n \right)}}$$

The architecture speeds up both sequential and parallel execution as there is increase in the core resources. As per Amdahl’s law, the original execution time is divided by enhanced execution time is the speedup.

4 Experimental Results

Designed a Single core MIPS processor consisting of the ALU, PC, Data Memory, Instruction memory by writing the code in VHDL language using Xilinx ISE. Then synthesized the code and the results were verified using ISIM Simulator. The simulated results are shown: In considering the above MIPS processor the instructions can be pipelined and it can execute 100 million instructions per second.

In this, we have integrated a scheduler along with the MIPS processor to fetch the data accordingly with the EDF algorithm. The data which has the deadline priority can be processed first. This can execute 123 Million instructions per second (MIPS)which are slightly higher than the MIPS processor.

In the multicore processor designed there are 3 cores and each core can execute the instruction in an effective manner. So that the processing speed can be 273 MIPS (Million Instructions per Second). This is almost 3 times faster than the MIPS Single core processor.

4.1 Performance Comparison

From the Fig. 11 it is clear that the Multicore processors can accommodate more amounts of transistors thus the processing speed also increased according to the Moore’s law. From the Fig. 12 the clock frequency for the various processors are compared. The multicore processors have more clock frequency as compared to the single core and dual core processors. So the processing speed is increased. It can execute 273 million instructions per second when compared to the single core only 113 million instructions per second which is as twice as that for the multicore processors.

Fig. 11
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Single core versus multicore

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Fig. 12
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Clock frequence comparison

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The clock power consumption for processing is higher in the Multicore processors when compared to the single core processors. This is because the processing speed is higher in the multicore processor when compared to the single core. But the total power consumption is drastically reduced in the multicore processor when compared to single core processor (Figs. 13, 14, 15).

Fig. 13
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Different cores clock frequency comparison

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Fig. 14
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Total power versus clock power

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Fig. 15
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LOGISIM modeling of a processor

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Increase in the power consumption and heat dissipation will lead to higher costs exhibiting different capabilities and performance levels. After modifying the interfaces across various benchmarks, heterogeneous multi-core architectures are designed from previously implemented processor cores. The experimental results show clear phased behavior with significant variation in the frequency.

5 Conclusion

The proposed architecture CEMulti-core wireless sensor network (CEMWSN) performs information fusion, encryption, network coding with increased computational power. The various application domains, such as wireless video, satellite-based sensor networks, space shuttle sensor networks, aerial-terrestrial and hybrid sensor networks are benefited in a wider way. The parallelized information from XILINX application reveals that the Multi-core embedded sensor nodes with scheduler provides better scalability and performance than the simple MIPS processor for a variety of applications. The research challenges and future opportunities include computer-vision, energy harvesting with near-threshold computing.