1 Introduction

In a few years, complementary meta-oxide semiconductor (CMOS) technology has been widely used for designing different circuits [1,2,3,4]. However, due to its physical limitations, such as short channel effect, impurity variation, and heat, the CMOS technology is expected to encounter some challenges for further development in future [5,6,7]. To overcome CMOS constraints, the novel technology of quantum-dot cellular automata (QCA) has been promising for the next ICs generation [8,9,10]. The simplest element in QCA technology is a square-shaped cell where four quantum dots are located in its four corners [11, 12]. Information is transferred by Coulomb's interactions between the cells instead of the electric current [13,14,15]. Two stable arrangements are formed with respect to Coulomb repulsion force: P = ‘ + 1’ and ‘P = -1’ which indicate binary values ‘1’ and ‘0’, respectively [16,17,18,19,20,21]. In this respect, different implementations have been designed by three inputs majority gate and inverter gate [22, 23]. Totally, unlike the CMOS circuits, the QCA clocking mechanism is obtained through the electric field [24,25,26,27,28,29]. Clocking in QCA plays two important roles: providing cells with energy and controlling the circuit data flow [30,31,32]. The polarization of cell that starts in the Switch phase (the ascending edge), continue to the extent that the cell becomes fully polarized [8, 33, 34]. In the hold phase that is considered as the highest level, the cell polarization will be maintained. Then, in the third phase, Release (the descending edge), the cell loses some of its polarization [1, 35, 36]. In the last phase, namely the Relax phase with the lowest level of the clock pulse, the cell is kept in an unpolarized state [37,38,39].


The contributions of the current work are:

  • Designing a novel 4:1 QCA MUX and 8:1 QCA MUX based on 2:1 QCA MUX

  • Designing a novel one bit RAM memory based on two proposed of 2:1 QCA MUX

  • Verifying the proposed 2:1 QCA MUX design using physical proofs.

  • Investigating the proposed designs in terms of number of cell, clock latency and area.

  • Analyzing the power consumption of the proposed designs using the QCAPro tool.

This study is organized as follows. In the Sect. 2, provides a discussion of the previous related works on of the QCA MUX and QCA RAM memory circuits. The proposed QCA MUX and QCA RAM memory are introduced in Sect. 3. The proposed QCA layouts along with simulation results are introduced in Sect. 4. Besides, comparisons are showed. Finally, this paper ends with the conclusion in Sect. 5.

2 Related works

In this section, a review of 2:1 QCA multiplexer circuits and single-bit QCA RAM memory circuits is presented [40,41,42]. A MUX is one of the most widely used combinational circuits that acts as a selector [23, 43, 44]. In general, a 2n:1 MUX has 2n inputs, n selection lines, and an output that can transfer one of the inputs to the output according to the values of its selections lines [22, 45, 46].

The 2:1 QCA MUX architecture, as presented in [24, 25, 47,48,49,50,51], is based on the block diagram as depicted in Fig. 1. These architectures include two AND gates, one OR gate, and an inverter gate.

Fig. 1
figure 1

Block diagram schematic of a 2:1 MUX

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Therefore, the logic function is expressed by Eq. (1):

$$F = A \cdot \overline{S} + B \cdot S$$
(1)

In additional, there are several QCA designs for the 2:1 QCA multiplexer [24, 25, 47,48,49,50,51] which are reviewed in the following section:

A 2:1 QCA multiplexer has been presented by Teodósio et al. in QCA technology, which includes three inputs majority gates and one inverter gate [47]. It is a multi-layer design with 88 cells and occupied area of 0.14 as well as 1 delays. The main disadvantages of this design are being multi layered, use of high number of cells counts and high occupied area, also in another design which includes three inputs majority gates. It is a single-layer design with 144 cells and occupied area of 0.28 as well as 2 delays. The main disadvantages of this design are use of high number of cells counts and high occupied area. The layout of the proposed designs is shown in Fig. 2a, b, respectively. In another study, a 2:1 QCA multiplexer has been presented by Kim et al. in QCA technology, which includes three inputs majority gates and one inverter gate [48]. It is a single-layer design with 46 cells and occupied area of 0.08 as well as 1 delays. Its main disadvantage is high number of cell counts. The layout of the proposed design is shown in Fig. 2c. Mardiras et al. [49] proposed a 2:1 QCA multiplexer in QCA technology, which includes two AND, two OR and an inverter gate. It is a single-layer design with 67 cells and occupied area of 0.14 and 4 delays. One of the advantages of this design is being single layer and its main disadvantage is high number of cell counts. The layout of the proposed design is shown in Fig. 2d. Asfestani et al. [50] proposed a 2:1 QCA multiplexer in QCA technology, which includes two fixed polarization cells without any conventional gates. It is a single-layer design with 12 cells and occupied area of 0.01 and 1 delays. The advantages of this design are low latency and low occupied area. The layout of the proposed design is shown in Fig. 2e.

Fig. 2
figure 2

The cellular designs of 2:1 QCA MUXs presented in a [47], b [47], c [48], d [49], e [50], f [25], g [24] and [51]

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In another study, a 2:1 QCA multiplexer has been presented by Jeon in QCA technology, which includes AND gate, OR gate and one inverter gate [25]. It is a single-layer design with 13 cells and occupied area of 0.01 as well as 1 delays. The layout of the proposed design is shown in Fig. 2f. A 2:1 QCA multiplexer has been presented by Jeon in QCA technology, which includes three AND gates, and three inverter gates [24]. It is a single-layer design with 19 cells and occupied area of 0.02 as well as 2 delays. The layout of the proposed design is shown in Fig. 2g. Finally, a 2:1 QCA multiplexer has been presented by Song et al. in QCA technology, which includes AND gate, OR gate and one inverter gate [51]. It is a single-layer design with 13 cells and occupied area of 0.01 as well as 2 delays. The layout of the proposed design is shown in Fig. 2h.

In Fig. 2, several single-layer and multi-layer 2:1 QCA MUX are provided.

In general, there are two different approaches to design RAM memory cells: a loop-based approach and a line-based approach. In a loop-based RAM, the storage system is achieved using a loop, whereas in a line-based RAM design, the line is used to save the prior value of the output.

In the following section, the existing works based on the design of RAM cell designs [51,52,53,54,55] have been reviewed.

In reference [51], a QCA RAM memory cell has been proposed based on the loop architecture and consisting of two three-input majority gates, one inverter and one 2–1 multiplexer, as shown in Fig. 1. Its feedback loop is constructed by connecting output port with one input port marked with “0” in the 2–1 multiplexer. In fact, the modified multiplexer is a high voltage sensitive D-latch.

In Fig. 3, a RAM memory cell is shown in QCA, which is based on the loop architecture, manufactured based on the SR-Latch [52]. The proposed design has 100 cells and requires 12 clock phases. As shown in Fig. 4, this design has ‘Input’, ‘Write/Read’, and ‘Select’ inputs and lacks ‘Set’ and ‘Reset’ abilities. When ‘Select = 1’ and ‘Write/Read = 0’, the RAM cell content does not alter and can be read, but when ‘Select = 1’ and ‘Write/Read = 1’, the input value of the ‘Input’ will be stored in the cell.

Fig. 3
figure 3

RAM cell presented in reference [51] a circuit diagram and b QCA layout

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Fig. 4
figure 4

RAM cell presented in reference [52] a circuit diagram and b QCA layout

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In addition, according to Fig. 5, a RAM memory cell is provided in QCA, which is based on the loop architecture and is performed based on a D-Latch [52]. The proposed design consists of 63 cells and requires eight clock phases.

Fig. 5
figure 5

RAM cell provided in reference [52] a circuit diagram and b QCA layout

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In reference [53], a QCA RAM memory cell has been proposed based on the loop architecture and consisting of two 2:1 QCA multiplexers, such that one of these multiplexers acts as a D-latch and inserts the output signal into the input signal of the other multiplexer. The provided design has ‘Set’ and ‘Reset’ abilities. When ‘Write/Read = 1’, the value of ‘Input’ or ‘Set/Reset’ can be inserted into the output. When ‘Select = 0’, the value of ‘Set/Reset’ is inserted; otherwise, ‘Input’ value will be inserted. The circuit and cellular diagram of the proposed design are shown in Fig. 6. As can be observed, the proposed design consists of 109 cells and needs seven clock phases.

Fig. 6
figure 6

The second presented RAM cell in [53] a circuit diagram and b QCA layout

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In Reference [54], a RAM memory cell in the QCA is introduced having ‘Set’ and ‘Reset’ abilities. This design is based on the loop mechanism and consists of 3-input majority gates and one 5-input majority gate. When ‘Select’ and ‘Write/Read’ inputs are activated, the input value can be inserted into the output by fixing ‘Set’ and ‘Reset’ values to ‘0’ and ‘1’, respectively. When ‘Select’ is disabled, the memory output can be set and reset by fixing the ‘Reset’ and ‘Set’ signals to ‘0’ and ‘1’, respectively. The circuit diagram and QCA cell of the presented design are shown in Fig. 7. It can be observed in this figure that this design consists of 88 cells and requires six clock phases.

Fig. 7
figure 7

The second presented RAM cell in [54] a circuit diagram and b QCA layout

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In Reference [55], a RAM memory is proposed in the QCA, based on the loop approach and consisting of two 2:1 multiplexers. In this design, the multiplexers provided in the reference [50] have been used. When ‘Select’ signal is disabled (‘Select = 0’), one out of the ‘Set’ or ‘Reset’ operations can be performed. On the other hand, upon activating the ‘Select’ signal, one of the actions out of the ‘Read’ or ‘Write’ can be done. The circuit diagram and cellular design of the presented design are shown in Fig. 8.

Fig. 8
figure 8

The second presented RAM cell in [55] a circuit diagram and b cellular design

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3 Proposed QCA designs

In this part, at first, an inimitable 2:1 QCA multiplexer with ultra-low number of cells is proposed. Then, using the proposed design, 4:1 and 8:1 QCA MUX designs are developed. In addition, some physical proofs are provided to confirm the correct function of the proposed design. Finally, with the proposed 2:1 QCA multiplexer, an efficient RAM cell is proposed.

3.1 The proposed QCA MUX

The circuit diagram and QCA cellular of the proposed 2:1 MUX are illustrated in Fig. 9. This design is based on the cellular interactions and can produce the correct output. As noted in Fig. 9, the proposed QCA multiplexer consists of 10 cells with an occupied area 0.004 μm2, and its output is generated after 0.5 clock cycles.

Fig. 9
figure 9

The proposed 2:1 MUX a circuit diagram and b cellular layout

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The physical proofs To check the precision of the proposed 2:1 MUX, the circuit‘s output should be considered for all of the combinations. We only check the precision of the MUX for the input vector of (S, I0, I1) = (1, 1, 0).

The kink energy between two electron charges is calculated through Eq. 2 [56, 57]:

$$U = \frac{{kq_{i} q_{j} }}{r}\left( J \right)$$
(2)

where U is kink energy, k is Coulomb’s constant, \(q_{i} q_{j}\) are electron charges, and r is the distance between two electron charges. By replacement of k and q values, U is calculated using Eq. 3 [56, 57]:

$$U = \frac{{9 \times 10^{9} \times \left( {1.6} \right)^{2} \times 10^{ - 38} }}{r} = \frac{{23.04 \times 10^{ - 29} }}{r}$$
(3)

Figure 10 illustrates the electron arrangement of a cellular network that affects the output cell in the radius of less than 60 nm with two different polarities for the output cell.

Fig. 10
figure 10

The cellular lattice affecting the output cell considering polarities of a “1” and b “0” in output cell

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At first, kink energy between e1 to e18 electrons is calculated by the electrons ex and ey in Fig. 10a, b through Eq. 3. The calculated kink energies for the two states in Fig. 10 are presented in Tables 1 and 2, respectively.

Table 1 Kink energies between electrons e1 to e18 with electrons ex and ey in Fig. 5a
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Table 2 Kink energies between electrons e1 to e18 with electrons ex and ey in Fig. 5b
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The results in Tables 1 and 2 show the total electrostatic energy in Fig. 10a is lower than Fig. 10b. It means that the output cell of Fig. 10a is more stable than Fig. 10b and it verifies the correct direction of the proposed MUX’s cells.

Moreover, the output equation of the 4:1 MUX with the inputs I0, I1, I2 and I3 as well as the select lines S1 and S0 is expressed in Eq. (4).

$${\text{Out}} = \overline{S1} \overline{S0 } I0 + \overline{S1} S0 I1 + S1 \overline{S0} I2 + S1S0 I3$$
(4)

The schematic of the circuit and the QCA cellular of the proposed 4:1 MUX are shown in Fig. 11. As illustrated in Fig. 11, the proposed 4:1 MUX consists of 49 cells and requires six clock phases.

Fig. 11
figure 11

The proposed 4:1 QCA MUX a circuit diagram and b cellular layout

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Finally, the output equation of a 8:1 MUX with the inputs I0, I1, I2, I3, I4, I5, I6 and I7 as well as the choose lines S2, S1 and S0 is expressed in Eq. (5).

$$\begin{aligned} {\text{Out}} & = \left( {\overline{S2} \overline{S1} \overline{S0} } \right)I0 + \left( {\overline{S2} \overline{S1} S0} \right)I1 + \left( {\overline{S2} S1\overline{S0} } \right)I2 + \left( {\overline{S2} S1S0} \right)I3 \\ & \quad + \left( {S2\overline{S1} \overline{S0} } \right)I4 + \left( {S2\overline{S1} S0} \right)I5 + \left( {S2S1\overline{S0} } \right)I6 + \left( {S2S1S0} \right)I7 \\ \end{aligned}$$
(5)

The schematic of the circuit and the QCA cellular of the proposed 8:1 QCA MUX are showed in Fig. 12. As indicated in Fig. 12, the proposed 8:1 QCA MUX includes of 135 cells and needs nine clock phases.

Fig. 12
figure 12

The proposed 8:1 QCA MUX a circuit diagram and b cellular layout

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3.2 The proposed QCA RAM cell

This section provides an efficient QCA RAM cell using the proposed 2:1 QCA MUX design. The circuit and QCA cellular of the proposed RAM with four operations including ‘Set’, ‘Reset’, ‘Write’ and ‘Read’ are illustrated in Fig. 13. ‘Select’, ‘\({\text{Set}}/\overline{{{\text{Reset}}}}\)’, ‘\({\text{Write}}/\overline{{{\text{Read}}}}\)’, and ‘Input’ are considered as the input signals and ‘Output’ is the output signal. The operation of the proposed RAM is controlled by ‘Select’ signal, such that by activating any one of them, either ‘Set/Reset’ or ‘Read/Write’ operations can be performed.

Fig. 13
figure 13

The proposed RAM cell with set and reset abilities using the proposed 2:1 QCA MUX a circuit view and b QCA layout

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When ‘Select’ signal has been activated and ‘\({\text{Write}}/\overline{{{\text{Read}}}}^{^{\prime}}\)’ signal is set to ‘1’, the input data are inserted into the output, and subsequently, the write operation will be done. In this operation, the ‘Set/Reset’ and the previous output values are “Don't Care”. In addition, when the ‘Select’ signal is activated to ‘1’ and the '\({\text{Write}}/\overline{{{\text{Read}}}} { }\)' signal is set to '0', the previous output value will be inserted into the output and as a result, the read operation will be done. The '\({\text{ Set}}/\overline{{{\text{Reset}}}} { }\)' value, in this operation, is “Don't Care”.

When the 'Select' signal is inactive and the '\({\text{ Set}}/\overline{{{\text{Reset}}}}\)' signal is set to '1', the '\({\text{Set}}/\overline{{{\text{Reset}}}}\)' value will be inserted into the output and subsequently, the set operation will be performed. In addition, the 'Reset' operation is performed by setting the 'Select' and '\({\text{Set}}/\overline{{{\text{Reset}}}}\)' signals to '0'. The '\({\text{Write}}/\overline{{{\text{Read}}}} { }\)', 'Input', and previous1output values in these two operations are set to "Don't Care". The full operation of the proposed QCA RAM cell is presented in Table 3.

Table 3 Operation of the proposed QCA RAM cell design
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Thus, the output function can be expressed by Eq. (6):

$$\begin{aligned} {\text{Output}} & = \overline{{{\text{Select}}}} \left[ {{\text{Set}}/\overline{{{\text{Reset}}}} } \right] + {\text{Select}}\left[ {\left( {\overline{{{\text{Write}}/\overline{{{\text{Read}}}} }} } \right) P0 } \right. \\ & \quad \left. { + \left( {\overline{{{\text{Write}}/\overline{{{\text{Read}}}} }} } \right){\text{Input}}} \right] \\ \end{aligned}$$
(6)

As indicated in Fig. 13, the proposed RAM includes of 26 cells and requires four clock phases.

As can be seen, a QCA RAM can be easily implemented by putting two 2:1 QCA MUX together. The proposed single-layer layout consists of 26 cells with an occupied area 0.03 μm2 so that the output is produced after 1.00 clock cycles.

4 Simulation results and discussion

This section, QCADesigner version 2.0.3 has been used to simulate proposed designs [37]. In this paper, the “Bistable Approximation Engine” is used. All parameters and simulation conditions have default values of the software.

The simulation waveforms are presented in Fig. 14 for the proposed 2:1 QCA MUX. The simulation waveforms confirm that the proposed single-layer QCA multiplexer performs well and its output is obtained after two clock phases.

Fig. 14
figure 14

The simulation waveforms for the proposed single-layer 2:1 QCA MUX

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The simulation waveforms are presented in Fig. 15 for the proposed 4:1 QCA MUX. The simulation waveforms confirm that the proposed single-layer multiplexer performs well and its output is obtained after six clock phases.

Fig. 15
figure 15

The simulation waveforms for the proposed single-layer 4:1 QCA MUX

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In this section, the simulation waveforms of the proposed RAM memory have been presented. The simulation waveforms of the proposed RAM are presented in Fig. 16. As observed, three different cases A, B and C, are intended to accurately describe the function of the proposed RAM.

Fig. 16
figure 16

Simulation waveforms of the proposed single-layer QCA RAM memory

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In case A, when the 'Select' signal is disabled or set to '0', the '\({\text{Set}}/\overline{{{\text{Reset}}}} { }\)' value is transmitted to the output after one clock cycle resulting in the 'Set' and 'Reset' operations.

In case B, when the 'Select' signal is activated and the '\({\text{Write}}/\overline{{{\text{Read}}}} { }\)' has been set to '1', the 'Input' signal is transmitted to the 'Output' after one clock cycle, and subsequently, the write operation is performed.

In case C, when the 'Select' is enabled (or set to 1') and '\({\text{Write}}/\overline{{{\text{Read}}}} { }\)' is set to '0', the previous output value is inserted into the output after one clock cycle and thus, the 'Read' operation is performed. The simulation waveforms of the proposed RAM are presented in Fig. 16.

The comparison of the proposed 2:1 QCA MUX with the pervious MUX designs is presented in Table 4; these have been compared in terms of the complexity, clock latency and area (vs.\({\mu m}^{2}\)).

Table 4 Comparison table of 2:1 QCA MUXs
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As it is observed, the proposed 2:1 QCA MUX shows 16.66% improvement in consumed cells relative to the best currently available single-layer multiplexer. In addition, the proposed scheme shows 54.54% improvement relative to the best multi-layer multiplexer.

Moreover, a comparison of the proposed 4:1 QCA MUX with the existing MUX designs is presented in Table 5.

Table 5 Comparison table of 4:1 QCA MUXs
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As it is observed, the proposed 4:1 QCA MUX shows 19.67% improvement in consumed cells relative to the best currently available single-layer multiplexer. In addition, the proposed scheme shows 47.87% improvement relative to the best multi-layer multiplexer.

Furthermore, a comparison of the proposed 8:1 QCA MUX with the existing multiplexer designs is presented in Table 6.

Table 6 Comparison table of 8:1 QCA MUXs
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As indicates in Tables 4, 5 and 6, the proposed QCA multiplexer designs have the minimum cell counts as compared to the existing designs. The proposed designs have lesser complexity and occupy area. The occupied area of the proposed QCA 8:1 multiplexer is 0.12 μm2, which is lesser than many of the previous designs. Moreover, the proposed 8:1 QCA MUX shows 22.85% improvement in consumed cells relative to the best currently available single-layer QCA MUX. In addition, the proposed scheme shows 72.67% improvement relative to the best multi-layer QCA MUX.

A comparison of the proposed RAM cell design with the previous designs has been presented in Table 7. This table contains information regarding the cell counts, types of wire crossings, and the number of constant values. The results show that the proposed design has improved in terms of the cell count, occupied area, and delay in comparison with the previous designs [52,53,54,55, 64] and therefore, is superior to the previous designs.

Table 7 Comparison table of the proposed QCA RAM cell designs
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The proposed RAM scheme has improved by 25% and 7.14% in terms of the cell count and occupied area, respectively, as compared to the previous design as mentioned in reference [55].

In addition, a results of the power consumption of the proposed 8:1 QCA MUX and QCA RAM memory are being done using the QCAPRO tool [65].

The results of the power dissipation maps for the proposed 8:1 QCA multiplexer with the previous designs [50, 58, 62] at three different levels of tunneling energy (0.5 EK, 1 EK, and 1.5 EK) are provided in Table 8.

Table 8 Energy consumption analysis of the 8:1 QCA multiplexers
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In addition, energy dissipation maps of the proposed design with a tunneling energy of 0.5 EK are presented in Fig. 17.

Fig. 17
figure 17

Energy dissipation map at 2 K and tunneling energy of 0.5 EK for the proposed 8:1 multiplexer in QCA

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As presented in Table 9, the proposed 8:1 QCA MUX has a much lesser power consumption than the other designs. The analysis results of the power consumption for the proposed circuit as comparison with the previous design in reference [50] at three different levels of tunneling energy (0.5 EK, 1 EK, and 1.5 EK) reveal a decrease in the energy consumption by 47.39%, 36.96%, and 31.66%, respectively.

Table 9 Energy consumption analysis of the proposed QCA RAM
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Moreover, the analysis results of the power consumption for the proposed QCA RAM memory in comparison with the previous designs [55, 66] at three several levels of tunneling energy (0.5 EK, 1 EK, and 1.5 EK) are presented in Table 9.

Moreover, the energy dissipation maps for the proposed design with a tunneling energy of 0.5 EK are presented in Fig. 18.

Fig. 18
figure 18

Energy dissipation map at 2 K and tunneling energy of 0.5 EK for the proposed QCA RAM cell

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The analysis results of the power consumption for the proposed circuit as comparison with the previous design in reference [55] at three different levels of tunneling energy (0.5 EK, 1 EK, and 1.5 EK) reveal a decrease in the energy consumption by 10%, 12.82%, and 6.25%, respectively.

5 Conclusion and future works

In this paper, an optimal single-layer 2:1 QCA MUX is proposed, which includes of only 10 cells and can produce a correct output based on the explicit interaction of cells. Subsequently, with the proposed design, 4:1 and 8:1 QCA MUX designs were proposed to have a lowest area. The results of the comparisons of the proposed multiplexer designs with the previous ones showed that the proposed designs are more efficient than the best of the previous designs. For example, the proposed 8:1 QCA MUX showed improvements of 22.86% and 77.8% in terms of the cell count, respectively, in comparison with the best single-layer and multi-layer multiplexers among the previous designs. In the this study, based on the two proposed 2:1 QCA multiplexers, a novel and efficient single-layer QCA RAM design with 'Set' and 'Reset' abilities was proposed. The results of the simulations indicated that the expected outputs were corrected. The proposed design is more efficient than the previous designs in terms of complexity cell counts, occupied area and delay. In addition, the QCAPro power consumption analysis tool was used to measure the power dissipation. In future work, the proposed designs can be used as a constructive block in the design of circuits with higher complexity, and design of high performance systems such as microprocessor, compressor, and divider.