Abstract
This paper presents Model Algebra (MA), a formalism for representing SoC designs at system level. We define the objects and composition rules of MA and show how system level models can be represented as expressions in this formalism. The formalism is applied to a system level design methodology, where design decisions are used to gradually transform the functional specification model of the system to a transaction level model with components and communication structure. Each transformation is represented as a manipulation of a model algebraic expression, and proven for correctness using the laws of model algebra. These laws are based on the well defined execution semantics and notion of functional equivalence for MA models. Our approach promises significant savings in the verification of system level models because only the first model needs to be verified using conventional techniques. All transformations of this model, derived using MA laws, are proven to be functionally equivalent.
Article PDF
Similar content being viewed by others
Avoid common mistakes on your manuscript.
References
G. Kahn, The Semantics of a Simple Language for Parallel Programming, Info. Proc., pp. 471–475 (August 1974).
Abdi S., Gajski D. (2004). System Level Verification with Model Algebra, Technical Report CECS-TR-04-29, University of California, Irvine
C. Hoare, Communicating Sequential Processes, Prentice Hall (1985).
R. Milner, A Calculus of Communicating Systems, Springer (1980).
Harel D. Statecharts: A Visual Formalism for Complex Systems. Science of Computer Programming. 8(3): 231–274 (June 1987), url citeseer.nj.nec.com/harel87statecharts.html.
J. Jorgensen and L. Kristensen, Verification of Colored Petri Nets Using State Spaces with Equivalence Classes, Proceedings of the Workshop on Petri Nets in System Engineering, pp. 20–31 (September 1997).
X. Chen, H. Hsieh, F. Balarin, and Y. Watanabe, Case Studies of Model Checking for Embedded System Designs, Third International Conference on Application of Concurrency to System Design, pp. 20–28 (June 2003).
S. Rajan, Correctness of Transformations in High Level Synthesis, International Conference on Computer Hardware Description Languages and their Applications, pp. 597–603 (June 1995).
Camposano R. (1990). Behavior-Preserving Transformations for High-Level Synthesis. Proceedings of the Mathematical Sciences Institute workshop on Hardware Specification, Verification and Synthesis: Mathematical Aspects. Springer-Verlag, New York, Inc. pp. 106–128
Middlehoek, A Methodology for the Design of Guaranteed Correct and Efficient Digital Systems, IEEE International High Level Design Validation and Test Workshop (November 1996).
H. Saito, T. Ogawa, T. Sakunkonchak, M. Fujita, and T. Nanya, An Equivalence Checking Methodology for Hardware Oriented C-based Specifications, IEEE International High Level Design Validation and Test Workshop, pp. 274–277 (October 2002).
D. Gajski, J. Zhu, R. Domer, A. Gerstlauer, and S. Zhao, SpecC: Specification Language and Methodology, Kluwer Academic Publishers (January 2000).
T. Sakunkonchak and M. Fujita, Verification of Synchronization in SpecC Description with the Use of Difference Decision Diagrams, Proceedings of the Forum for Design Languages (September 2002).
E. Barros and A. Sampaio, Towards Provably Correct Hardware/Software Partitioning Using Occam, Proceedings of the International Workshop on Hardware–Software Codesign, pp. 210–217 (June 2004).
S. Abdi and D. Gajski, Automatic Generation of Equivalent Architecture Model from Functional Specification, Proceedings of the Design Automation Conference (June 2004).
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Abdi, S., Gajski, D. Verification of System Level Model Transformations. Int J Parallel Prog 34, 29–59 (2006). https://doi.org/10.1007/s10766-005-0001-y
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10766-005-0001-y