Abstract
This paper presents a robust and low-power single-ended robust 11T near-threshold SRAM cell in 10-nm FinFET technology. The proposed cell eliminates write disturbance and enhances write performance by disconnecting the path between cross-coupled inverters during the write operation. FinFETs suffer from width quantization, and SRAM performance is highly dependent to transistors sizing. The proposed structure with minimum sized tri-gate FinFETs operates without failure under major process variations. In addition, read disturbance is reduced by isolating the storage nodes during the read operations. To reduce power consumption this cell uses only one bit-line for both read and write operations. The proposed SRAM cell reduces write delay, average power and PDP by 20, 78 and 62%, respectively as compared to the 9T single-ended SRAM cell. Moreover, the proposed cell enhances write static noise margin by 33% under process variation.
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1 Introduction
The ever increasing demand for use of battery operated devices in recent years has forced designers to consider power as a key parameter in circuit design. To reduce power consumption, several techniques have been proposed. Reducing supply voltage (VDD) is an effective way to decrease both dynamic and static power consumptions, if circuit can still meet the system requirements [1, 2]. Static random access memory (SRAM) occupies a significant design area in modern digital and mixed-signal integrated circuits and considerably contributes to the whole system power consumption and delay. Consequently, design of a low-power near-threshold SRAM cell is quite important [3,4,5,6,7,8].
Near-threshold circuits are popular due to their very low power consumption. However, they also increase the risk of failure and are more susceptible to process variation due to their low supply voltage. Scaling the technology node to deep sub-micron and nanoscale have caused a significant increase in short channel effects and have intensified process variations [4]. Transistors’ strength ratios and threshold voltage (V th ) are critical for stability and performance of SRAMs and lead to extreme challenges in designing a low-power and robust SRAM cell.
Various SRAM cells have been proposed for low-power applications [3, 9,10,11,12,13]. The major goals of these designs are reduction of power consumption and increasing static noise margin (SNM) by isolating the storage nodes from the read path to enhance the read SNM compared to the Hold SNM.
A single-ended (single bit-line) SRAM is a cell that uses only one bit-line to perform its write or read operations. Using one bit-line leads to the reduction of area and dynamic power consumption. As a bit-line has a large capacitance, by eliminating a bit-line a large capacitor is reduced from the design. By performing a read or write operation, a large capacitance must be charged and discharged which consumes a lot of power, and omitting this capacitor can save almost half of the dynamic power dissipation. It even helps in saving static power by omitting a potentially leaky bit-line which is shared between numerous cells. However, as a single-ended cell has only one bit-line to perform the write operation, its write margin is degraded. Some methods have already been presented to improve the write static noise margin (WSNM) by using a write assist circuit which comes at the cost of extra transistors and additional control circuitries [4]. Another way is to use transistors with multiple threshold voltages and different sizes to change the strength of transistors to help the circuit with its write operation [11]. However, it increases fabrication costs and is not suitable for FinFET-based circuits, due to width quantization limit in FinFETs.
In this paper, a novel single-ended SRAM cell for robust and low-power near-threshold applications is proposed. In this cell, read stability is improved by decoupling the read path from the storage nodes. Moreover, using a single bit-line improves power consumption. In the proposed cell, all transistors can be considered minimum-size which is very important for FinFET-based design due to the width quantization restriction in FinFET technology.
The rest of this paper is organized as follows: Sect. 2 reviews the existing single bit-line cells. The proposed SRAM is introduced and described in Sect. 3. The simulation results and comparisons are presented in Sect. 4 and finally Sect. 5 concludes the paper.
2 An overview of the previous SRAM cells
2.1 5T SRAM cell
Figure 1(a) shows the conventional 5T SRAM cell [11]. This cell uses one bit-line for both read and write operations but suffers from read and write disturbances. To achieve an acceptable WSNM, some transistors in this cell need to be stronger than other transistors which is in contrast to RSNM which needs the opposite ratios with respect to WSNM ratios. To achieve an acceptable RSNM and WSNM, this cell needs to use transistors with different threshold voltages and exact transistor sizing. However, due to width quantization effect in FinFET transistors, the latter is not possible in this technology [12].
Existing single-ended SRAM cells. a 5T, b 8T, c 9T single-ended NBL, d asymmetric 8T, e near-threshold 7T
2.2 8T SRAM cell
The 8T SRAM cell, which is shown in Fig. 1(b) [13], uses two bit-lines for the write operation and a single bit-line scheme for the read operation. It eliminates read disturbance by decoupling storage nodes from read path during the read operation. However, existence of an extra read bit-line (RBL) increases design complexity and power consumption. As the probability of charging and discharging of BLs per operation is reduced, the average power consumption, which is dominated by the dynamic power consumption, decreases as compared to the conventional SRAM cells.
2.3 9T single-ended data-aware write negative bit-line (NBL) SRAM cell
The 9T single-ended NBL SRAM cell, which is illustrated in Fig. 1(c) [1], uses only a single BL for both read and write operations. This cell eliminates the read disturbance, and dissipates lower standby power because of its single BL structure. However, it has difficulty in performing write operation, due to its single bit-line write scheme. To meet this problem, this cell uses a virtual ground, and to benefit from higher strength during the write operation, it uses a negative bit-line scheme. It always discharges the bit-line for the write operations and always writes ‘0’ in the cell. However, to perform both ‘0’ and ‘1’ write operations, it writes the data specifically in Q or QB, respectively.
2.4 Asymmetric 8T SRAM cell
The single-ended asymmetric 8T SRAM cell uses only one bit-line for both read and write operations, as shown in Fig. 1(d) [4]. This cell eliminates read disturbance by separating the read and write paths. By using one BL for both read and write operations, this cell reduces power consumption. In addition, it uses a read/write assist circuit, which leads to a superior write SNM. To perform the read operation, this cell activates the RWL line and forces the WWL line to ‘0’.
As it can charge or discharge the BL line, there is no need for pre-charging BL to perform the read operation. However, by using an nMOS transistor as the read access device, this cell cannot charge the BL line completely, but charges it to a level which is enough to be recognized as a ‘1’ in the read operation. The single-ended asymmetric 8T SRAM cell uses a virtual ground for its write operation. During the write operation, the virtual ground will adopt a voltage above 0 V, which makes the write operation easier. Although adding this virtual ground to the cell increases the design complexity and cost, it enhances the cell write SNM considerably.
2.5 Near-threshold 7T SRAM cell
Near-threshold 7T SRAM cell, shown in Fig. 1(e) [3], performs both read and write operations using one bit-line (BL). Similar to 9T SRAM cell, this cell is data-aware and uses two extra signals to perform its operations. The near-threshold 7T SRAM cell reduces read delay. However, it suffers from read disturbance due to existence of a charge sharing path between Q and BL nodes. This cell has a two-phase write operation and the control signals are forced to different voltages in each stage. However, it still suffers from write disturbance and is not reliable in the presence of process variations.
3 Proposed SRAM cell
3.1 Structure
The schematic and timing diagram of the proposed SRAM cell are shown in Fig. 2. The core of the cell consists of two cross-coupled inverters (M1, M2, M3, M4). Moreover, two pMOS devices (M5 and M6) are placed between the inverters feedback paths such that M6 is placed between the storage node Q and the output node of the left inverter (Q1) and M5 is placed between the storage node QB and the output node of the right inverter (Q2). In addition, the M7–M11 devices provide the read and write operations in this cell. The word line (WL) controls both read and write operations of the proposed cell such that when there is a write or read operation, the WL must be activated to execute the operation.
Proposed SRAM cell. a circuit schematic, b timing diagram
The write word line A (WWLA) controls the writing of ‘0’ and write word line B (WWLB) controls the writing of ‘1’ in the cell [1, 3]. The WWLA, WWLB and BL lines are column-based, while the word line (WL) is row-based. During the hold time, all three control signals are forced to ‘0’, which keeps M5 and M6 on, and the data will be held by the feedback path of the cross-coupled inverters.
3.2 Read operation
Figure 3 illustrates both read ‘0’ and ‘1’ operations of the proposed SRAM cell. For the read operation, at first, BL is needed to be pre-charged to VDD. Then, WL is assrted and both WWLA and WWLB remain at their inactive state. If the stored data is ‘0’, BL will be discharged through M9 - M11, and if the stored data is ‘1’, M9 will be in the cut-off region. Accordingly, there will be no path for BL to start discharging and therefore, it will remain at its pre-charged voltage. Due to the data isolation from read path in the proposed SRAM cell, the read SNM is as high as the hold SNM. The read SNMs of the proposed SRAM cell and the conventional 6T SRAM cell are shown in Fig. 4. The read SNM of the proposed design is 178 mV, while it is 80 mV for the conventional 6T SRAM cell at 0.45 V. Although the read SNM of the conventional cell can be increased by considerably modifying the transistors strength ratios, it occupies a lot of area in FinFET technology with a little gain for read SNM, due to the width quantization effect.
Read operation of the proposed SRAM cell. a Read ‘0’ operation, b Read ‘1’ operation
RSNM comparison of conventional 6T SRAM cell and the proposed SRAM cell
3.3 Write operation
The write operation scenarios of the proposed SRAM cell with data-aware column-based WWLs [3] are illustrated in Fig. 5. It is required to force BL to ‘0’ to perform the write operations for both ‘0’ and ‘1’. To execute the write ‘0’ operation, WWLB and WL are forced to VDD and WWLA remains forced to the ground. Accordingly, M6 will switch to cut-off mode and accordingly, the feedback path from the right inverter output to the left inverter input is cut and the node Q can be easily discharged through the M7 and M11 transistors without any contention from the right inverter. Moreover, the node QB, as the output of the left inverter, will be charged to VDD through M4 and M5 and accordingly ‘0’ is written on the cell. To reduce the writability degradation, caused by the two series-connected nMOS transistors, the feedback path is disconnected during the write operations.
Write operation of the proposed SRAM cell. a Write ‘1’ operation, b Write ‘0’ operation
Different metrics can be used for evaluating the writability of a SRAM cell, such as write SNM (WSNM). The WSNM is measured by combining the read and write voltage transfer characteristics (VTCs). A cell has the ability to perform a correct write operation when its WSNM is negative and read and write VTCs do not cross each other [10]. Figure 6 shows the write SNM of the proposed single-ended SRAM cells, which indicates its perfect writability with 225 mV WSNM at 0.45 V near threshold operation supply voltage.
WSNM Comparison of the proposed SRAM cell and 5T SRAM cell
3.4 Single bit-line to reduce power consumption
The proposed SRAM cell uses only one bit-line for both read and write operations. Many SRAM cells such as the conventional 6T SRAM cell and the cells presented in [14] and [15] use two bit-lines and a differential scheme for both read and write operations. The cells proposed in [15, 16] use differential bit-lines for write operation, and a single read bit-line for read operation. The probability of charging and discharging the bit-lines for different types of bit-line schemes for the read and write operations are given in Fig. 7. It is assumed that the probability of write operation is equal to the read operation [1] and the probability of storing data ‘0’ is 60% and the probability of storing data ‘1’ is 40% [14].
Probability of charging bit-line per operation
Using the single bit-line scheme for both read and write operations reduces the probability of bit-line charging per operation by 50% as compared to the case with differential bit-lines scheme for both read and write operations and 38% as compared to the case with differential bit-lines scheme for write operation and single bit-line scheme for read operation. As a result, the single bit-line scheme reduces the power consumption of bit-line per operation which is a large portion of the total power consumption, due to the large capacitance of bit-line.
3.5 Transistors strength ratios
For robust near-threshold operation, a SRAM cell needs to have high hold stability, read stability and writability, which are commonly evaluated by the SNM factor. The proposed cell provides all of these metrics by using minimum size FinFETs with normal threshold voltages. This is provided by the inserted pMOS transistors in the feedback path of the cross-coupled inverters. These two devices make the write operation very easy and due to the cut off path and eliminated force of the other inverter this cell can perform write operation with minimum size transistors.
4 Simulation results and comparisons
In this section, the proposed SRAM cell is simulated and compared with the previous related single-ended SRAMs using 10 nm common-gate FinFET technology [17]. Some of the important parameters for the utilized FinFETs are listed in Table 1. The BL capacitance is assumed to be 10 fF. The evaluations and comparisons are performed in terms of transient metrics including read delay, write delay, power consumption and power delay product (PDP) for an 8 × 8 SRAM array and DC metrics including read, write and hold SNMs for one cell.
The simulation results of the SRAM arrays, at 60° temperature and 0.45 V supply voltage are given in Table 2. In this table, the read access delay is assumed as the period between the activation of WL, when its voltage reaches to ‘VDD/2’, and the time at which the BL voltage discharges and its voltage reaches to ‘0.8 × VDD’ [11]. Due to using the same paths for read operation, both of the 9T single-ended NBL and proposed SRAM cells have approximately the same read delays. The asymmetric 8T SRAM cell uses a shorter path than the 9T and proposed SRAM cells. However, as the asymmetric 8T cell tends to charge the bit-line while the cell holds ‘1’, and due to incapability of passing a strong ‘1’ by an nMOS device, this operation takes a time approximately equal to which of the proposed SRAM and the 9T cells. The near-threshold 7T SRAM cell has much lower read delay in comparison with three other cells because it has a shorter path and it does not need to charge the bit-line (it just has to discharge it through two nMOS transistors). The proposed SRAM cell has a smaller RSNM than the 8T and 9T cells, due to incapability of passing a strong ‘0’ by pMOS transistors, but the difference is very small and does not threat circuit’s function. The near-threshold 7T SRAM cell has the worst RSNM which is 60% smaller than the proposed cell.
One of the most important features in a single-ended SRAM is write delay. The write delay is measured as the period between the activation of WL, when its voltage reaches ‘VDD/2’ and the time when the storage node’s voltage rises up (or down) to ‘VDD/2’. According to the results, the single-ended asymmetric 8T SRAM cell has the longest write delay among the SRAM cells. Moreover, the 9T single-ended SRAM cell uses a negative bit-line which accelerate the write operation of this cell. However, due to the force of the cross-coupled inverters in feedback path, this operation requires longer time than the proposed SRAM cell. Due to cutting off the feedback path, which eliminates the contention condition during the write operation, the proposed cell has a write delay far shorter than 9T and 8T SRAM cells. The write delay of the proposed cell is 5, 87 and 20% shorter than the 7T, 8T and 9T SRAM cells, respectively. The proposed cell has a shorter write delay than the other cells at different operating voltages as depicted in Fig. 8. It is noteworthy that the 7T cell has been designed specifically for low voltages and it does not work properly at higher voltages. Accordingly, the results for this cell are given only for the supply voltages lower than 0.6 V.
Write delay in different voltages
Furthermore, the WSNM of the proposed SRAM cell is the same as the 9T cell and is 5× and 2.8× wider than the 7T and 8T SRAM cells, respectively. As shown in Fig. 9, the proposed cell has also a considerably wider WSNM than 9T cell at upper operating voltages.
Write SNM at different voltages
The average power consumption of the proposed SRAM cell is about 30, 40 and 78% lower than the 7T, 8T and 9T SRAM cells, respectively which makes it a suitable option for portable applications with limited power budget. The proposed, 8T and 9T SRAM cells have the same number of charges and discharges for their bit-lines. However, as the proposed SRAM cell performs the write operation much faster than the other cells, the short circuit power is considerably reduced. The near-threshold 7T SRAM cell has lower short circuit power consumption, but it has a higher number of charges and discharges due to its two phase write operation. The power consumptions of the SRAMs in different operating voltages are given in Fig. 10.
Average power consumption in different voltages
According to Table 2, the 9T single-ended NBL cell consumes the lowest static power due to its extra VGND extra control signal. This signal is forced to VDD during the hold state and as a result there is no voltage difference between BL and VGND, which eliminates the current in this path. The near-threshold 7T cell has fewer transistors and a slightly lower static power in comparison with the proposed cell. The proposed cell has longer path between BL and GND than the asymmetric 8T SRAM cell and accordingly it has a lower static current in this path. It also has a longer path from VDD to GND in the cross-coupled inverters than both 9T and 8T SRAM cells due to the inserted PMOS transistors. In general, single-ended SRAM cells have lower static power consumption as compared to double-ended cells. Figure 11 shows the static power consumption of the SRAM cells at different operating voltages. At 0.45 V operating voltage, the proposed cell consumes 8 and 18% higher static power than 7T and 9T SRAM cells respectively, but it consumes %25 lower static power than 8T SRAM cell.
Static power consumption in different voltages
Systematic and random process variations are the most critical challenges in designing nanoscale circuits. Variations in the fin height (HFin), fin width (tFin) and channel length (L) are among the most important sources of parametric variation s in a FinFET-based circuit. Specifically, increment of tSi and reduction of L can considerably intensify the short channel effects such as drain induced barrier lowering (DIBL) and Vt roll-off and leads to considerably high leakage currents. Moreover, HFin dominantly determines the effective channel width and drive current of the device [18, 19]. These variations can significantly increase the power consumption and degrades the performance and robustness of the SRAM cells. In order to assess the effects of process variations, Monte Carlo simulations has been conducted with Gaussian distribution and ± 10% variations at the ± 3σ level.
The SNM variations of the cells under process variations are given in Table 3. The results indicate that although the hold and read SNMs of the proposed design experience slightly higher variations, it has a very lower write SNM variation as compared to the other designs. Figure 12 shows the write SNMs of the cells under process variations.
Write SNM of the cells at 0.45 V. a 8T, b 9T, c 7T, d proposed
Table 4 gives the maximum parametric variations of the SRAM cells under process variations. According to the results, the proposed SRAM cell experiences very lower parametric variations in most cases as compared to the other cells. For instance, from the average power point of view, the proposed SRAM cell has 92, 93 and 74% less variations than the 9T and 8T and 7T cells, respectively. Moreover, the PDP variation of the proposed SRAM cell is 96, 98 and 96% lower than the 9T, 8T and 7T cells. The PDP metric stands for the energy usage per operation and can be considered as an important parameter in a digital circuit. The Monte Carlo simulation results also show that the 9T, 8T and 7T SRAM cells show 10, 12 and 24% failure rates, respectively, while the proposed cell shows no failure during 1000 times simulation. Most of the failures occur during the write operation which is tightly related to the transistors aspect ratios in the previous SRAMs. However, the proposed SRAM cell provides a disturbance-free write operation which leads to a very small variation in the write operation and therefore makes the cell highly tolerant to process variations.
5 Conclusion
Near-threshold design has attracted a lot of attention due to its very low power consumption. This paper presents a robust and low-power single-ended 11T SRAM cell. This cell eliminates the read disturbance by decoupling the storage nodes from the read path, which is a common problem in the conventional SRAM cells. In addition, the proposed SRAM cell enhances the write SNM, as a common limitation in single-ended SRAMs, by inserting two pMOS devices in the feedback paths between the cross-coupled inverters. Most of the single-ended SRAM cells have a considerable write delay, which is highly reduced in the proposed cell. Furthermore, the WSNM of the proposed SRAM cell is significantly larger than those of the 7T, 8T and 9T SRAM cells, which is one of the most important parameters in single-ended SRAMs. In addition, the proposed SRAM cell consumes 30, 40 and 60% lower power as compared to the 7T, 8T and 9T SRAM cells, respectively. In addition, the proposed SRAM cell shows considerably lower parametric variations in the presence of major process variations compared to the previous designs. The simulation results confirm that the proposed SRAM cell is an efficient design solution for applications which operate at low voltages and need to maintain a reasonably high performance and robustness.
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Ensan, S.S., Moaiyeri, M.H. & Hessabi, S. A robust and low-power near-threshold SRAM in 10-nm FinFET technology. Analog Integr Circ Sig Process 94, 497–506 (2018). https://doi.org/10.1007/s10470-018-1107-7
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DOI: https://doi.org/10.1007/s10470-018-1107-7